Process for preparing a silicon-on-insulator substrate comprising an electric-charge trapping layer and having predetermined characteristics

TW202634978APending Publication Date: 2026-08-16SOITEC SA
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Patent Information

Application Number
TW114146326
Authority / Receiving Office
TW · TW
Patent Type
Applications
Current Assignee / Owner
Priority Date
2024-11-27
Filing Date
2025-11-27
Publication Date
2026-08-16

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Abstract

micrometres. The preparation process comprises a finishing sequence comprising an annealing step exposing the exposed face of the substrate to an inert or reducing atmosphere for at least
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