Control circuit for controlling light emitting element

Abstract

A control circuit for controlling a light emitting element. The control circuit includes a memory circuit, an operation circuit and a timer. The operation circuit calculates a unit period according to a set frequency and a number of scales of a duty cycle, and generates a unit count value according to the operation frequency and the unit period. The operation circuit stores the unit count value in the memory circuit. The timer controls the operation circuit to generate a control signal according to the unit count value stored in the memory circuit. The operation circuit controls the light emitting element using the control signal. The operation frequency is higher than the set frequency.

Description

[Technical Field]

[0001] The present invention relates to an electronic circuit, and more particularly to a control circuit for controlling a light-emitting element. [Previous Technology]

[0002] The light emission of current light-emitting elements can be controlled by a control circuit. However, the control circuit generates a control signal based on a fixed clock frequency. The frequency and period of the control signal cannot be changed. Therefore, the light emission of current light-emitting elements is based on a fixed frequency. The light emission mode of the light-emitting element is limited. [Summary of the Invention]

[0003] The present invention provides a control circuit for controlling light-emitting elements, which can generate a variety of control signals.

[0004] In one embodiment of the present invention, the control circuit includes a memory circuit, an arithmetic circuit, and a timer. The arithmetic circuit is coupled to the memory circuit. The arithmetic circuit receives a set frequency and the order of the operating cycle, calculates a unit cycle based on the set frequency and the order, and generates a unit count value based on the operating frequency and the unit cycle. The arithmetic circuit stores the unit count value in the memory circuit. The timer is coupled to the arithmetic circuit. The timer controls the arithmetic circuit to generate a control signal based on the unit count value stored in the memory circuit. The arithmetic circuit uses the control signal to control the light-emitting element. The operating frequency is higher than the set frequency.

[0005] Based on the above, the control circuit calculates the unit period according to the set frequency and order, generates a unit count value according to the operation frequency and unit period, and then generates a unit count value according to the operation frequency and unit period. The timer receives the unit count value and controls the operation circuit to generate control signals according to the unit count value. In this way, the control circuit can generate a variety of control signals.

Implementation Method

[0006] Some embodiments of the present invention will now be described in detail with reference to the accompanying drawings. Component symbols used in the following description are considered to be the same or similar components when they appear in different drawings. These embodiments are only a part of the present invention and do not disclose all possible implementations of the invention. More precisely, these embodiments are merely examples within the scope of the patent application of the present invention.

[0007] Please refer to Figure 1, which is a schematic diagram of a control circuit according to an embodiment of the present invention. In this embodiment, the control circuit 100 includes a memory circuit 110, an arithmetic circuit 120, and a timer 130. The arithmetic circuit 120 is coupled to the memory circuit 110. The arithmetic circuit 120 receives a set frequency FS and a duty cycle order SCL, calculates a unit period PUNIT based on the set frequency FS and the order SCL, and generates a unit count value CNT based on the arithmetic frequency FC and the unit period PUNIT. The arithmetic circuit 120 stores the unit count value CNT in the memory circuit 110. In this embodiment, the arithmetic frequency FC is higher than the set frequency FS.

[0008] In this embodiment, timer 130 is coupled to arithmetic circuit 120. Timer 130 controls arithmetic circuit 120 to generate control signal SC based on unit count value CNT stored in memory circuit 110. Arithmetic circuit 120 uses control signal SC to control light-emitting element LD.

[0009] It is worth mentioning that the control circuit 100 calculates the unit period PUNIT based on the set frequency FS and the order of the operating cycle SCL, and generates a unit count value CNT based on the operation frequency FC and the unit period PUNIT. The timer 130 receives the unit count value CNT and controls the operation circuit 120 to generate a control signal SC based on the unit count value CNT. Therefore, the control circuit 100 can change the frequency and / or waveform of the control signal SC based on the set frequency FS and the order of the operating cycle SCL. In this way, the control circuit 100 can generate various control signals SC.

[0010] In this embodiment, the set frequency FS is the frequency applicable to the light-emitting element LD. The order SCL is equal to the gray level applicable to the light-emitting element LD. That is, the order SCL is the number of different gray levels that the light-emitting element LD can achieve. For example, if the light-emitting element LD is designed to achieve 255 levels of brightness, the order SCL is equal to "255".

[0011] In this embodiment, the set frequency FS and the order SCL can be stored in the memory circuit 110. The set frequency FS and the order SCL can be input to the memory circuit 110, for example, through the control interface CI. However, the present invention is not limited to the source of the set frequency FS and the order SCL.

[0012] In this embodiment, the arithmetic circuit 120 responds to the start bit BS to calculate the unit count value CNT. For example, the memory circuit 110 responds to the arithmetic command CMD to provide the start bit BS. The arithmetic command CMD may be provided, for example, by the control interface CI. However, the present invention is not limited to the source of the arithmetic command CMD.

[0013] When the arithmetic circuit 120 receives the start bit BS, the arithmetic circuit 120 responds to the start bit BS receiving the set frequency FS and the order SCL from the memory circuit 110. Next, the arithmetic circuit 120 generates the unit count value CNT based on the set frequency FS, the order SCL and the arithmetic frequency FC.

[0014] In this embodiment, when the arithmetic circuit 120 is instructed to generate a control signal SC, the arithmetic circuit 120 reads the unit count value CNT from the memory circuit 110 and provides the unit count value CNT to the timer 130. In some embodiments, the timer 130 directly receives the unit count value CNT stored in the memory circuit 110.

[0015] In this embodiment, the light-emitting element LD may include a light-emitting unit (not shown) and a driving circuit (not shown) for driving the light-emitting unit. The driving circuit may drive the light-emitting unit according to the control signal SC. The light-emitting unit may be an LED or other element that can provide output light.

[0016] In this embodiment, the memory circuit 110 may be a storage medium capable of storing data. In this embodiment, the arithmetic circuit 120 may be, for example, a central processing unit (CPU), or other programmable general-purpose or special-purpose microprocessor, digital signal processor (DSP), programmable controller, application-specific integrated circuit (ASIC), programmable logic device (PLD), or other similar device.

[0017] Please refer to Figures 1 and 2. Figure 2 is an operation flowchart of the control circuit according to an embodiment of the present invention. In this embodiment, the operation flow S100 includes steps S110 to S140. In step S110, the arithmetic circuit 120 obtains the operation frequency FC, the set frequency FS, and the order SCL. Further, in this embodiment, the operation frequency FC can be the frequency of the clock of the arithmetic circuit 120. Therefore, the arithmetic circuit 120 itself can know the operation frequency FC. In addition, when the arithmetic circuit 120 receives the start bit BS, the arithmetic circuit 120 responds to the start bit BS receiving the set frequency FS and the order SCL from the memory circuit 110.

[0018] In step S120, the arithmetic circuit 120 calculates the product of the set frequency FS and the order SCL, and uses the reciprocal of the product as the unit period PUNIT. Specifically, the arithmetic circuit 120 can obtain the unit period PUNIT according to formula (1).

[0019] …Formula (1)

[0020] For example, the frequency FS is set to 30 kHz (but the invention is not limited thereto). The order SCL is equal to "255". Therefore, the unit period PUNIT is equal to 130.7 nanoseconds (ns).

[0021] In step S130, the arithmetic circuit 120 divides the unit period PUNIT by the reciprocal of the arithmetic frequency FC to obtain the unit count value CNT.

[0022] …Formula (2)

[0023] In other words, the arithmetic circuit 120 multiplies the unit period PUNIT by the arithmetic frequency FC to obtain the unit count value CNT. Specifically, the arithmetic circuit 120 can obtain the unit count value CNT according to formula (2).

[0024] For example, the operating frequency FC is equal to 60 MHz (however, this invention is not limited thereto). The unit period PUNIT is equal to 130.7 ns. Therefore, the unit count value CNT is equal to "7.84". The unit count value CNT can be approximated as an integer value. Therefore, the unit count value CNT is approximated as "8".

[0025] In step S130, the arithmetic circuit 120 stores the unit count value CNT into the memory circuit 110.

[0026] In step S140, the arithmetic circuit 120 stores the unit count value CNT in the memory circuit 110. When the arithmetic circuit 120 is instructed to generate a control signal SC, the arithmetic circuit 120 reads the unit count value CNT from the memory circuit 110 and provides the unit count value CNT to the timer 130. Furthermore, the timer 130 controls the arithmetic circuit 120 to generate the control signal SC based on the unit count value CNT.

[0027] For example, the control signal SC is a pulse-width modulation (PWM) signal. The unit count value CNT corresponds to the pulse width difference between two adjacent gray levels of the control signal SC. The timer 130 can trigger the arithmetic circuit 120 based on the unit count value CNT, causing the arithmetic circuit 120 to provide a high voltage value based on a first cycle of at least one unit count value CNT to generate a high voltage value portion of the control signal SC, and to provide a low voltage value based on a second cycle of at least one unit count value CNT to generate a low voltage value portion of the control signal SC.

[0028] For example, the higher the multiple of the unit count value CNT corresponding to the high voltage value and the higher the multiple of the unit count value CNT corresponding to the low voltage value, the lower the frequency of the control signal SC. The lower the multiple of the unit count value CNT corresponding to the high voltage value and the lower the multiple of the unit count value CNT corresponding to the low voltage value, the higher the frequency of the control signal SC.

[0029] For example, the unit count value CNT equals "8". The operation frequency FC can be the frequency of the clock of the operation circuit 120. Therefore, the pulse width difference between two adjacent gray levels of the control signal SC is equal to 8 times the period of the clock of the operation circuit 120. In other words, when the gray level corresponding to the control signal SC increases by "1", the width of the positive pulse of the control signal SC increases by 8 times the period of the clock of the operation circuit 120. When the gray level corresponding to the control signal SC increases by "2", the width of the positive pulse of the control signal SC increases by 16 times the period of the clock of the operation circuit 120.

[0030] It should be noted that the control circuit 200 can use the operating frequency FC and the unit count value CNT to implement the control signal SC with a set frequency FS. Once the set frequency FS of the control signal SC is changed and / or by the working cycle, the control circuit 200 can correspondingly change the unit count value CNT to implement the control signal SC with the set frequency FS.

[0031] Please refer to Figures 1 and 3. Figure 3 is a waveform diagram of a control signal according to an embodiment of the present invention. In this embodiment, Figure 3 shows control signals SC1 to SC4. Control signal SC1 has a fixed operating period and frequency. The arithmetic circuit 120 changes the operating period of control signal SC1 by fixing a first multiple K1 of the unit count value CNT and changing a second multiple K2 of the unit count value CNT, thereby determining the gray level of the light-emitting element LD. The first multiple K1 is greater than the second multiple K2. The second multiple K2 is associated with the duration of the high voltage level of control signal SC1. For example, the set frequency FS is equal to 30 kHz. The operating frequency FC is equal to 60 MHz. The order SCL is equal to "255". Therefore, the initial first multiple K1 is, for example, equal to "2000". The second multiple K2 is, for example, equal to one of "1" to "255". Therefore, based on the unit count value CNT, the arithmetic circuit 120 can flexibly adjust the waveform of control signal SC1 to generate control signals SC2 to SC4. In this embodiment, at least one of the first multiple K1 and the second multiple K2 of the control signal SC1 can be adjusted over time to generate a new control signal.

[0032] For example, the arithmetic circuit 120 changes the first multiple K1 of the unit count value CNT to change the period of the control signal SC1, thereby generating the control signal SC2. For example, the arithmetic circuit 120 increases the first multiple K1 of the unit count value CNT to generate the control signal SC2. Therefore, the period of the control signal SC2 is longer than the period of the control signal SC1.

[0033] For example, the operational circuit 120 changes the first multiple K1 and the second multiple K2 of the unit count value CNT to generate a control signal SC3. The period of the control signal SC3 changes from period T3 to period T2, and then from period T2 to period T1. Next, after several periods T1, the period of the control signal SC3 changes from period T1 to period T2, and then from period T2 to period T3. Period T3 is shorter than period T2. Period T2 is shorter than period T1. Furthermore, the working period corresponding to period T3 is longer than the working period corresponding to period T2. The working period corresponding to period T2 is longer than the working period corresponding to period T1. Therefore, the control signal SC3 provides three stages of grayscale and period, thereby presenting a three-stage breathing light effect.

[0034] The operational circuit 120 changes the first multiple K1 and the second multiple K2 of the unit count value CNT to generate a control signal SC4. The period of the control signal SC4 changes from period T1 to period T2, and then changes back to period T1 after several periods T2. Next, the period of the control signal SC4 changes back to period T2 after several periods T1. Therefore, the control signal SC3 provides two stages of grayscale and period, thus presenting a two-stage breathing light effect.

[0035] Please refer to Figure 4, which is a schematic diagram of a control circuit according to an embodiment of the present invention. In this embodiment, the control circuit 200 includes a memory circuit 110, an arithmetic circuit 220, and a timer 130. The arithmetic circuit 220 includes a decoder 221 and a calculation circuit 222. The decoder 221 is coupled to the memory circuit 110. When a start bit BS is received, the decoder 221 receives a set frequency FS and an order SCL from the memory circuit 110. The calculation circuit 222 is coupled to the decoder 221 and the timer 130. The calculation circuit 222 calculates the unit period PUNIT and generates a unit count value CNT based on the arithmetic frequency FC and the unit period PUNIT.

[0036] When the start bit BS is received, the decoder 221 provides the setting frequency FS and the order SCL to the calculation circuit 222. The calculation circuit 222 generates a unit count value CNT and stores the unit count value CNT in the memory circuit 110. When the arithmetic circuit 220 is instructed to generate a control signal SC, the calculation circuit 222 reads the unit count value CNT from the memory circuit 110 and provides the unit count value CNT to the timer 130. Therefore, the timer 130 controls the calculation circuit 222 to generate the control signal SC based on the triggering of the unit count value CNT. The calculation circuit 222 provides the control signal SC to the light-emitting element LD.

[0037] In summary, the control circuit calculates the unit period based on the set frequency and order, generates a unit count value based on the operation frequency and unit period, and then uses the unit count value to control the operation circuit to generate a control signal. In this way, the control circuit can generate a variety of control signals.

[0038] Although the present invention has been disclosed above by way of embodiments, it is not intended to limit the present invention. Anyone skilled in the art can make some modifications and refinements without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be determined by the appended claims. [Simplified Explanation of the Diagram]

[0039] Figure 1 is a schematic diagram of a control circuit according to an embodiment of the present invention. Figure 2 is an operation flowchart of the control circuit according to an embodiment of the present invention. Figure 3 is a waveform diagram of the control signal according to an embodiment of the present invention. Figure 4 is a schematic diagram of a control circuit according to an embodiment of the present invention.

Claims

1. A control circuit for controlling a light-emitting element, comprising: Memory circuit; An arithmetic circuit, coupled to the memory circuit, is configured to receive a set frequency and the order of the operating cycle, calculate a unit cycle based on the set frequency and the order, generate a unit count value based on the arithmetic frequency and the unit cycle, and store the unit count value in the memory circuit. A timer, coupled to the arithmetic circuit and configured to control the arithmetic circuit to generate a control signal based on the unit count value stored in the memory circuit, wherein the arithmetic circuit uses the control signal to control the light-emitting element, and wherein the arithmetic frequency is higher than the set frequency.

2. The control circuit as claimed in claim 1, wherein the set frequency is a frequency applicable to the light-emitting element.

3. The control circuit as claimed in claim 1, wherein the order is equal to the gray level applicable to the light-emitting element.

4. The control circuit as claimed in claim 1, wherein the set frequency and the order are stored in the memory circuit.

5. The control circuit as described in claim 4, wherein: The memory circuit responds to the operation command by providing a start bit, and the operation circuit responds to the start bit by receiving the set frequency and the order from the memory circuit.

6. The control circuit as claimed in claim 5, wherein the arithmetic circuit comprises: A decoder, coupled to the memory circuit, is configured to receive the set frequency and the order from the memory circuit when the start bit is received.

7. The control circuit as claimed in claim 6, wherein the arithmetic circuit further comprises: A computing circuit, coupled to the decoder and the timer, is configured to calculate the unit period and generate the unit count value based on the operation frequency and the unit period, wherein the timer controls the computing circuit to generate the control signal based on the triggering of the unit count value.

8. The control circuit as claimed in claim 1, wherein when the arithmetic circuit is instructed to generate the control signal, the arithmetic circuit reads the unit count value from the memory circuit and provides the unit count value to the timer.

9. The control circuit as claimed in claim 1, wherein the arithmetic circuit calculates the product of the set frequency and the order, and takes the reciprocal of the product as the unit period.

10. The control circuit of claim 9, wherein the arithmetic circuit multiplies the unit period by the arithmetic frequency to obtain the unit count value.

11. The control circuit as claimed in claim 1, wherein the arithmetic circuit changes a first multiple of the unit count value to change the period of the control signal.

12. The control circuit as claimed in claim 11, wherein: The arithmetic circuit fixes a first multiple of the unit count value and changes a second multiple of the unit count value to change the working period of the control signal, thereby determining the gray level of the light-emitting element. The first multiple is greater than the second multiple, and the second multiple is associated with the duration of the high voltage level of the control signal.

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