Semiconductor laminate structure and mothod for fabrication the same

Abstract

A semiconductor laminate structure includes a substrate, a first buffer layer, a second buffer layer and a channel layer. The first buffer layer is disposed on the substrate, wherein the first buffer layer includes a first Group-III-element nitride doped with carbon, and the first buffer layer has a first carbon doping concentration. The second buffer layer is disposed on the first buffer layer, wherein the second buffer layer includes a second Group-III-element nitride doped with carbon, the second buffer layer has a second carbon doping concentration, and the second carbon doping concentration is at least one order of magnitude lower than the first carbon doping concentration. The channel layer is disposed on the second buffer layer.

Description

Technical Field

[0001] This disclosure relates to semiconductor stacked structures and their fabrication methods, particularly to a semiconductor stacked structure and its fabrication method that is beneficial for reducing surface cracks and wafer warpage. Prior Technology

[0002] In the semiconductor field, III-V group semiconductor materials, such as gallium nitride, can be used to form various integrated circuit devices, such as high-electron-mobility transistors (HEMTs) and other high-frequency components or light-emitting diodes.

[0003] Due to the high cost of gallium nitride (GaN) substrates, current GaN semiconductor devices primarily utilize heterostructures with different materials than GaN, such as sapphire, silicon carbide, and silicon. GaN epitaxial layers are grown on these substrates using epitaxial growth methods. However, significant lattice and thermal mismatches exist between the GaN epitaxial layer and the heterostructure. Therefore, a buffer layer is typically placed between the GaN epitaxial layer and the heterostructure. Generally, increasing the thickness of the buffer layer can improve insulation properties, reducing vertical leakage current and increasing breakdown voltage (BV). However, increasing the thickness often leads to stress accumulation, which can cause surface cracks and increase wafer warpage. Summary of the Invention

[0004] One of the purposes of this disclosure is to provide a semiconductor stacked structure and a method for fabricating the same, in order to solve the aforementioned problems.

[0005] According to one embodiment of this disclosure, a semiconductor stacked structure is provided, comprising a substrate, a first buffer layer, a second buffer layer, and a channel layer. The first buffer layer is disposed on the substrate, wherein the first buffer layer comprises a carbon-doped group III nitride and has a first carbon doping concentration. The second buffer layer is disposed on the first buffer layer, wherein the second buffer layer comprises a carbon-doped group III nitride and has a second carbon doping concentration, wherein the second carbon doping concentration is at least one order of magnitude lower than the first carbon doping concentration. The channel layer is disposed on the second buffer layer.

[0006] According to another embodiment of this disclosure, a method for fabricating a semiconductor multilayer structure is provided, comprising the following steps: A substrate is provided. A first buffer layer is provided on the substrate, wherein the first buffer layer comprises a carbon-doped group III nitride and has a first carbon doping concentration. A second buffer layer is provided on the first buffer layer, wherein the second buffer layer comprises a carbon-doped group III nitride and has a second carbon doping concentration, wherein the second carbon doping concentration is at least one order of magnitude lower than the first carbon doping concentration. A channel layer is provided on the second buffer layer.

[0007] Compared to previous technologies, this disclosure utilizes the fact that the second carbon doping concentration of the second buffer layer is at least an order of magnitude lower than the first carbon doping concentration of the first buffer layer, which can release stress and thus help reduce surface cracks and wafer warpage. Simple Explanation of the Diagram

[0008] Figure 1 is a schematic cross-sectional view of a semiconductor stacked structure according to an embodiment of the present disclosure. Figure 2 is a schematic cross-sectional view of a high electron mobility transistor according to another embodiment of this disclosure. Figure 3 is a schematic cross-sectional view of a semiconductor stacked structure according to yet another embodiment of the present disclosure. Figure 4 is a schematic cross-sectional view of a semiconductor stacked structure according to yet another embodiment of the present disclosure. Figure 5 shows the X-ray diffraction (XRD) results of the semiconductor stacked structure according to Comparative Example 1 and Embodiments 1 and 2 of this disclosure. Figure 6 is an optical microscope (OM) result of Comparative Example 1 and the semiconductor stacked structure according to Examples 1 and 2 of this disclosure. Figure 7 is a secondary ion mass spectrometry (SIMS) result of the semiconductor stacked structure according to Example 3 of this disclosure. Figure 8 is an XRD result diagram of the semiconductor stacked structure of Comparative Example 2 and Example 3 according to the present disclosure. Figure 9 is an OM result diagram of the semiconductor stacked structure according to Comparative Example 2 and Embodiment 3 of this disclosure. Figure 10 is an XRD result diagram of the semiconductor stacked structure of Comparative Example 3 and Example 4 according to the present disclosure. Figure 11 is an OM result diagram of the semiconductor stacked structure of Comparative Example 3 and Embodiment 4 according to the present disclosure. Implementation

[0009] The foregoing descriptions and other technical contents, features, and effects of this disclosure will be clearly presented in the following detailed description of the preferred embodiments with reference to the accompanying drawings. The directional terms used in the following embodiments, such as up, down, left, right, front, back, bottom, and top, are only for reference to the accompanying drawings. Therefore, the directional terms used are for illustrative purposes and not for limiting the scope of this disclosure. Furthermore, in the following embodiments, the same or similar elements will be represented by the same or similar reference numerals.

[0010] The following description of "the first feature is formed on or above the second feature" can refer to "the first feature and the second feature are in direct contact" or "there are other features between the first feature and the second feature" so that the first feature and the second feature are not in direct contact.

[0011] Although this disclosure uses terms such as first, second, third, etc., to describe various elements, components, regions, layers, and / or sections, it should be understood that such elements, components, regions, layers, and / or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, and / or section from another, and do not in themselves imply or represent any prior ordinal number of the element, nor do they represent the arrangement order of one element with another, or the order of manufacturing methods. Therefore, without departing from the scope of the specific embodiments of this disclosure, the first element, component, region, layer, or section discussed below may also be referred to as a second element, component, region, layer, or section. The same terms may not be used in the claims and the specification; accordingly, the first element, component, region, layer, and / or section in the specification may be a second element, component, region, layer, and / or section in the claims.

[0012] The numerical ranges and parameters described below are approximate values. Here, "approximate" generally means that the actual value is within plus or minus 10%, 5%, 1%, or 0.5% of a specific value or range. It is understood that all ranges, quantities, values, proportions, and percentages used herein are modified with "approximate". Therefore, unless otherwise stated, the numerical parameters disclosed in this specification and the accompanying claims are approximate values ​​and are subject to change as needed.

[0013] Furthermore, any two values ​​or directions used for comparison can have a certain degree of error. If the first value equals the second value, it implies that there may be an error of about 10% between the first and second values.

[0014] According to embodiments disclosed herein, the depth, thickness, width, or height of each element, or the spacing or distance between elements, can be measured using OM, SEM, TEM, or other suitable methods. According to some embodiments, a scanning electron microscope can be used to obtain a cross-sectional image containing the elements to be measured, and the depth, thickness, width, or height of each element, or the spacing or distance between elements, can be measured.

[0015] Please refer to Figure 1, which is a schematic cross-sectional view of a semiconductor stacked structure 10 according to an embodiment of the present disclosure. The semiconductor stacked structure 10 includes a substrate 100, a buffer layer 130, a buffer layer 140, and a channel layer 170 stacked along a vertical direction D1, which may be parallel to, for example, the normal direction of the top surface of the substrate 100 (not shown). The buffer layer 130 is disposed on the substrate 100 and contains a carbon-doped Group III-element nitride, having a carbon doping concentration. The buffer layer 140 is disposed on the buffer layer 130, wherein the buffer layer 140 contains a carbon-doped Group III-element nitride, having a carbon doping concentration, and the carbon doping concentration of the buffer layer 140 is at least one order of magnitude lower than that of the buffer layer 130. In some embodiments, the carbon doping concentration of the buffer layer 140 may be one to three orders of magnitude lower than that of the buffer layer 130. The channel layer 170 is disposed on the buffer layer 140. By having a carbon doping concentration at least one order of magnitude lower in the buffer layer 140 disposed further away from the substrate 100 than in the buffer layer 130 disposed closer to the substrate 100, it is beneficial to release stress, thereby reducing surface cracks and wafer warpage.

[0016] The substrate 100 can be made of silicon or other semiconductor materials, either as a substrate or a composite substrate. In one embodiment, the substrate 100 is, for example, a silicon layer having a <111> lattice structure, but is not limited thereto. In other embodiments, the substrate 100 may also contain semiconductor compounds such as silicon carbide (SiC), gallium arsenide (GaAs), indium arsenide (InAs), or indium phosphide (InP), or semiconductor alloys such as silicon germanium (SiGe), silicon germanium carbide (SiGeC), gallium arsenide phosphide (AsGaP), or indium gallium phosphide (InGaP). The thickness T0 of the substrate 100 can be from 350 μm to 1150 μm.

[0017] A buffer layer 130 is disposed on the substrate 100, and the buffer layer 130 can be used to buffer stress from the substrate 100. The group III nitride may contain aluminum, for example, aluminum gallium nitride (Alx1Ga1-x1N, 0 < x1 ≤ 1), wherein the aluminum content may be 25% to 35%, the aforementioned aluminum content refers to the weight percentage of aluminum in aluminum gallium nitride. The buffer layer 130 has a carbon doping concentration, the carbon doping concentration of the buffer layer 130 may be, for example, from 1E19 atoms / cm3 to 5E21 atoms / cm3. This is beneficial to increase the insulation of the buffer layer 130, thereby reducing the occurrence of vertical leakage current, and thus improving the breakdown voltage, the aforementioned breakdown voltage refers to having a higher breakdown voltage. In some embodiments, the buffer layer 130 may be further doped with iron, and the buffer layer 130 has a first iron doping concentration, the first iron doping concentration may be, for example, from 1E18 atoms / cm3 to 1E20 atoms / cm3. This improves insulation and reduces vertical leakage. The thickness T3 of the buffer layer 130 can be, for example, 300 nm to 1000 nm. This ensures the buffer layer 130 has a suitable thickness T3; too low a thickness T3 may not provide sufficient stress relief, while too high a thickness T3 may lead to increased stress accumulation, thus affecting the stress relief effect.

[0018] A buffer layer 140 is disposed on the buffer layer 130, and the buffer layer 140 can be used to buffer stress from the substrate 100. The group III nitride may contain aluminum, for example, aluminum gallium nitride (Alx2Ga1-x2N, 0 < x2 ≤ 1), wherein the aluminum content may be 15% to 35%. The buffer layer 140 has a carbon doping concentration, for example, from 1E17 atoms / cm3 to 1E19 atoms / cm3. This helps to increase the insulation of the buffer layer 140, thereby reducing vertical leakage current and improving breakdown voltage, which refers to a higher breakdown voltage. In some embodiments, the buffer layer 140 may be further doped with iron, and the buffer layer 140 has a second iron doping concentration, for example, from 1E18 atoms / cm3 to 1E20 atoms / cm3. This helps to improve insulation and reduce vertical leakage current. The thickness T4 of the buffer layer 140 can be, for example, 300 nm to 1000 nm. In this way, the thickness T4 of the buffer layer 140 is moderate. If the thickness T4 is too low, it may not provide a sufficient stress relief effect. If the thickness T4 is too high, it may lead to an increase in stress accumulation, thus affecting the stress relief effect.

[0019] The buffer layer 140 may be a single-layer structure, but is not limited thereto. In some embodiments, the buffer layer 140 may be a multi-layer structure. In Figure 1, the buffer layer 140 is illustrated by including a first sublayer 142 and a second sublayer 144. The aluminum content of the first sublayer 142 is fixed, the aluminum content of the second sublayer 144 is fixed, the aluminum content of the first sublayer 142 is different from the aluminum content of the second sublayer 144, and the thickness t41 of the first sublayer 142 is greater than or equal to 100 nm, and the thickness t42 of the second sublayer 142 is greater than or equal to 100 nm. That is, the buffer layer 140 may include multiple sublayers, the aluminum content in each sublayer is fixed, and the aluminum content of different sublayers may be different. In addition, the thickness of each sublayer may be greater than or equal to 100 nm. Preferably, the number of sublayers in the buffer layer 140 may be two to three. In some embodiments, the buffer layer 140 may include a plurality of first sublayers 142 and a plurality of second sublayers 144, which are stacked alternately along a vertical direction. In some embodiments, the difference in aluminum content between the first sublayer 142 and the second sublayer 144 may be within 10%. This is beneficial for improving the effectiveness of reducing surface cracks and wafer warpage.

[0020] In some embodiments, the aluminum content of the group III nitride is W1%, and the aluminum content of the group III nitride is W2%, which can satisfy the following conditions: This provides a certain degree of stress relief. In other words, whether the aluminum content in buffer layer 140 is higher or lower than the aluminum content in buffer layer 130, it can provide a certain degree of stress relief. In some embodiments, the aluminum content in buffer layer 140 is lower than the aluminum content in buffer layer 130. A lower aluminum content in buffer layer 140 compared to a higher aluminum content in buffer layer 130 provides a better stress relief effect, but this is not limited to this. The aluminum content in buffer layer 130 and buffer layer 140 can be adjusted according to actual needs, such as the overall epitaxial structure design in the semiconductor stack-up structure 10.

[0021] The material of the channel layer 170 can be gallium nitride (GaN). The thickness T7 of the channel layer 170 can be from 50 nm to 5000 nm.

[0022] In detail, the semiconductor stack-up structure 10 may optionally further include a buffer layer 110, a buffer layer 120, a high-resistivity layer 160, an electron-providing layer 180, and a capping layer 190. Buffer layers 110 and 120 are sequentially disposed on the substrate 100 and between the substrate 100 and the buffer layer 130. The high-resistivity layer 160 is disposed on the buffer layer 140 and between the buffer layer 140 and the channel layer 170. The electron-providing layer 180 is disposed on the channel layer 170. The capping layer 190 is disposed on the electron-providing layer 180.

[0023] A buffer layer 110 is disposed on the substrate 100 and can be used to buffer stress from the substrate 100. The buffer layer 110 may contain a group III nitride, which may contain aluminum, for example, aluminum gallium nitride (Alx3Ga1-x3N, 0 < x3 ≤ 1), wherein the aluminum content may be 50% to 70%. The buffer layer 110 may have a carbon doping concentration, which may be less than that of the buffer layer 130. The carbon doping concentration of the buffer layer 110 may be, for example, 1E19 atoms / cm3 to 1E21 atoms / cm3. This helps to increase the insulation of the buffer layer 110, thereby reducing vertical leakage current and improving withstand voltage. In some embodiments, the buffer layer 110 may be further doped with iron, and the buffer layer 110 may have a third iron doping concentration, for example, 1E18 atoms / cm3 to 1E20 atoms / cm3. This improves insulation and reduces vertical leakage. The thickness T1 of the buffer layer 110 can be, for example, 300 nm to 1000 nm.

[0024] A buffer layer 120 is disposed on the buffer layer 110, and the buffer layer 120 can be used to buffer stress from the substrate 100. The buffer layer 120 may contain a group III nitride, which may contain aluminum, for example, aluminum gallium nitride (Alx4Ga1-x4N, 0 < x4 ≤ 1), wherein the aluminum content may be 40% to 50%. The buffer layer 120 has a carbon doping concentration, which may be greater than that of the buffer layer 110 and less than that of the buffer layer 130. The carbon doping concentration of the buffer layer 120 may be, for example, 1E19 atoms / cm3 to 5E21 atoms / cm3. This is beneficial for increasing the insulation of the buffer layer 120, thereby reducing the occurrence of vertical leakage current and improving the withstand voltage. In some implementations, the buffer layer 120 may be further doped with iron, and the buffer layer 120 may have a fourth iron doping concentration, for example, from 1E18 atoms / cm3 to 1E20 atoms / cm3. This improves insulation and reduces vertical leakage. The thickness T2 of the buffer layer 120 may, for example, be from 200 nm to 1000 nm.

[0025] A high-resistivity layer 160 is disposed on the buffer layer 140, and the resistivity of the high-resistivity layer 160 is higher than that of the buffer layer 140. The material of the high-resistivity layer 160 can be doped gallium nitride (GaN), and the doping element can be carbon, iron, magnesium, zinc or a combination thereof, and the doping amount can be 2E19 atoms / cm3. The thickness T6 of the high-resistivity layer 160 can be from 0.2 µm to 5.5 µm.

[0026] An electron providing layer 180 is disposed on the channel layer 170. The material of the electron providing layer 180 may be aluminum indium gallium nitride (InAlx5Ga1-x5N, 0.1 < x5 < 1) or aluminum gallium nitride (Alx6Ga1-x6N, 0.1 < x6 < 1). The thickness T8 of the electron providing layer 180 may be from 8 nm to 45 nm.

[0027] A capping layer 190 is disposed on the electron providing layer 180. The material of the capping layer 190 may be p-type gallium nitride or p-type aluminum gallium nitride (Alx7Ga1-x7N, 0.05 < x7 < 1). The thickness T9 of the capping layer 190 may be from 0.5 nm to 50 nm.

[0028] The semiconductor stack 10 may optionally include other layers. In some embodiments, the semiconductor stack 10 may further include a nucleation layer (not shown) disposed on the substrate 100. The material of the nucleation layer may be aluminum nitride (AlN) or aluminum indium gallium nitride (Inx8Aly8Ga1-x8-y8N, 0 ≤ x8 ≤ 1, 0 ≤ y8 ≤ 1, and x8 + y8 ≤ 1; or, 0 ≤ x8 < 0.01, 0.9 < y8 ≤ 1). When forming the nucleation layer, the process temperature may be gradually increased, for example, by 10 °C to 15 °C per minute. The thickness of the nucleation layer may be from 1 nm to 500 nm. This can improve the bonding between the substrate 100 and other layers and reduce the probability of cracking and warping.

[0029] In this embodiment, a semiconductor stacked structure 10 comprising four buffer layers is used as an example. The four buffer layers are sequentially named buffer layers 110, 120, 130, and 140 along the vertical direction D1 from the substrate 100 away from the substrate 100. However, this disclosure is not limited to this, and the number of buffer layers can be adjusted according to actual needs. This invention selects carbon as a dopant and makes the carbon doping concentration of the two buffer layers 130 and 140 furthest from the substrate 100 decrease with increasing distance from the substrate 100. Furthermore, the carbon doping concentration of buffer layer 140 is at least one order of magnitude lower than that of buffer layer 130, which is beneficial for stress release and can reduce surface cracks and wafer warpage. When the carbon doping concentration of buffer layer 130 is not a constant value, the aforementioned carbon doping concentration of buffer layer 130 can refer to the buffer layer with the highest carbon doping concentration. When the carbon doping concentration of buffer layer 140 is not a constant value, the aforementioned carbon doping concentration of buffer layer 140 can refer to the buffer layer with the lowest carbon doping concentration.

[0030] Furthermore, in buffer layers 110, 120, 130 and 140, the carbon doping concentration in buffer layers 110, 120 and 130 is configured to increase with distance from substrate 100 (i.e., satisfying the following condition: carbon doping concentration in buffer layer 110 < carbon doping concentration in buffer layer 120 < carbon doping concentration in buffer layer 130), and the carbon doping concentration in buffer layers 130 and 140 is configured to decrease with distance from substrate 100 (i.e., carbon doping concentration in buffer layer 130 > carbon doping concentration in buffer layer 140), and the carbon doping concentration in buffer layer 130 is at least one order of magnitude greater than the carbon doping concentration in buffer layer 140.

[0031] In buffer layers 110, 120, 130 and 140, the aluminum content in buffer layers 110, 120 and 130 is configured to decrease with increasing distance from substrate 100 (i.e., satisfying the following condition: aluminum content in buffer layer 110 > aluminum content in buffer layer 120 > aluminum content in buffer layer 130). The aluminum content in buffer layers 130 and 140 is configured to decrease or increase with increasing distance from substrate 100. For details on this part, please refer to the relevant explanation above.

[0032] Furthermore, when the semiconductor stack-up structure 10 includes N buffer layers, sequentially arranged from bottom to top (i.e., from the substrate 100 towards the direction away from the substrate 100) as buffer layer 1, buffer layer 2, ..., buffer layer N-1 and buffer layer N, the carbon doping concentration of buffer layers 1 to N-1 is configured to increase with increasing distance from the substrate 100, while the carbon doping concentration of the two buffer layers N-1 and N furthest from the substrate 100 is configured to decrease with increasing distance from the substrate 100, and the carbon doping concentration of buffer layer N-1 is at least one order of magnitude greater than that of buffer layer N. The aluminum content of buffer layers 1 to N-1 is configured to decrease with increasing distance from the substrate 100, while the aluminum content of the two buffer layers N-1 and N furthest from the substrate 100 can be configured to decrease or increase with increasing distance from the substrate 100. In some embodiments, the aluminum content of buffer layer N may be less than the aluminum content of buffer layer N-2. The first figure uses N equal to 4 as an example, but is not limited to this; N can be an integer greater than or equal to 2. In some embodiments, N equals 4 or 5, thereby ensuring that the number of buffer layers is moderate, providing sufficient buffering effect while avoiding excessive growth cycle and overall thickness that would lead to stress accumulation.

[0033] The various material layers disposed on the substrate 100 in the semiconductor stack structure 10, such as buffer layers 110, 120, 130, 140, high-resistivity layer 160, channel layer 170, electron-providing layer 180, and capping layer 190, can be epitaxially grown using metal-organic chemical vapor deposition (MOCVD). The thickness of each layer and the carbon doping concentration can be adjusted by process parameters such as pressure, temperature, and time. In other words, each material layer disposed on the substrate 100 in the semiconductor stack structure 10 can be an epitaxial layer. In some embodiments, the total thickness of the material layers disposed on the substrate 100 in the semiconductor stack structure 10 can be 4 μm to 5 μm. The semiconductor stack structure 10 can be further processed to manufacture the desired semiconductor device or apparatus, such as HEMT 20 in Figure 2.

[0034] Please refer to Figure 2, which is a cross-sectional schematic diagram of a HEMT 20 according to an embodiment of this disclosure. The HEMT 20 can be fabricated from a semiconductor stack-up structure 10. Specifically, compared to the semiconductor stack-up structure 10, the HEMT 20 further includes a gate electrode 230, a source electrode 210, and a drain electrode 220. The gate electrode 230 is disposed on a capping layer 190, while the source electrode 210 and drain electrode 220 are respectively disposed on opposite sides of the gate electrode 230 and located on a channel layer 170. The source electrode 210 and drain electrode 220 can penetrate the electron supply layer 180 to reach the top surface of the channel layer 170, or to a depth of the channel layer 170 (not shown). As shown in Figure 2, the area not covered by the capping layer 190 will form a two-dimensional electron gas (2DEG) 240 due to the piezoelectric effect generated between the channel layer 170 and the electron supply layer 180. By applying a bias voltage to the P-type capping layer 190 using the gate electrode 230, the concentration of 2DEG 240 in the channel layer 170 located below the P-type capping layer 190 can be controlled, thereby controlling the switching of the HEMT 20. Compared to silicon power transistors, the HEMT 20 has a wider band gap, thus exhibiting low on-state resistance (RON) and low switching losses. The HEMT 20 can be used as a power switching transistor for voltage converter applications or high-power telecommunications applications, but this disclosure is not limited thereto. The formation of the gate electrode 230, source electrode 210, and drain electrode 220 in the semiconductor stack-up structure 10 is well known in the art and will not be described further here.

[0035] Please refer to Figure 3, which is a cross-sectional schematic diagram of a semiconductor stacked structure 10A according to another embodiment of this disclosure. The main difference between the semiconductor stacked structure 10A and the semiconductor stacked structure 10 is that the semiconductor stacked structure 10A further includes at least one superlattice stacked layer 150 disposed on the buffer layer 140, wherein the superlattice stacked layer 150 includes a plurality of units U1 stacked in the vertical direction D1. Each unit U1 may include aluminum nitride 151, aluminum gallium nitride 152, and gallium nitride 153 (aluminum nitride 151 / aluminum gallium nitride 152 / gallium nitride 153) stacked sequentially in the vertical direction D1. Here, aluminum nitride 151, aluminum gallium nitride 152, and gallium nitride 153 are stacked sequentially from bottom to top in the vertical direction D1. In other embodiments, aluminum nitride 151, aluminum gallium nitride 152, and gallium nitride 153 may be stacked sequentially from top to bottom in the vertical direction D1. By incorporating the superlattice stacked layer 150, the ability to release stress is improved. In other embodiments, each unit U1 may comprise any two of aluminum nitride 151, aluminum gallium nitride 152, and gallium nitride 153 stacked sequentially in the vertical direction D1, such as aluminum nitride 151 / aluminum gallium nitride 152, aluminum nitride 151 / gallium nitride 153, and aluminum gallium nitride 152 / gallium nitride 153. The unit thickness t51 of unit U1 may, for example, be greater than 100 angstroms (Å), and the thickness T5 of the superlattice stacked layer 150 may be from 0.5 µm to 20 µm. The superlattice stacked layer 150 may be epitaxially grown via metal-organic chemical vapor deposition.

[0036] In this embodiment, a semiconductor stacked structure 10A comprising a single superlattice stacked layer is used as an example. However, it is not limited to this. In other embodiments, the semiconductor stacked structure 10A may comprise multiple superlattice stacked layers. Each superlattice stacked layer comprises a plurality of units stacked in the vertical direction D1. Each unit comprises at least two of aluminum nitride, aluminum gallium nitride, and gallium nitride, stacked sequentially from bottom to top or from top to bottom in the vertical direction D1. The thickness of the units in different superlattice stacked layers may be configured to gradually vary along the vertical direction D1, and the thickness of different superlattice stacked layers may be configured to gradually vary along the vertical direction D1 to further enhance the stress release capability.

[0037] In some embodiments, the total thickness of the material layers disposed on the substrate 100 in the semiconductor stack structure 10A may be from 5 μm to 10 μm. The semiconductor stack structure 10A can be further processed to manufacture the desired semiconductor device or apparatus. Other details regarding the semiconductor stack structure 10A can be found in the relevant description of the semiconductor stack structure 10, and will not be repeated here.

[0038] Please refer to Figure 4, which is a schematic cross-sectional view of a semiconductor stacked structure 10B according to another embodiment of this disclosure. The main difference between semiconductor stacked structure 10B and semiconductor stacked structure 10 is that semiconductor stacked structure 10B lacks buffer layers 110 and 120 compared to semiconductor stacked structure 10. In some embodiments, the total thickness of the material layers disposed on the substrate 100 in semiconductor stacked structure 10B can be from 1 μm to 2.9 μm. Semiconductor stacked structure 10B can be further processed to manufacture the desired semiconductor device or apparatus. Other details regarding semiconductor stacked structure 10B can be found in the relevant description of semiconductor stacked structure 10, and will not be repeated here.

[0039] The present invention also provides a method 400 for fabricating a semiconductor stacked structure, which may include steps 410, 440, 450, and 470. Step 410 involves providing a substrate. Step 440 involves providing a first buffer layer on the substrate, wherein the first buffer layer comprises a carbon-doped group III nitride and has a first carbon doping concentration. Step 450 involves providing a second buffer layer on the first buffer layer, wherein the second buffer layer comprises a carbon-doped group III nitride and has a second carbon doping concentration, and the second carbon doping concentration is at least one order of magnitude lower than the first carbon doping concentration. Step 470 involves providing a channel layer on the second buffer layer.

[0040] The first and second buffer layers can be formed by epitaxial growth using metal chemical vapor deposition (MCV), and can also be formed by the reaction of a group III gas source and a group V gas source. According to one embodiment of the present invention, the first and second buffer layers are carbon-doped aluminum gallium nitride, the group III gas source can be trimethylgallium (TMGa) and trimethylaluminum (TMAl), and the group V gas source can be ammonia (NH3). The process parameters for forming the first and second buffer layers are shown in Table 1 below, where the V / III ratio represents the mole ratio of the group V gas source to the group III gas source, and GR represents the growth rate. Table 1 Process parameters Temperature (°C) Pressure (mbar) V / III GR (um / hr) First buffer layer 1080~1100 40~60 10~100 2~4 Second buffer layer 1045~1065 65~85 1200~1600 0.5~1.5

[0041] As shown in Table 1, the temperature at which the second buffer layer is formed can be lower than the temperature at which the first buffer layer is formed, the pressure at which the second buffer layer is formed can be greater than the pressure at which the first buffer layer is formed, the V / III ratio at which the second buffer layer is formed can be greater than the V / III ratio at which the first buffer layer is formed, and the growth rate at which the second buffer layer is formed can be less than the growth rate at which the first buffer layer is formed. In some embodiments, the ratio of the V / III ratio at which the second buffer layer is formed to the V / III ratio at which the first buffer layer is formed can be from 12 to 160, for example, 10, 20, 30, 40, 50, 60, 70, 80, 90, 100, 110, 120, 130, 140 or 150, but is not limited thereto. In some embodiments, the ratio of the GR forming the second buffer layer to the GR forming the first buffer layer may be from 0.125 to 0.75, for example, 0.1, 0.15, 0.2, 0.25, 0.3, 0.35, 0.4, 0.45, 0.5, 0.55, 0.6, 0.65 or 0.7, but is not limited thereto.

[0042] Furthermore, within a suitable temperature and pressure range, by increasing the V / III ratio, the present invention can increase the amount of N source introduced, thereby suppressing the amount of C doping. On the other hand, by reducing the growth rate, the amount of C doping can also be suppressed. Therefore, by adjusting the deposition parameters, the purpose of changing the carbon doping concentration gradient in the first and second buffer layers can be achieved without introducing a new carbon source to adjust the carbon doping concentration, thus reducing costs and simplifying the process.

[0043] The method 400 for fabricating a semiconductor multilayer structure may optionally further include steps 420, 430, 460, 480, and 490. Step 420 involves providing a third buffer layer between the substrate and the first buffer layer, wherein the third buffer layer comprises a carbon-doped group III nitride, the third buffer layer has a third carbon doping concentration, and the third carbon doping concentration is less than the first carbon doping concentration. Step 430 involves providing a fourth buffer layer between the substrate and the first buffer layer, wherein the fourth buffer layer comprises a carbon-doped group III nitride, the fourth buffer layer has a fourth carbon doping concentration, and the fourth carbon doping concentration is less than the first carbon doping concentration. The fourth buffer layer may be disposed between the third buffer layer and the first buffer layer, and the fourth carbon doping concentration may be greater than the third carbon doping concentration. In other words, this example includes four buffer layers, which are sequentially arranged from the substrate away from the substrate as a third buffer layer, a fourth buffer layer, a first buffer layer, and a second buffer layer. Furthermore, when the semiconductor stack-up structure includes multiple buffer layers, the first and second buffer layers are the two buffer layers furthest from the substrate among all buffer layers. The carbon doping concentration in different buffer layers can be adjusted by controlling the deposition parameters of each buffer layer, without the need to introduce a new carbon source to adjust the carbon doping concentration. Step 460 involves providing at least one superlattice stack layer on the second buffer layer. Step 480 involves providing an electron-providing layer on the channel layer. Step 490 involves providing a capping layer on the electron-providing layer. For other details regarding the semiconductor stack-up structure, please refer to the relevant content of semiconductor stack-up structures 10, 10A, and 10B above.

[0044] [<] [Examples and Comparative Examples] [>]

[0045] (I) Semiconductor stacked structures of Examples 1, 2 and Comparative Example 1: The semiconductor stacked structures of Examples 1 and 2, from bottom to top, sequentially include a substrate, a nucleation layer, a buffer layer 1, a buffer layer 2, a buffer layer 3, a buffer layer 4, a high-resistivity layer, a channel layer, an electron-providing layer, and a capping layer. Compared with the semiconductor stacked structure 10 in Figure 1, the semiconductor stacked structures of Examples 1 and 2 further include a nucleation layer disposed on the substrate. For the main components of each layer of the semiconductor stacked structures of Examples 1 and 2, please refer to Table 2. Each layer may have different dopants and doping concentrations. The aluminum content and gallium content in the aluminum gallium nitride of different layers may be different. For details of each layer, please refer to the relevant description in Figure 1. Table 2 Material Cover layer Gallium nitride Electronic supply layer Gallium aluminum nitride Channel layer Gallium nitride High-resistivity layer Gallium nitride Buffer layer 4 Gallium aluminum nitride Buffer layer 3 Gallium aluminum nitride Buffer layer 2 Gallium aluminum nitride Buffer layer 1 Gallium aluminum nitride nucleation layer Aluminum nitride substrate Silicon layers with <111> lattice structure

[0046] The main difference between Examples 1 and 2 is the aluminum content in the buffer layer 4. The main difference between Comparative Example 1 and Examples 1 and 2 is that Comparative Example 1 uses the material of buffer layer 3 instead of buffer layer 4. That is, Examples 1 and 2 contain four buffer layers, while Comparative Example 1 contains only three buffer layers. Furthermore, the total thickness of buffer layers 3 and 4 in Examples 1 and 2 is substantially equal to the thickness of buffer layer 3 in Comparative Example 1.

[0047] Please refer to Table 3 for the process parameters of buffer layer 3 and buffer layer 4 in Example 2. The process parameters of buffer layer 4 in Example 1 are mainly adjusted by changing the ratio of Al to Ga in the Group III gas source, which can result in different aluminum contents in buffer layer 4 of Examples 1 and 2. Table 3 Process parameters Temperature (°C) Pressure (mbar) V / III GR (um / hr) Buffer layer 3 1090 50 40.5 3.13 Buffer layer 4 1055 75 1496 0.90

[0048] The semiconductor stacked structures of Examples 1, 2, and Comparative Example 1 were subjected to X-ray diffraction analysis using an X-ray diffractometer, which revealed the aluminum composition of each material layer in the semiconductor stacked structure. Please refer to Figure 5, which shows the XRD results of the semiconductor stacked structures of Comparative Example 1 and Examples 1 and 2 according to this disclosure. In Figure 5, signal peak PK1 corresponds to the signal of buffer layer 1 in Example 1, signal peak PK2 corresponds to the signal of buffer layer 2 in Example 1, signal peak PK3 corresponds to the signal of buffer layer 4 in Example 1, from which the aluminum content can be calculated to be 32.4%, signal peak PK4 corresponds to the signal of buffer layer 3 in Example 1, from which the aluminum content can be calculated to be 28%, and signal peak PK5 corresponds to the signal of buffer layer 4 in Example 2, from which the aluminum content can be calculated to be 24.5%. As can be seen from Figure 5, the positions and intensities of the signals of buffer layers 1, 2, and 3 in Examples 2 and Comparative Example 1 are substantially the same as those of the signals of buffer layers 1, 2, and 3 in Example 1. In Example 1, the aluminum content of buffer layer 4 is greater than that of buffer layer 3, and the difference between the aluminum content of buffer layer 4 and buffer layer 3 is less than 10%. In Example 2, the aluminum content of buffer layer 4 is less than that of buffer layer 3, and the difference between the aluminum content of buffer layer 4 and buffer layer 3 is within 10% (i.e., greater than -10%).

[0049] The surface morphology of the semiconductor stacked structures of Examples 1, 2, and Comparative Example 1 was observed using an optical microscope. Please refer to Figure 6, which shows the OM results of the semiconductor stacked structures of Comparative Example 1 and Examples 1 and 2 according to this disclosure, where parts (A), (B), and (C) are the OM results of Comparative Example 1, Examples 1, and 2, respectively. As shown in Figure 6, compared to Comparative Example 1, the semiconductor stacked structures of Examples 1 and 2 have reduced surface cracks. For example, the size (e.g., thickness or length) of the cracks is smaller, the number is less, or the density is lower. In conjunction with Figure 5 above, it can be seen that the aluminum content of buffer layer 4 in Example 1 is greater than that of buffer layer 3, and the aluminum content of buffer layer 4 in Example 2 is less than that of buffer layer 3. In other words, when the difference between the aluminum content of buffer layer 4 and the aluminum content of buffer layer 3 is within ±10%, surface cracks can be reduced.

[0050] The total thickness TT of the material layer (i.e., epitaxial layer) other than the substrate in the semiconductor stacked structures of Examples 1, 2 and Comparative Example 1 was measured using an instrument (model: EtaMax PLATO). The edge crack size CR was observed and measured using an optical microscope. The center curvature CB and warpage WP were measured using an instrument (model: EtaMax PLATO). The aforementioned measurement results are recorded in Table 4. The crack size CR can be obtained by directly measuring the crack length observed by the optical microscope. The curvature CB and warpage WP can be automatically calculated by the instrument after scanning the complete wafer image (mapping). Table 4 Comparative Example 1 Example 1 Example 2 TT (μm) 4.48 4.48 4.44 CR (mm) 3.5~4 1.5 4~5 CB(μm) -55.07 -51.75 -38.71 WP(μm) 66.95 60.51 48.15

[0051] As shown in Table 4, compared with Comparative Example 1, the semiconductor stacked structures of Examples 1 and 2 have a smaller degree of center bending CB and warpage WP, that is, the semiconductor stacked structure according to the present invention can effectively reduce the degree of warpage.

[0052] Based on the measurement results of the secondary ion mass spectrometer (see Figure 7 for related explanations), in buffer layers 1 to 4 of Examples 1 and 2, the carbon doping concentration of buffer layers 1 to 3 gradually increases from the substrate away from the substrate, while the carbon doping concentration of buffer layers 3 to 4 gradually decreases from the substrate away from the substrate. Furthermore, the carbon doping concentration of buffer layer 4 is at least one order of magnitude lower than that of buffer layer 3. In other words, by selecting carbon as the dopant and ensuring that the carbon doping concentration of buffer layers 3 and 4, which are furthest from the substrate, decreases with increasing distance from the substrate, and that the carbon doping concentration of buffer layer 4 is at least one order of magnitude lower than that of buffer layer 3, the aluminum content of buffer layer 4 can be slightly higher or slightly lower than that of buffer layer 3 (within ±10%). This is beneficial for stress release, reducing surface cracks and wafer warpage.

[0053] (II) Semiconductor Stack Structures of Example 3 and Comparative Example 2: The main difference between Example 3 and Example 2 is that Example 3 further includes a superlattice stacked layer disposed between the buffer layer 4 and the high-resistivity layer. The semiconductor stack structure of Example 3, compared to the semiconductor stack structure 10A in Figure 3, further includes a nucleation layer disposed on the substrate. Details regarding the superlattice stacked layer can be found in the relevant description in Figure 3. The main difference between Comparative Example 2 and Example 3 is that Comparative Example 2 omits the buffer layer 4; that is, Example 3 includes four buffer layers, while Comparative Example 2 includes only three buffer layers.

[0054] The semiconductor stacked structure of Example 3 was analyzed using secondary ion mass spectrometry. Please refer to Figure 7, which shows the SIMS results of the semiconductor stacked structure of Example 3 disclosed herein. The relationship between the intensity and depth of the metal components (in this case, aluminum and gallium) can be analyzed, with the metal component intensity corresponding to the right vertical axis. The relationship between carbon doping concentration and depth can also be analyzed, with the carbon doping concentration corresponding to the left vertical axis. Furthermore, regions R1, R2, R3, R4, R5, R6, R7, and R8 sequentially correspond to the depth (or thickness) ranges of the substrate, nucleation layer, buffer layer 1, buffer layer 2, buffer layer 3, buffer layer 4, superlattice stacked layer, and high-resistivity layer. As shown in Figure 7, the carbon doping concentration varies gradient from buffer layer 1 to buffer layer 3, increasing gradually from the substrate away from it. The minimum carbon doping concentration in buffer layer 1 and the maximum carbon doping concentration in buffer layer 3 are approximately one order of magnitude equal. From buffer layer 3 to buffer layer 4, the carbon doping concentration decreases significantly. The carbon doping concentration in buffer layer 4 is at least one order of magnitude lower than that in buffer layer 3. Specifically, the carbon doping concentration in buffer layer 4 is more than two orders of magnitude lower than that in buffer layer 3, but less than three orders of magnitude lower. Furthermore, since the main difference between Example 3 and Examples 1 and 2 is that Example 3 has an additional superlattice stacked layer, the carbon doping concentration in buffer layers 1 to 4 of Examples 1 and 2 can be the same as that in Example 3. Therefore, Figure 7 is also suitable for illustrating the relationship between the carbon doping concentration and depth in buffer layers 1 to 4 of Examples 1 and 2.

[0055] The semiconductor stacked structures of Example 3 and Comparative Example 2 were subjected to X-ray diffraction analysis using an X-ray diffractometer, which revealed the aluminum composition of each material layer in the semiconductor stacked structure. Please refer to Figure 8, which shows the XRD results of the semiconductor stacked structures of Comparative Example 2 and Example 3 according to this disclosure. In Figure 8, signal peak PK6 corresponds to the signal of buffer layer 3 in Example 3, and signal peak PK7 corresponds to the signal of buffer layer 4 in Example 3. As can be seen from Figure 8, the position and intensity of the signal of buffer layer 3 in Comparative Example 2 are substantially the same as those in Example 3. In Example 3, the aluminum content of buffer layer 4 is less than that of buffer layer 3, and the difference between the aluminum content of buffer layer 4 and buffer layer 3 is within 10% (i.e., greater than -10%).

[0056] The surface morphology of the semiconductor stacked structures of Example 3 and Comparative Example 2 was observed using an optical microscope. Please refer to Figure 9, which shows the OM results of the semiconductor stacked structures of Comparative Example 2 and Example 3 according to this disclosure, where parts (A) and (B) are the OM results of Comparative Example 2 and Example 3, respectively. Other performance measurements of Example 3 and Comparative Example 2 are shown in Table 5. Table 5 Comparative Example 2 Example 3 TT (μm) 4.91 5.38 CR (mm) 1~2 0.5~1 CB(μm) -20.45 1.33 WP(μm) 27.68 13.18

[0057] As can be seen from Figure 9 and Table 5, compared with Comparative Example 2, the semiconductor stacked structure of Example 3 has reduced surface cracks and smaller central bending degree CB and warpage degree WP. That is, the semiconductor stacked structure according to the present invention can effectively reduce the degree of warpage.

[0058] Furthermore, Example 3 has an additional superlattice stacked layer compared to Examples 1 and 2, resulting in a thicker material layer. In Example 3, the total material layer thickness TT is greater than 5 μm. Theoretically, this total thickness TT would lead to increased stress accumulation, making it easier for edge cracks and greater bending and warping to occur after the epitaxial growth is completed and the temperature is lowered to room temperature. However, as shown in the above measurements, by controlling the carbon doping concentration of buffer layers 3 and 4, the present invention can improve the bending degree CB and warping degree WP of the semiconductor stacked structure even with an increased total material layer thickness TT, and the edge cracks are also reduced compared to Comparative Example 2. This demonstrates that the semiconductor stacked structure of the present invention can be configured with a thicker material layer to improve the insulation of the underlying layer, while also having a good stress relief effect.

[0059] (III) Semiconductor Stack Structures of Example 4 and Comparative Example 3: The main difference between Example 4 and Example 2 is that Example 4 does not include buffer layer 1 and buffer layer 2, and the process parameters of buffer layer 4 are adjusted in Example 4, such as reducing the temperature and growth rate. The difference between Comparative Example 3 and Example 4 is that Comparative Example 3 uses the same temperature and pressure when forming buffer layer 3 and buffer layer 4, and the V / III ratio and GR are substantially the same. Since the process parameters for forming buffer layer 3 and buffer layer 4 in Comparative Example 3 are substantially the same, the carbon doping concentration of buffer layer 3 and buffer layer 4 in Comparative Example 3 is substantially the same and there is no gradient change. Please refer to Table 6 for the process parameters of buffer layer 3 and buffer layer 4 in Comparative Example 3 and Example 4. Table 6 Process parameters Temperature (°C) Pressure (mbar) V / III GR (um / hr) Comparative Example 3 Buffer layer 3 995 75 1393 0.94 Buffer layer 4 995 75 1496 0.84 Example 4 Buffer layer 3 1090 50 40.5 3.22 Buffer layer 4 995 75 1496 0.84

[0060] The semiconductor stacked structures of Example 4 and Comparative Example 3 were subjected to X-ray diffraction analysis using an X-ray diffractometer, which revealed the aluminum composition of each material layer in the semiconductor stacked structure. Please refer to Figure 10, which shows the XRD results of the semiconductor stacked structures of Comparative Example 3 and Example 4 according to this disclosure. In Figure 10, signal peak PK8 corresponds to the signal of buffer layer 3 in Example 4, and signal peak PK9 corresponds to the signal of buffer layer 4 in Example 4. As can be seen from Figure 10, the positions and intensities of the signals of buffer layers 3 and 4 in Comparative Example 3 and Example 3 are substantially the same. In Example 4, the aluminum content of buffer layer 4 is less than that of buffer layer 3, and the difference between the aluminum content of buffer layer 4 and buffer layer 3 is within 10% (i.e., greater than -10%).

[0061] The surface morphology of the semiconductor stacked structures of Example 4 and Comparative Example 3 was observed using an optical microscope. Please refer to Figure 11, which shows the OM results of the semiconductor stacked structures of Comparative Example 3 and Example 4 according to this disclosure, where parts (A) and (B) are the OM results of Comparative Example 3 and Example 4, respectively. Other performance measurements of Example 4 and Comparative Example 3 are shown in Table 7. Table 7 Comparative Example 3 Example 4 TT (μm) 2.23 2.23 CR (mm) 3~4 <1.5 CB(μm) -6.46 -15.67 WP(μm) twenty two 21.3

[0062] As can be seen from Figure 11 and Table 7, when the total thickness TT of the material layer is small (2.23 μm in this case), the crack size CR of the semiconductor stacked structure of Example 4 is significantly improved compared to Comparative Example 3. Furthermore, the semiconductor stacked structure of Example 4 has a smaller degree of center bending CB and warpage WP. In other words, the semiconductor stacked structure according to the present invention can effectively reduce surface cracks and reduce warpage.

[0063] Compared to prior art, this disclosure utilizes a buffer layer located further from the substrate with a carbon doping concentration at least one order of magnitude lower than that located closer to the substrate. This facilitates stress release, thereby reducing surface cracks and wafer warpage. The above description is only a preferred embodiment of the present invention. All equivalent changes and modifications made in accordance with the claims of the present invention shall be covered by the present invention.

[0064] 10, 10A, 10B: Semiconductor stack-up structure

[0065] 20:HEMT

[0066] 100:Substrate

[0067] 110, 120, 130, 140: Buffer layer

[0068] 142: First Sublayer

[0069] 144: Second Sublayer

[0070] 150: Superlattice stacked layer

[0071] 151: Aluminum Nitride

[0072] 152: AlGaN

[0073] 153: Gallium Nitride

[0074] 160: High-resistivity layer

[0075] 170: Channel Layer

[0076] 180: Electron Supply Layer

[0077] 190: Overlay

[0078] 210: Source electrode

[0079] 220: Drain electrode

[0080] 230: Gate electrode

[0081] 240:2DEG

[0082] D1: Vertical direction

[0083] PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9: Signal Peak

[0084] R1, R2, R3, R4, R5, R6, R7, R8: Regions

[0085] T0, T1, T2, T3, T4, T5, T6, T7, T8, T9, t41, t42, t51: Thickness

[0086] U1: Unit

Claims

1. A semiconductor stacked structure, comprising: a substrate; a first buffer layer disposed on the substrate, wherein the first buffer layer comprises a carbon-doped Group-III-element nitride, the first buffer layer having a first carbon doping concentration; a second buffer layer disposed on the first buffer layer, wherein the second buffer layer comprises a carbon-doped Group-III-element nitride, the second buffer layer having a second carbon doping concentration, the second carbon doping concentration being at least one order of magnitude lower than the first carbon doping concentration, and the first buffer layer and the second buffer layer being the two buffer layers furthest from the substrate; and a channel layer disposed on the second buffer layer.

2. The semiconductor stacked structure as described in claim 1 further comprises: a third buffer layer disposed between the substrate and the first buffer layer, wherein the third buffer layer comprises a carbon-doped group III nitride, the third buffer layer has a third carbon doping concentration, and the third carbon doping concentration is less than the first carbon doping concentration.

3. The semiconductor stacked structure as described in claim 2, wherein the concentration of the third carbon doping is on the same order of magnitude as the concentration of the first carbon doping.

4. The semiconductor stacked structure as described in claim 1 further comprises: at least one superlattice stacked layer disposed on the second buffer layer, wherein the at least one superlattice stacked layer comprises a plurality of units stacked in a vertical direction, each unit comprising at least two of aluminum nitride, aluminum gallium nitride, and gallium nitride stacked sequentially in the vertical direction.

5. The semiconductor stacked structure as described in claim 1, wherein the first buffer layer and the second buffer layer are further doped with iron.

6. The semiconductor stacked structure as described in claim 1, wherein the first group III nitride and the second group III nitride contain aluminum, the aluminum content of the first group III nitride is W1%, and the aluminum content of the second group III nitride is W2%, which satisfies the following conditions:

7. The semiconductor stacked structure as described in claim 1, wherein the thickness of the second buffer layer is 300 nanometers to 1000 nanometers.

8. The semiconductor stacked structure as described in claim 1, wherein the second group III nitride comprises aluminum, the second buffer layer comprises a first sublayer and a second sublayer, the aluminum content of the first sublayer is fixed, the aluminum content of the second sublayer is fixed, and the aluminum content of the first sublayer is different from the aluminum content of the second sublayer.

9. The semiconductor stacked structure as described in claim 8, wherein the thickness of the first sublayer is greater than or equal to 100 nanometers and the thickness of the second sublayer is greater than or equal to 100 nanometers.

10. A method for fabricating a semiconductor stacked structure, comprising: providing a substrate; providing a first buffer layer on the substrate, wherein the first buffer layer comprises a carbon-doped group III nitride and the first buffer layer has a first carbon doping concentration; providing a second buffer layer on the first buffer layer, wherein the second buffer layer comprises a carbon-doped group III nitride and the second buffer layer has a second carbon doping concentration, the second carbon doping concentration being at least one order of magnitude lower than the first carbon doping concentration, and the first buffer layer and the second buffer layer being the two buffer layers furthest from the substrate; and providing a channel layer on the second buffer layer.

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