Method for fabricating semiconductor device and semiconductor device

Abstract

Techniques are described for semiconductor device fabrication with increased transistor isolation density by employing a combined cut metal gate (CMG) and epitaxial growth (EPI) patterning (CMGEP) technique to selectively disable transistors in a fabricated array. As described herein, such embodiments provide a larger etching window to avoid EPI damage (i.e., damage to surrounding source / drain structures), and larger margins for avoiding scum defects and photoresist peeling defects. In particular, rather than etching along (in line with) the metal gate line, CMGEP approaches remove a source / drain structure (before or after epitaxial growth) and cut perpendicularly across adjacent metal gate lines in one or more corresponding shallow trench isolation (STI) regions. Techniques are also described for selectively disabling transistors using gate threshold voltage differentiation and / or bottom isolation dielectric deposition.

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