Semiconductor device

Abstract

A semiconductor device comprising multiple semiconductor dies and a joint conductive line. These semiconductor dies are located on both sides of a predetermined cutting area. The joint conductive line electrically connects these semiconductor dies, wherein in a top view, the joint conductive line includes multiple crack prevention corners located in the predetermined cutting area.

Description

Technical Field

[0001] This invention relates to a semiconductor device, and more particularly to a semiconductor device comprising a wire having a crack-prevention structure for connecting multiple chips. Prior Technology

[0002] Conventional integrated circuit (IC) fabrication methods primarily utilize photomasks to define the dimensions of each device component, where device performance is often limited by the size of the two-dimensional wafer. To improve IC performance (e.g., capacity or processing speed) within a limited area, this can be achieved by reducing feature size and / or vertically stacking multiple wafers. However, this also leads to reduced process yield and increased costs. As information processing volumes increase, the performance requirements for ICs also rise. Generally, each wafer in an IC often employs a single-die design. However, due to limitations in process technology, product yield, and other factors, single-die designs struggle to meet the ever-increasing performance demands.

[0003] To improve the performance of integrated circuits, splicing metal lines can be formed between multiple dies during the wafer manufacturing stage, and the wafer can be appropriately diced to form a spliced ​​wafer comprising multiple electrically coupled dies. However, since the splicing metal lines are straight lines intersecting the dicing direction, cracks generated during the dicing process can easily propagate along the splicing metal lines into the dies, reducing product yield. Summary of the Invention

[0004] The present invention provides a semiconductor device that can improve the performance of integrated circuits and reduce damage caused by the dicing process.

[0005] One embodiment of the present invention provides a semiconductor device including a plurality of semiconductor dies and splicing wires. The semiconductor dies are located on both sides of a predetermined dicing region. The splicing wires electrically connect the semiconductor dies, wherein, in the top view, the splicing wires include a plurality of crack-prevention corners located within the predetermined dicing region.

[0006] Based on the above, the crack prevention corner of the splicing wire of the present invention can prevent cracks generated during the cutting process from extending along the splicing wire into the semiconductor die, thereby improving product yield. Simple Explanation of the Diagram

[0007] Figure 1A is a top schematic diagram of a semiconductor device according to an embodiment of the present invention. Figure 1B is a partial enlarged view of Figure 1A, showing a top view schematic diagram of a splicing wire according to an embodiment of the present invention. Figure 1C is a cross-sectional view along line A-A' in Figure 1B. Figure 1D is a cross-sectional view along line B-B' in Figure 1A. Figure 1E is a partial enlarged view of Figure 1A, showing a top view schematic diagram of the splicing wire according to another embodiment of the present invention. Figure 1F is a partial enlarged view of Figure 1A, showing a top view schematic diagram of the splicing wire according to another embodiment of the present invention. Figure 1G is a partial enlarged view of Figure 1D, showing a cross-sectional schematic diagram of a capacitor element according to an embodiment of the present invention. Figure 2A is a top schematic diagram of a semiconductor device according to an embodiment of the present invention. Figure 2B is a partial enlarged view of Figure 2A, showing a top view of the cut spliced ​​wires of the semiconductor device. Figure 2C is a cross-sectional view along line B-B' in Figure 2A. Figure 3 is a partial top view schematic diagram of a semiconductor device according to an embodiment of the present invention. Figure 4A is a top view schematic diagram of a splicing wire according to another embodiment of the present invention. Figure 4B is a top view of the spliced ​​wire in Figure 4A after it has been cut. Figure 5A is a top view schematic diagram of a splicing wire according to another embodiment of the present invention. Figure 5B is a top view of the spliced ​​wire in Figure 5A after it has been cut. Figure 6A is a top schematic diagram of a wafer according to an embodiment of the present invention. Figure 6B is a partially enlarged view of Figure 6A, showing a top view schematic diagram of the splicing wire located between the first semiconductor die and the second semiconductor die in an intermediate step of the semiconductor device. Figure 6C is a cross-sectional view along line B-B' in Figure 6A. Figure 7A is a top schematic diagram of a semiconductor device according to an embodiment of the present invention. Figure 7B is a partial cross-sectional schematic diagram of the semiconductor device in Figure 7A. Implementation

[0008] Referring to Figures 1A to 1D, the semiconductor device in this embodiment is a wafer 10. The wafer 10 may include a plurality of semiconductor dies D and splicing wires 220. These semiconductor dies D are located on both sides of a predetermined dicing region SL. The splicing wires 220 electrically connect adjacent semiconductor dies D. Each semiconductor die D may include an array element 110, an interconnect structure 200, a sealing structure 210, and connection terminals 300 formed on a substrate 100 of the wafer 10. The substrate 100 may include a semiconductor substrate, a glass substrate, or a ceramic substrate, such as a silicon substrate, a silicon-germanium substrate, a silicon carbide substrate, an aluminum nitride substrate, a sapphire substrate, or a combination thereof. Furthermore, the substrate 100 may include silicon-coated insulators, but this disclosure is not limited thereto.

[0009] It should be noted that, for the sake of simplicity, the electrical connection between the splicing wire 220 and the adjacent semiconductor die D is shown as a straight line in Figure 1A. However, the splicing wire 220 disclosed herein is not a straight line. As shown in Figure 1B, which is a partial enlarged view of the dashed box DB1 in Figure 1A, the splicing wire 220 of the present invention includes multiple crack prevention corners CR in the top view, thereby preventing cracks generated during the cutting process from extending along the splicing wire 220 into the semiconductor die D, thereby improving the yield of the semiconductor device. Furthermore, the subsequent Figures 2A, 6A, and 7A are also drawn for the same simplification reasons as described above, and it should be understood that the splicing wire 220 disclosed herein is not a straight line, but rather includes multiple crack prevention corners CR.

[0010] The array element 110 includes a plurality of identical or similar elements, such as a silicon capacitor array including a plurality of silicon capacitor elements or a memory cell array including a plurality of memory cell elements. This disclosure does not limit the type of array element 110. In some embodiments, a buffer layer 102 may be included between the array element 110 and the substrate 100. A cover layer 120 may be disposed on the array element 110.

[0011] In this embodiment, the array element 110 can be a silicon capacitor array, and the silicon capacitor array of one semiconductor die D can be connected in series with the silicon capacitor array of another semiconductor die D via splicing wire 220. This can increase the breakdown voltage of the device. In another embodiment, the silicon capacitor array of one semiconductor die D can be connected in parallel with the silicon capacitor array of another semiconductor die D via splicing wire 220. This can increase the total capacitance of the semiconductor device. As shown in FIG1D, the array element 110 may include a first plate electrode 112, a capacitor element 113, and a second plate electrode 116. The capacitor element 113 is located between the first plate electrode 112 and the second plate electrode 116. It should be noted that, as mentioned earlier, since line B-B' in Figure 1A is used to represent the electrical connection with the adjacent semiconductor die D at the location corresponding to the splicing wire 220, line B-B' at the location corresponding to the splicing wire 220 should be understood as a cross-section according to the extension direction of the splicing wire 220. Therefore, Figure 1D shows the splicing wire 220 extending from one semiconductor die D to another semiconductor die D. Furthermore, for the same reason, the locations in Figures 2C, 6C, and 7B corresponding to the splicing wire 220 should also be understood as cross-sections according to the extension direction of the splicing wire 220.

[0012] Figure 1G corresponds to the position of the dashed box X in Figure 1D. In this embodiment, as shown in Figure 1G, the capacitor element 113 may include a bottom electrode 1131, a dielectric layer 1132, and a top electrode 1133. The dielectric layer 1132 may be disposed on the bottom electrode 1131. The capacitor element 113 may also include a stop layer 1134 disposed on the first plate electrode 112, and the bottom of the bottom electrode 1131 may pass through the stop layer 1134 to contact the first plate electrode 112. It should be noted that the capacitor element 113 in Figure 1G is only one example, and the capacitor element 113 of the present invention can be fabricated according to various known processes and structures, and is not limited to the content shown in this embodiment. In addition, any known structure and process can be used to fabricate the array element 110 disclosed herein, and is not limited to silicon capacitor arrays.

[0013] In this embodiment, the splicing wire 220 can be disposed on the cover layer 120, and the interconnect structure 200 can be disposed above the splicing wire 220. The splicing wire 220 and the interconnect structure 200 can be located in the interlayer dielectric layer 290 on the cover layer 120. In other words, the splicing wire 220 can be disposed above the array element 110. The interconnect structure 200 may include stacked conductive layers 231, 232 and pad layer 230, and the conductive layers 231, 232 and pad layer 230 can be electrically connected through conductive vias. In this embodiment, the conductive layer 231 is located between the conductive layer 232 and the pad layer 230. In some embodiments, the conductive layers 231, 232 include, for example, tungsten, aluminum, copper, alloys of the above metals or other suitable conductive materials. The interconnect structure 200 can be electrically connected to the array element 110 via the splicing wire 220, for example, electrically connected to the first electrode 112 and the second electrode 116 of the array element 110. This allows interconnection between multiple semiconductor dies D to be achieved through splicing wires 220, thereby improving the performance of the semiconductor device (e.g., increasing capacity or improving electrical performance).

[0014] The pad layer 230 is located on top of the interconnect structure 200. In some embodiments, the pad layer 230 may comprise, for example, tungsten, aluminum, copper, an alloy of the above metals, or other suitable conductive materials. In some embodiments, the pad layer 230 and the conductive layers 231, 232 located below it may comprise the same or different conductive materials.

[0015] The interlayer dielectric layer 290 includes a plurality of openings 292, which expose the pad layer 230. A connection terminal 300 may be disposed above the pad layer 230. In this embodiment, the connection terminal 300 may fill the openings 292 and contact the pad layer 230, thereby electrically connecting to the pad layer 230. In some embodiments, an under-bump metallization (UBM) layer may also be included between the connection terminal 300 and the pad layer 230, but this invention is not limited thereto. In some embodiments, the connection terminal 300 may include microbumps, controlled collapse chip connection (C4) bumps, ball grid array (BGA) or other types of connection terminals.

[0016] In some embodiments, the splicing wire 220 connects to semiconductor dies D arranged along the X direction or to semiconductor dies D arranged along the Y direction.

[0017] As shown in Figure 1C, the sealing structure 210 is located at the edge of each semiconductor die D and surrounds the array element 110, thereby protecting the array element 110. For example, the sealing structure 210 can act as a protective barrier to enhance the mechanical strength of the semiconductor die D and prevent the semiconductor die D from being damaged by external forces during the manufacturing process or subsequent packaging and cutting. In addition, the sealing structure 210 helps to prevent moisture and other external contaminants from penetrating into the array element 110 and avoiding any impact on the array element 110.

[0018] Referring to Figures 1B, 1C, and 1D, the sealing structure 210 may include a first sealing ring 211, an open ring 212, a second sealing ring 213, a third sealing ring 214, and a fourth sealing ring 215 stacked together, but this disclosure is not limited thereto. In this embodiment, the splicing wire 220 passes through the opening 2121 of the open ring 212 and is electrically connected to the array element 110. From another perspective, the splicing wire 220 has a portion 2201 that overlaps with the vertical projection of the second sealing ring 213, the third sealing ring 214, and / or the fourth sealing ring 215, but does not overlap with the open ring 212.

[0019] The first sealing ring 211 may be located on the substrate 100. In some embodiments, the first sealing ring 211 may be formed in the cover layer 120 and belong to the same conductive layer as the first electrode 112 or the second electrode 116 of the array element 110. For example, the first sealing ring 211 and the first electrode 112 (or the second electrode 116) may be formed simultaneously via a metal layer deposition process and a patterning process. In some embodiments, the first sealing ring 211 may be electrically connected to the underlying substrate 100 through a conductive via 103, but this disclosure is not limited thereto.

[0020] The open ring 212 may be located above the first sealing ring 211. In this embodiment, the open ring 212 may include a conductive layer and may be electrically connected to the first sealing ring 211 through the conductive via 103. In some embodiments, the splicing wire 220 and the open ring 212 may belong to the same conductive layer. For example, the splicing wire 220 and the open ring 212 may be formed simultaneously via a metal layer deposition process and a patterning process, so that the splicing wire 220 and the open ring 212 are separated from each other.

[0021] The second sealing ring 213 may be located above the open ring 212 and span the splicing conductor 220. In this embodiment, the second sealing ring 213 may be located in the interlayer dielectric layer 290. The second sealing ring 213 may include a conductive layer and may be electrically connected to the open ring 212 through the conductive via 103. In some embodiments, the second sealing ring 213 may belong to the same conductive layer as the conductive layer 232 of the interconnect structure 200. For example, the second sealing ring 213 and the conductive layer 232 may be formed simultaneously via a metal layer deposition process and a patterning process.

[0022] The third sealing ring 214 may be located above the second sealing ring 213 and spans the splicing wire 220. The third sealing ring 214 is electrically connected to the second sealing ring 213 through a conductive via. In this embodiment, the third sealing ring 214 may be located in the interlayer dielectric layer 290. The third sealing ring 214 may include a conductive layer and may be electrically connected to the second sealing ring 213 through the conductive via 103. In some embodiments, the third sealing ring 214 may belong to the same conductive layer as the conductive layer 231 of the interconnect structure 200. For example, the third sealing ring 214 and the conductive layer 231 may be formed simultaneously via a metal layer deposition process and a patterning process.

[0023] The fourth sealing ring 215 may be located above the third sealing ring 214 and spans the splicing wire 220. In this embodiment, the fourth sealing ring 215 may be located in the interlayer dielectric layer 290. The fourth sealing ring 215 may include a conductive layer and may be electrically connected to the third sealing ring 214 through the conductive via 103. In some embodiments, the fourth sealing ring 215 may belong to the same conductive layer as the pad layer 230 of the interconnect structure 200. For example, the fourth sealing ring 215 and the pad layer 230 may be formed simultaneously via a metal layer deposition process and a patterning process.

[0024] In this embodiment, the predetermined cutting region SL is located between the sealing structures 210 of adjacent semiconductor dies D. In some embodiments, the thickness T2 of the interlayer dielectric layer 290 at the predetermined cutting region SL is less than or equal to the thickness T1 of the interlayer dielectric layer 290 located inside the sealing structure 210, so that the top surface of the predetermined cutting region SL is recessed relative to the top surface of the semiconductor die D (not shown in the figure). Furthermore, in this embodiment, by placing the splicing wire 220 at the relatively bottom layer of these metal layers (i.e., the metal layer located between the array element 110 and the interconnect structure 200), the impact of the splicing wire 220 on the surface flatness of the predetermined cutting region SL can be reduced, so no additional planarization process needs to be performed on the predetermined cutting region SL.

[0025] The splicing conductor 220 includes multiple crack-prevention corners CR located between the sealing structures 210 of two adjacent semiconductor dies D. In other words, the crack-prevention corners CR are located within a predetermined cutting region SL. Specifically, in this embodiment, the splicing conductor 220 may include a predetermined cutting portion 220C and crack-prevention portions 220D located on both sides of the predetermined cutting portion 220C. The extension direction of the predetermined cutting portion 220C is different from the extension direction of the predetermined cutting region SL, and these crack-prevention corners CR are located within the crack-prevention portions 220D. In FIG. 1B, the predetermined cutting region SL extends along a first direction E1 (also referred to as the cutting direction), and the crack-prevention portions 220D of the splicing conductor 210 include multiple first segments 220B parallel to the first direction E1 and multiple second segments 220A perpendicular to the first direction E1. The crack-prevention corners CR are located at the junction between the first segments 220B and the second segments 220A. In other words, the second segment 220A can be connected to the first segment 220B via a crack-prevention corner CR. In this embodiment, the crack-prevention corner CR may include a right angle. As shown in FIG1B, the extension direction of the predetermined cut portion 220C may be perpendicular to the first direction E1. In this embodiment, the extension direction of the portion of the splicing wire 220 passing through the opening 2121 of the open ring 212 (i.e., the second segment 220A) is the same as the extension direction of the predetermined cut portion 220C.

[0026] In addition, in some embodiments, wafer 10 may have splicing wires 280 for connecting adjacent semiconductor dies D arranged along a diagonal direction.

[0027] Figure 1E shows a partial enlarged view of the dashed box DB2 in Figure 1A. In this embodiment, the splicing guide 280 includes multiple crack-prevention corners CR in the top view. Specifically, the splicing guide 280 may include a predetermined cut portion 280C and crack-prevention portions 280D located on both sides of the predetermined cut portion 280C. The extension direction of the predetermined cut portion 280C is different from the extension direction of the predetermined cut area SL, and these crack-prevention corners CR are located within the crack-prevention portions 280D. Figures 1F and 1E share the same inventive concept, differing only in the number of crack-prevention corners CR, resulting in different shapes. Furthermore, the splicing guide 280 and the splicing guide 220 share the same inventive concept, therefore, the relevant technical details will not be repeated. The predetermined cut portion 280C is the portion that will overlap with the cutting line SR during the cutting process.

[0028] In other embodiments of the invention, a semiconductor device MD can be fabricated by dicing a wafer 10. For example, the wafer 10 can be diced along the dashed frame shown in FIG. 2A to obtain the semiconductor device MD. The dicing process is performed, for example, by a saw or other suitable means. The semiconductor device MD contains a plurality of semiconductor dies D, and the number of semiconductor dies D in a single semiconductor device MD can be determined as needed. In this embodiment, the array element 110 may be a memory cell array including a plurality of memory cell elements. Each semiconductor die D may have any capacity size, for example, but not limited to 2GB. According to the invention, the capacity of the semiconductor device MD can be flexibly adjusted by changing the dicing range. For example, the higher the required capacity, the more semiconductor dies D the semiconductor device MD includes.

[0029] In this way, the design of semiconductor dies D does not need to be changed to meet different capacity requirements, thereby reducing the design cost of semiconductor device MD. Furthermore, this invention uses splicing wires 220 to interconnect semiconductor dies D to semiconductor dies D, allowing multiple semiconductor dies D to be integrated into a single semiconductor device MD, rather than combining multiple semiconductor dies D through packaging. This reduces the area of ​​the semiconductor device MD (also known as a chip).

[0030] Referring to Figures 2B and 2C, during the dicing process, the wafer 10 can be diced along the dicing line SR in a predetermined dicing area SL, leaving a dicing mark SW at the edge of the semiconductor device MD. In this embodiment, the splicing wire 220 in the predetermined dicing area SL located at the edge of the semiconductor device MD is diced, leaving a diced splicing wire C220. In other words, the semiconductor die D located at the edge of the semiconductor device MD includes the diced splicing wire C220. The diced splicing wire C220 passes through the opening 2121 of the open ring 212 of the sealing structure 210 (refer to Figure 1C) and extends to the edge of the semiconductor device MD (i.e., the dicing mark SW).

[0031] In addition, the central region of the semiconductor device MD includes a number of uncut predetermined cutting regions SL, and these uncut predetermined cutting regions SL contain uncut splicing wires 220, as shown in Figure 1B.

[0032] In this embodiment, the crack prevention corner CR prevents cracks generated during the cutting process from extending along the splicing wire 220 into the semiconductor die D, thus avoiding damage to the array element 110 located inside the sealing structure 210. In this embodiment, both the uncut splicing wire 220 (see FIG. 1B) and the cut splicing wire C220 (see FIG. 2B) include the crack prevention corner CR. Furthermore, components that are the same as or similar to those shown in the embodiments of FIG. 1A to FIG. 1F will be represented by the same component symbols, and these same or similar components will not be described again.

[0033] In the foregoing embodiments, each semiconductor die D includes a sealing structure 210, but this disclosure is not limited to this. The number of sealing structures 210 can be adjusted as needed. As shown in FIG3, a single semiconductor die D may include multiple sealing structures 210. These sealing structures 210 are arranged between the array element 110 and the edges of each semiconductor die D, such that one sealing structure 210 surrounds another sealing structure 210.

[0034] When a single semiconductor die D comprises multiple hermetically sealed structures 210, the splicing wires coupled to it pass through the multiple hermetically sealed structures 210 of this semiconductor die D. As shown in Figure 3, the cut splicing wire C220 passes through the opening 2121 of the open ring 212 of the multiple hermetically sealed structures 210. It should be noted that, although not shown, it should be understood that the uncut splicing wires also pass through the opening 2121 of the open ring 212 of the multiple hermetically sealed structures 210. Furthermore, the cut splicing wire C220 in Figure 3 is only used to illustrate its relative positional relationship with the hermetically sealed structure 210, and the complete structure of the cut splicing wire C220 is not shown.

[0035] In the foregoing embodiments, each splicing conductor 220 (refer to FIG. 1B) has four crack-prevention corners CR located in a predetermined cutting area SL; however, the present invention does not limit the number of crack-prevention corners CR. Preferably, each splicing conductor 220 may include two or more crack-prevention corners CR located in the predetermined cutting area SL. For example, the number of crack-prevention corners CR may be a multiple of 2. The following examples are based on other variations of the present invention.

[0036] Referring to Figures 4A and 4B, in this embodiment, the splicing wire 220 may include eight crack-prevention corner CRs. Furthermore, the cut splicing wire C220 may include four crack-prevention corner CRs. In addition, components that are the same as or similar to those in the foregoing embodiments will be represented using the same element symbols, and these same or similar components will not be described again.

[0037] Please refer to Figures 5A and 5B. In this embodiment, the splicing conductor 220 includes twelve crack-prevention corner CRs. Furthermore, the cut splicing conductor C220 includes six crack-prevention corner CRs. Additionally, components that are the same as or similar to those in the previous embodiments will be represented using the same element symbols, and these same or similar components will not be described again.

[0038] In the above embodiments, the connection terminal 300 of the semiconductor die D (refer to FIG. 2C) is electrically connected to the pad layer 230; however, the present invention is not limited thereto. Other variations based on the present invention will be exemplified below.

[0039] Referring to Figures 6A and 6B, in this embodiment, each semiconductor die in the wafer 10 can be tested before forming the connection terminal 300 (shown in Figure 7B). After testing, semiconductor dies without abnormalities are marked as first semiconductor die D, and semiconductor dies with abnormalities (such as open circuits, short circuits, or leakage) are marked as second semiconductor die D'. The second semiconductor die D' has the same structure as the first semiconductor die D; the only difference is that the second semiconductor die D' may experience electrical or functional abnormalities due to process deviations, contamination, or other factors. The detailed structure of the second semiconductor die D' will not be repeated here.

[0040] In this embodiment, after testing, the position of the second semiconductor die D' on the wafer 10 can be determined. Then, a barrier structure 240 can be formed on the pad layer 230 of the interconnect structure 200 of the second semiconductor die D' using three-dimensional printing technology, lithography technology, or other suitable methods. For example, the barrier structure 240 can be filled into the opening 292 of the interlayer dielectric layer 290 of the second semiconductor die D', so that the barrier structure 240 contacts the pad layer 230.

[0041] Next, as shown in Figures 7A and 7B, connection terminals 300 are disposed above each pad layer 230. The connection terminal 300 of the first semiconductor die D is electrically connected to the pad layer 230, while the connection terminal 300 of the second semiconductor die D' is electrically isolated from the pad layer 230 because the barrier structure 240 is disposed between the pad layer 230 and the connection terminal 300. In this embodiment, due to the presence of the barrier structure 240, the top surface of the connection terminal 300 of the first semiconductor die D is lower than the top surface of the connection terminal 300' of the second semiconductor die D'.

[0042] After forming the connection terminal 300, the wafer 10 can be diced to obtain the semiconductor device MD. In this embodiment, the semiconductor device MD may include a first semiconductor die D and a second semiconductor die D'. In the conventional manufacturing process of spliced ​​chips, if any semiconductor die is found to be abnormal during the testing phase, the entire spliced ​​chip will be scrapped. Alternatively, a complex dicing process must be used to remove the specific abnormal semiconductor die. This results in resource waste. In contrast, this embodiment, by setting the barrier structure 240, not only can the interference of the second semiconductor die D' be reduced, but the semiconductor device MD can also contain abnormal semiconductor dies (i.e., the second semiconductor die D'). In this way, this embodiment does not require a complex dicing process to specifically remove the second semiconductor die D' in the semiconductor device MD, thereby improving process yield and reducing resource consumption, thus reducing manufacturing costs.

[0043] According to the semiconductor device of the present invention, in actual production, regardless of the number of semiconductor chips required for the integrated circuit to meet performance requirements, the same wafer can be produced uniformly, for example, a wafer containing 1000 semiconductor chips. Then, based on the required performance, a dicing process is used to cut semiconductor devices with four semiconductor chips, two semiconductor chips, or only one semiconductor chip. This allows the use of the same photomask to fabricate integrated circuits with different performance characteristics, and also reduces the update frequency of lithography equipment, shortening development time and reducing production costs. Furthermore, the crack-prevention corner of the splicing conductor of the present invention prevents cracks generated during the dicing process from extending along the splicing conductor into the semiconductor chip, thereby improving product yield. Therefore, the semiconductor device of the present invention belongs to a green semiconductor technology.

[0044] 10: Wafer 100: Base 102: Buffer layer 110: Array element 112: First flat plate electrode 113: Capacitor Components 1131: Bottom electrode 1132: Dielectric layer 1133: Top electrode 1134: Stopping Layer 116: Second plate electrode 120: Covering layer 200: Internal Wiring Structure 210: Sealing structure 211: First sealing ring 212: Open ring 213: Second sealing ring 214: Third sealing ring 215: Fourth sealing ring 220: Splicing wire 220B: First line segment 220A: Second line segment 230: Subbase layer 240: Barrier Structure 280: Splicing wire 290: Interlayer dielectric layer 292: Opening 300, 300': Connecting terminals 2121: Opening of an open ring 2201: Part C220: Cut spliced ​​wire CR: Crack prevention at corners D: Semiconductor die / First semiconductor die D': Second semiconductor die DB1,DB2,X: Dashed border E1: First Direction MD: Semiconductor Device SL: Pre-defined cutting area SR: Cutting line SW: Cut marks

Claims

1. A semiconductor device, comprising: Multiple semiconductor chips are located on both sides of a predetermined cutting region, each semiconductor chip including an array element; and a splicing wire extending through the predetermined cutting region to electrically connect the array element of one of the semiconductor chips to the array element of another of the semiconductor chips, wherein, in a top view, the splicing wire includes multiple crack prevention corners located in the predetermined cutting region.

2. The semiconductor device of claim 1, wherein the splicing conductor includes a predetermined cut portion and a crack prevention portion located on both sides of the predetermined cut portion, the extension direction of the predetermined cut portion is different from the extension direction of the predetermined cut area, and the crack prevention corners are located in the crack prevention portion.

3. The semiconductor device of claim 2, wherein the predetermined dicing region extends along a first direction, and the crack prevention portion of the splicing conductor includes: Multiple first line segments, each of which extends parallel to the first direction; And a plurality of second segments, each of which extends perpendicular to the first direction and is connected to one of the first segments via one of the cracks that prevent the corners.

4. The semiconductor device as claimed in claim 3, wherein the extension direction of the predetermined cut portion is perpendicular to the first direction.

5. The semiconductor device of claim 1, wherein the number of crack prevention corners is greater than or equal to 2.

6. The semiconductor device of claim 1, wherein the number of crack prevention corners is a multiple of 2.

7. The semiconductor device of claim 1, wherein the crack prevention corners include right angles.

8. The semiconductor device as claimed in claim 1, wherein, Each semiconductor die includes a sealing structure located at the edge of each semiconductor die and surrounding the array element. The sealing structure includes a first sealing ring and an open ring stacked together. The splicing wire extends through an opening of the open ring of one of the semiconductor dies, the predetermined cutting area, and an opening of the open ring of the other semiconductor die to electrically connect the array element of one of the semiconductor dies to the array element of the other semiconductor die.

9. The semiconductor device of claim 1, wherein the array element is a silicon capacitor array, and the silicon capacitor array of one of the semiconductor chips is connected in series with the silicon capacitor array of the other of the semiconductor chips via the splicing wire.

10. The semiconductor device of claim 1, wherein the array element is a silicon capacitor array, and the silicon capacitor array of one of the semiconductor chips is connected in parallel with the silicon capacitor array of the other of the semiconductor chips via the splicing wire.

11. The semiconductor device of claim 1, wherein the splicing wire is disposed above the array element, and each of the semiconductor chips further comprises: An interconnect structure is disposed above the splicing conductor and electrically connected to the array element via the splicing conductor. The interconnect structure includes a conductive layer and a pad layer stacked together, and a connection terminal is disposed above the pad layer. The semiconductor chips include a first semiconductor chip and a second semiconductor chip, and the connection terminal of the first semiconductor chip is electrically connected to the pad layer.

12. The semiconductor device of claim 11, wherein the second semiconductor die further comprises: A barrier structure is disposed between the pad layer and the connection terminal, thereby electrically isolating the connection terminal of the second semiconductor die from the pad layer.

13. The semiconductor device of claim 8, wherein the sealing structure further includes a second sealing ring, the open ring being disposed on the first sealing ring, and the second sealing ring being disposed on the open ring and extending across the splice wire.

14. The semiconductor device of claim 8, wherein the splicing wire of one of the semiconductor chips located at an edge of the semiconductor device passes through the open loop and extends to the edge of the semiconductor device.

15. The semiconductor device of claim 8, wherein each semiconductor die includes a plurality of the sealing structures, and the sealing structures are arranged between the array element and the edge of each semiconductor die such that one of the sealing structures surrounds the other of the sealing structures.

16. The semiconductor device of claim 8, wherein the splicing wire includes a predetermined cut portion and a crack prevention portion located on both sides of the predetermined cut portion, the extension direction of the predetermined cut portion is different from the extension direction of the predetermined cut area, and the crack prevention corners are located in the crack prevention portion, wherein the extension direction of the portion of the splicing wire passing through the opening of the open ring is the same as the extension direction of the predetermined cut portion.

17. The semiconductor device of claim 1, comprising a plurality of the splicing wires, one of which is connected to the semiconductor chips arranged along the X direction, another of which is connected to the semiconductor chips arranged along the Y direction, and yet another of which is connected to the semiconductor chips arranged along a diagonal direction.

18. The semiconductor device of claim 8, wherein the splicing wire includes a plurality of line segments passing through the sealing structure and a predetermined cut portion, and the line segments passing through the sealing structure and the predetermined cut portion form a non-linear extension configuration in the top view.

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