Semiconductor structure and manufacturing method thereof

TW202635142AActive Publication Date: 2026-08-16WINBOND ELECTRONICS CORP
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Patent Information

Application Number
TW114104064
Authority / Receiving Office
TW · TW
Patent Type
Applications
Current Assignee / Owner
Filing Date
2025-02-05
Publication Date
2026-08-16
Estimated Expiration
2045-02-04

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  • Figure TWG2TA001072015_001
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    Figure TWG2TA001072015_002
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    Figure TWG2TA001072015_003
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Abstract

A semiconductor structure and a manufacturing method of this invention is provided. The semiconductor structure includes a substrate having an active area, a plurality of word line structures, a doped region, a plurality of pillar structures, a spacer and a contact. The plurality of word line structures are disposed in the substrate. The extending direction of the word line structure is interlaced with the extending direction of the active area. The doped region is disposed in the substrate in the active area and located between adjacent word line structures. The plurality of pillar structures are disposed on the substrate to surround the doped region. The spacer is disposed on the sidewall of the pillar structure, so that the pillar structure and the spacer jointly cover the end of the active area. The contact is disposed on the doped region and in contact with the spacer.
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Claims

1. A semiconductor structure, comprising: The substrate contains active regions; Multiple character line structures are disposed in the substrate, wherein the extension direction of the character line structure is staggered with the extension direction of the active area; A doped region is disposed in the substrate within the active region and located between adjacent word line structures; a plurality of columnar structures are disposed on the substrate to surround the doped region; A spacer wall is disposed on the entire sidewall of the columnar structure, such that the columnar structure and the spacer wall together cover the end of the active region; and a contact window is disposed on the doped region and contacts the spacer wall.

2. The semiconductor structure as claimed in claim 1, wherein two of the plurality of columnar structures are each located at opposite ends of the active region in the extension direction of the active region, and the columnar structures do not completely cover the ends of the active region.

3. The semiconductor structure as claimed in claim 1, wherein the top surface of the contact window, the top surface of the columnar structure, and the top surface of the spacer wall are coplanar.

4. The semiconductor structure as claimed in claim 1, wherein the columnar structure comprises: A silicon oxide layer is disposed on the substrate; And a doped polycrystalline silicon layer is disposed on the silicon oxide layer.

5. The semiconductor structure as claimed in claim 1, wherein the top surface of the substrate below the columnar structure is higher than the top surface of the rest of the substrate.

6. A method for manufacturing a semiconductor structure, comprising: A substrate is provided, wherein the substrate has an active region, a plurality of word line structures are formed in the substrate, and the extension directions of the word line structures intersect the extension direction of the active region; a doped region is formed in the substrate in the active region, wherein the doped region is located between adjacent word line structures; a plurality of columnar structures are formed on the substrate, wherein the plurality of columnar structures surround the doped region; a spacer wall is formed on the entire sidewall of the columnar structure, such that the columnar structure and the spacer wall together cover the end of the active region; and a contact window is formed on the doped region, wherein the contact window contacts the spacer wall.

7. A method for manufacturing a semiconductor structure as claimed in claim 6, wherein the method for forming the columnar structure, the spacer wall, and the contact window comprises: A silicon oxide layer is formed on the substrate; A doped polycrystalline silicon layer is formed on the silicon oxide layer; A mask layer is formed on the doped polycrystalline silicon layer; a patterning process is performed on the mask layer, the doped polycrystalline silicon layer, and the silicon oxide layer to form the plurality of initial columnar structures, wherein the initial columnar structures are formed by stacking the silicon oxide layer, the doped polycrystalline silicon layer, and the mask layer, and two of the plurality of initial columnar structures are each located at two opposite ends of the active region in the extension direction of the active region, and the initial columnar structure located at the end does not completely cover the end of the active region; a spacer material layer is conformally formed on the substrate; Perform an etch-back process to remove part of the spacer wall material layer until the top surface of the mask layer and the substrate are exposed; A contact window material layer is formed on the substrate, wherein the contact window material layer covers the plurality of initial columnar structures; Remove part of the contact window material layer until the top surface of the cover layer is exposed; And remove the covering layer to form the columnar structure.

8. A method of manufacturing a semiconductor structure as claimed in claim 7, wherein after the back etch process, the mask layer has a curved top surface.

9. A method of manufacturing a semiconductor structure as claimed in claim 7, wherein after a portion of the contact window material layer is removed, the top surface of the contact window material layer and the top surface of the doped polycrystalline silicon layer in the initial columnar structure are coplanar.

10. A method of manufacturing a semiconductor structure as claimed in claim 7, wherein when removing the mask layer, a portion of the spacer material layer is also removed, such that the top surface of the contact window material layer, the top surface of the doped polycrystalline silicon layer, and the top surface of the spacer material layer are coplanar.