Integrated circuit device and method for forming integrated circuit

Abstract

A device is provided. The device includes: a first substrate; a first interconnect structure on the first substrate; a second substrate; a second interconnect structure on the second substrate, the first substrate being bonded to the second substrate by a hybrid bond between the first interconnect structure and the second interconnect structure; an active circuit region in the second substrate, the active circuit region including a via that extends through the second substrate; and at least four alignment patterns that are offset from the via. Each of the alignment patterns includes: a first conductive feature in a first top metal layer of the first interconnect structure; and a second conductive feature in a second top metal layer of the second interconnect structure, the second conductive feature having size that does not exceed that of the first conductive feature.

Description

[Technical Field]

[0001] This disclosure relates to an integrated circuit device and a method for forming an integrated circuit. [Previous Technology]

[0002] Semiconductor devices are formed on, in, and / or from semiconductor wafers and are used in a variety of electronic devices, such as mobile phones, laptops, desktop computers, tablets, watches, gaming systems, and various other industrial, commercial, and consumer electronics. One or more semiconductor manufacturing processes are performed to form semiconductor devices on, in, and / or from semiconductor wafers. [Summary of the Invention]

[0003] According to some embodiments of the present disclosure, an integrated circuit device is provided, comprising a first substrate, a first interconnect structure, a second substrate, a second interconnect structure, an active circuit region, and alignment patterns. The first interconnect structure is located on the first substrate. The second interconnect structure is located on the second substrate, and the first substrate is bonded to the second substrate by a hybrid bond between the first interconnect structure and the second interconnect structure. The active circuit region is located in the second substrate and includes a via extending through the second substrate. At least four alignment patterns are offset from the via. Each alignment pattern includes: a first conductive feature located in a first top metal layer of the first interconnect structure and a second conductive feature located in a second top metal layer of the second interconnect structure. The size of the second conductive feature does not exceed the size of the first conductive feature.

[0004] According to some embodiments of the present disclosure, a method for forming an integrated circuit includes the following steps: Forming a first wafer. Forming a first interconnect structure on the first wafer, the first interconnect structure including at least four first alignment features located in a first top metal layer of the first interconnect structure. Forming a second wafer. Forming a second interconnect structure on the second wafer, the second interconnect structure including at least four second alignment features located in a second top metal layer of the second interconnect structure. Bonding the first wafer to the second wafer by forming a hybrid bond between the first interconnect structure and the second interconnect structure, each first alignment feature overlapping with a corresponding second alignment feature. Determining nonlinear alignment distortion of the first wafer and the second wafer based on the overlap of the first alignment features and the second alignment features. Determining at least one via location based on the nonlinear alignment distortion. Forming a via at the at least one via location.

[0005] According to some embodiments of this disclosure, a method for forming an integrated circuit includes the following steps: A first wafer is provided, the first wafer having a first interconnect structure. A second wafer is provided, the second wafer having a second interconnect structure. A bonding structure is formed by bonding the first wafer to the second wafer, including: forming a hybrid bond between the first interconnect structure and the second interconnect structure, the bonding structure including at least four alignment marks, each alignment mark located in the first interconnect structure and the second interconnect structure. Based on these alignment marks, a nonlinear alignment distortion of the first wafer and the second wafer is determined. The nonlinear alignment distortion is fed forward to a lithography process. At least one via is formed in the second wafer by the lithography process.

Implementation Method

[0006] The following disclosure provides several different embodiments or instances for implementing different features of the provided object. Specific examples of components and arrangements are described below to simplify the content of this disclosure. Of course, these are merely examples and are not intended to be limiting. For example, the following description of forming a first feature above or on a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which an additional feature is formed between the first and second features such that the first and second features do not need to be in direct contact. Furthermore, element symbols or letters may be repeated in various instances of this disclosure. This repetition is for simplicity and clarity and does not in itself specify a relationship between the various embodiments or configurations discussed.

[0007] Furthermore, for ease of description, spatially relative terms such as "below," "under," "below," "above," and "above" may be used herein to describe the relationship between one element or feature and another element or feature as shown in the figures. In addition to the orientations shown in the figures, the spatially relative terms are intended to cover different orientations of the device in use or operation. The device may be oriented in other ways (rotated 90 degrees or otherwise), and the spatially relative descriptive terms used herein shall be interpreted accordingly.

[0008] The terms "overlapping" and / or similar terms may be used to describe an element or feature that is perpendicularly coincident with another element or feature and is higher than the other element or feature. For example, if the height of a first element is higher than that of a second element and at least a portion of the first element is perpendicularly coincident with at least a portion of the second element, then the first element overlaps the second element.

[0009] The terms "substitute" and / or similar terms may be used to describe an element or feature that is perpendicularly coincident with another element or feature and is at a lower height than the other element or feature. For example, if the height of a first element is lower than that of a second element and at least a portion of the first element is perpendicularly coincident with at least a portion of the second element, then the first element is substituted with the second element.

[0010] The term "above" can be used to describe an element or feature that is higher than another element or feature. For example, if the height of the first element is higher than that of the second element, then the first element is above the second element.

[0011] The term "below" can be used to describe an element or feature whose height is lower than that of another element or feature. For example, if the height of the first element is lower than that of the second element, then the first element is located below the second element.

[0012] With advancements in advanced semiconductor process nodes, wafer-on-wafer (WoW) processing technology (sometimes referred to as 3D wafer stacking) represents a significant advancement in semiconductor manufacturing, increasing transistor density and enhancing device performance. WoW involves stacking multiple wafers by direct bonding or using intermediate layers (such as through-silicon vias, TSVs) that are vertical electrical connections through silicon. WoW processing offers several benefits. By stacking wafers, more components can be integrated into a smaller footprint, effectively increasing the number of transistors or other components per die area. Reduced interconnect lengths due to vertical stacking reduce power consumption, accelerate signal transmission, and improve overall performance due to reduced parasitic capacitance and inductance. Different types of chips (such as logic, memory, and sensors) can be integrated into a single package, thereby improving performance characteristics associated with each technology. WoW processing enables the formation of complex systems with multiple functions within the same package, which is beneficial for applications requiring high data throughput and energy efficiency. WoW (Work-of-Warp) processing technology is conducive to the creation of advanced, compact, and efficient electronic devices, which may include computing, communication, and automotive electronic systems. WoW processing faces challenges in managing thermal issues, achieving high-precision bond alignment, and providing long-term device reliability.

[0013] When bonding two wafers to form a vertical wafer stack, a well-determined alignment accuracy between wafers is conducive to avoid overlapping errors when additional features are formed after bonding. Alignment precision may include linear terms (e.g., translation, rotation, expansion / contraction) and nonlinear terms (which may be referred to as “distortion”). For example, to determine the overlap offset at each TSV position, the alignment accuracy can be determined by resorting to alignment markers included in the wafer. As the circuit feature size shrinks and the association of nonlinear alignment terms with overlap errors becomes stronger, for each exposure the lens or “field” including a single alignment mark position becomes increasingly insufficient to obtain a precise judgment of in-field alignment accuracy. Measurement of key junction alignment accuracy after wafer thinning reduces the ability to perform rework because the thinned wafer is difficult to detach without cracking. Overlapping pilot data were used to generate a single calibration formulation for distortion compensation applied to the entire batch of wafers. Overlapping feedback data can be provided using a pilot gold-calibrated formula.

[0014] In an embodiment of the present elucidating content, a method of performing WoW processing resorts to determining the alignment accuracy (AA) of a key junction using an alignment monitoring pattern. The alignment monitoring pattern may include at least four alignment markers, at least two of which are in-field alignment markers. The high similarity between junction AA and overlay (OVL) enables accurate prediction of bond alignment distortion, which is fed-forward to subsequent processes (e.g., microfilming for TSV formation), thereby reducing rework rate and increasing yield. Alignment monitoring patterns provide improved precision (e.g., within 1 nm). The alignment monitoring pattern provides measurements during the post-keying phase before the thinning phase, the thinning phase or even any dorsal interconnection phase before microfiltration. The alignment monitoring patterns had reduced dimensions (e.g., 15 μm˟15 μm to 60 μm˟60 μm), allowing for in-field measurements. Alignment of the monitoring pattern reduces cost by reducing the number of exposure / overcover measurement / return cycles and improving cycle times. Alignment monitoring patterns can be included in many wafer-on-wafer products.

[0015] FIG.

[0016] Figure 2 illustrates flowcharts of some embodiments of the method 200 for forming an integrated circuit device according to some embodiments. Although method 200 is described and illustrated below as a series of actions or events, it should be understood that the order in which these actions or events are shown should not be construed as limiting. For example, some actions may occur in a different order and / or simultaneously with other actions or events other than those shown and / or described herein. Furthermore, not all actions shown may be necessary to implement one or more of the states or embodiments described herein. In addition, one or more actions described herein may be performed in one or more separate actions and / or stages.

[0017] In Figure 1A, an in-process IC wafer 100 (or simply "first wafer") is provided, corresponding to action 204 in Figure 2. The in-process IC wafer 100 may include integrated circuit die regions 110 located on and / or in a semiconductor substrate 102. In some embodiments, the in-process IC wafer 100 is formed by process operations, which may include patterning, deposition, cleaning, planarization, annealing, epitaxial growth, etc. Process operations form circuit features such as metal gates, epitaxial source / drain electrodes, conductive vias, conductive traces, etc.

[0018] In some embodiments, the semiconductor substrate 102 includes at least one of a substrate, a photomask, a semiconductor device, a dielectric layer, an epitaxial layer, a silicon-on-insulator (SOI) structure, a semiconductor layer, a conductive material layer, and a die. The semiconductor substrate 102 includes at least one of silicon, germanium, carbide, arsenide, gallium, arsenic, phosphide, indium, antimonide, SiGe, SiC, GaAs, GaN, GaP, InGaP, InP, InAs, InSb, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, GaInAsP, or other suitable materials. The semiconductor substrate 102 includes at least one of single-crystal silicon, silicon with a <100> crystal orientation, silicon with a <110> crystal orientation, silicon with a <111> crystal orientation, or other suitable materials. Other structures and / or configurations of the semiconductor substrate 102 are within the scope of this disclosure.

[0019] In some embodiments, the IC die region 110 may be a work-in-process die or a finished die to be monolithized in subsequent process operations. The IC die region 110 may be or include a microcontroller (MCU), a microprocessor (MPU), a graphics processing unit (GPU), an artificial intelligence (AI) accelerator, a memory IC, an analog IC, a logic IC, an optoelectronic device, a power management IC, or a wireless communication IC. In some embodiments, the IC die regions 110 are arranged in one or more columns 112 and one or more rows 113. Columns 112 extend along a first direction D1 and are arranged along a second direction D2. Rows 113 extend along the second direction D2 and are arranged along the first direction D1. Each IC die region 110 may be located in a photolithography field 114, the size of which is related to a single exposure "lens" from a mask. The photolithography field 114 may include at least two IC die regions 110. For example, the size of the lithography field 114 is approximately 26 mm × 33 mm, and the size of each IC die region 110 is approximately 10 mm × 10 mm or smaller. Other sizes of the IC die region 110 are also envisioned as embodiments herein.

[0020] In some embodiments, each IC die region 110 includes one or more patterned layers of different materials configured to form electronic circuits. Components of each IC die region 110 may include transistors, interconnects, capacitors, resistors, inductors, etc. The IC die region 110 may include a number of material layers, such as a substrate 102, epitaxial layer, isolation layer, gate dielectric layer, gate electrode layer, source / drain layer, contact layer, interconnect layer, dielectric layer, passivation layer, etc. Forming the material layers may include performing one or more semiconductor processes, such as deposition, lithography, etching, doping, planarization, etc. Along a vertical axis perpendicular to the main surface of the IC die region 110, from bottom to top, the IC die region 110 may include device regions and interconnect regions located on the device regions. Device regions typically include transistors and capacitors, while interconnect regions typically include interconnects and capacitors, inductors, resistors, etc. The transistor may be or include a field-effect transistor (FET), which may include planar transistors, fin FETs (or "FinFETs"), nanostructure FETs (e.g., wafer FETs), vertical FETs, etc. In some embodiments, the interconnect region may include memory devices, such as phase-change random access memory (PCRAM) devices, magnetoresistive random access memory (MRAM) devices, and / or other suitable memory devices.

[0021] In some embodiments, before the first wafer 100 is bonded to the second wafer in subsequent operations, an interconnect structure or a redistribution layer (RDL) structure may be formed on the active surface of the first wafer 100. For example, the first wafer 100 may include a device layer in which transistors are disposed, and may further include a first interconnect structure located on the device layer, the first interconnect structure having a front-end-of-line (FEOL) interconnect, a mid-end-of-line (MEOL) interconnect, and a back-end-of-line (BEOL) interconnect. The RDL structure may be formed on the BEOL interconnect, such as on the top metal layer of the BEOL interconnect. The RDL structure may include at least two dielectric layers in which metallization features (e.g., vias and traces) are embedded. The top metal layer of the RDL structure may include active pads or active contacts for forming signal connections with the second wafer. The top metal layer of the RDL structure may include first alignment features, which may be first conductive features. After bonding, the first alignment feature can directly overlap with the second alignment feature of the second wafer. Alignment accuracy can be determined based on the overlap accuracy between the first and second alignment features. Each pair of overlapping first and second alignment features can be collectively referred to as alignment marks. Each integrated circuit die region 110 can include an alignment pattern having at least four alignment marks. That is, when a single mask exposure is associated with the entire integrated circuit die region 110, each single mask exposure can include an alignment pattern comprising at least four alignment marks. In some embodiments, at least two alignment marks are in-field alignment marks, meaning that the alignment marks are formed in the active circuit region of the IC die region 110, rather than on the periphery of the IC die region 110 or within scribe lines surrounding the IC die region 110.

[0022] In Figure 1B, a second wafer 104 is provided, corresponding to action 206 in Figure 2, and the second wafer 104 is bonded to the first wafer 102, corresponding to action 208 in Figure 2.

[0023] The second wafer 104 may be similar to the first wafer 102 in some respects, but may include circuitry or components different from those of the first wafer 102. As a non-limiting example, the first wafer 102 may be bonded to the second wafer 104 to form a complementary metal-oxide-semiconductor (CMOS) image sensor (CIS). In this example, the second wafer 104 may include a backside illumination (BSI) image sensor, and the first wafer 102 may include readout and controller circuitry, image processing circuitry, digital signal processor (DSP) circuitry, etc. The formation of the second wafer 104 may include process operations similar to those described with reference to Figure 1A, such as etching, deposition, cleaning, planarization, epitaxial growth, etc.

[0024] During bonding, the first wafer 102 may be bonded to the second wafer 104 by bonding equipment 120. Bonding equipment 120 may include a first stage 122, a second stage 124, and a press 126. The first wafer 102 is supported and / or held by the first stage 122. The second wafer 104 is supported and / or held by the second stage 124. The press 126 is operable to translate the second stage 124 toward the first stage 122 along a third direction D3 (or "vertical direction D3") to press the first wafer 102 and the second wafer 104 together.

[0025] In operation, the bonding device 120 may include one or more high-precision alignment mechanisms, such as optical or mechanical structures, to improve the alignment of alignment features 1021, 1041, 1023, 1043, 1025, and 1045 of the RDL structure of the first wafer 102 and the second wafer 104. The bonding device 120 may apply substantially uniform pressure to the surfaces of the first wafer 102 and the second wafer 104. For hybrid bonding, a dielectric-dielectric bond is initially formed, followed by a metal-metal (e.g., copper-copper) bond during the annealing operation. The bonding device 120 may include heating capabilities to achieve temperatures favorable to the annealing operation, which is beneficial to hybrid bonding. The temperature range may be from room temperature for initial bonding to about 200°C to 300°C or higher for metal diffusion and solidification. In some embodiments, prior to bonding, the surfaces (especially the RDL) of the first wafer 102 and the second wafer 104 are prepared to be flat and clean. This may include performing chemical mechanical polishing (CMP) to recess alignment features 1021, 1041, 1023, 1043, 1025, 1045 to a level slightly below the dielectric surface to allow expansion and bonding. To prevent contamination that could lead to porosity or bonding defects, the bonding apparatus 120 may operate in a cleanroom environment or under controlled atmospheric conditions.

[0026] During the formation of the dielectric junction, the oxide layers on the first wafer 102 and the second wafer 104 may come into contact with each other and form a weak junction at room temperature or slightly above temperature. The first wafer 102 and the second wafer 104 are then heated to allow alignment features 1021, 1041, 1023, 1043, 1025, and 1045 to expand, thereby producing the structure shown in Figure 1C. Although not depicted separately in Figure 1B, conductive active pads may be included in the first wafer 102 and the second wafer 104, and expand, come into contact with each other, and form a strong metallic junction via diffusion during the bonding process.

[0027] In Figure 1C, the first wafer 102 and the second wafer 104 are bonded to each other. As shown, after bonding, some or all of the alignment features 1021, 1041, 1023, 1043, 1025, and 1045 may be misaligned. For example, the first alignment feature 1021 and the corresponding second alignment feature 1041 are misaligned by a first separation distance S1 along the first direction D1. In another example, the first alignment feature 1023 and the corresponding second alignment feature 1043 are misaligned by a second separation distance S3 along the first direction D1. The first separation distance S1 and the second separation distance S3 may be linear misalignments (such as translation, rotation, or extension), nonlinear misalignments, or a combination of both.

[0028] In Figure 1D, a linear alignment term caused by misalignment between alignment features 1023 and 1043 is determined, corresponding to action 210 in Figure 2. As shown, due to a first translation 130X, the first alignment feature 1023 and the second alignment feature 1043 are offset from each other along a first direction D1. Due to a second translation 130Y, the first alignment feature 1023 and the second alignment feature 1043 are offset from each other along a second direction D2. In some embodiments, due to the expansion 130N of the first wafer 102, the second wafer 104, or both, the first alignment feature 1023 and the second alignment feature 1043 are offset from each other along the first direction D1 and / or the second direction D2. Due to the rotation 130R of the first wafer 102, the second wafer 104, or both, the first alignment feature 1023 and the second alignment feature 1043 have an angular offset from each other, as shown by angle θ1. In addition to linear effects (e.g., translation, rotation, expansion), the first alignment feature 1023 and the second alignment feature 1043 may be offset from each other due to nonlinear effects.

[0029] In Figure 1E, infrared (IR) light (or "light in the infrared spectrum") 1200 is directed to alignment mark 1400, which includes a first alignment feature 1023 and a second alignment feature 1043. An image is generated by sensing the reflection of the IR light 1200 from the alignment mark 1400. Based on this image, a linear alignment term associated with the alignment mark 1400 can be calculated.

[0030] Figure 1E depicts a forbidden region 1300 that directly overlaps with the alignment mark 1400 and extends from the upper surface 104a of the second wafer 104 to the lower surface 102b of the first wafer 102. To avoid scattering of IR light 1200 and to obtain a clear image of the alignment mark 1400, the forbidden region 1300 is substantially devoid of circuit features. That is, the forbidden region 1300 may consist only of the substrates of the first wafer 102 and the second wafer 104, the first RDL 102R and the second RDL 104R, and the alignment mark 1400.

[0031] As shown in Figure 1E, alignment mark 1400 may be adjacent to via location 162, where a via (e.g., TSV) will be formed in subsequent operations. Via location 162 typically overlaps with active circuitry 1029, conductive pads 1027 and 1047, and interconnect structure 1049 of the first wafer 102. First conductive pad 1027 is located in a first RDL 102R, and second conductive pad 1047 is located in a second RDL 104R. Interconnect structure 1049 is located in the second RDL 104R. Additional interconnect structures may extend from active circuitry 1029 to first conductive pad 1027, as shown by dashed lines.

[0032] The alignment mark 1400 is offset from the via position 162 along the first direction D1 by, for example, a distance S6. In some embodiments, the distance S6 between the alignment mark 1400 and the via position 162 is no more than about 50 micrometers (μm) to about 100 μm. A distance S6 exceeding about 100 μm may result in inaccurate determination of nonlinear alignment terms.

[0033] In some embodiments, the thickness of the second wafer 104 during alignment mark 1400 imaging exceeds about 500 μm, about 600 μm, about 700 μm, or other suitable thickness. In some embodiments, the thickness is about 775 μm, which may be substantially equal to the thickness of the bare wafer forming the second wafer 104 before processing.

[0034] In Figure 1F, a single lithography field 114 is depicted, which includes at least four alignment marks 1400. As an example, the lithography field 114 depicted in Figure 4 includes seventeen alignment marks 1400. Other numbers of alignment marks 1400 are contemplated herein as embodiments. Alignment marks 1400 may also be referred to as in-field alignment marks 1400. By including at least four alignment marks 1400 in each lithography field 114, the accuracy of determining nonlinear alignment terms can be improved. In some embodiments, the determination of nonlinear alignment terms includes interpolation between offsets determined by at least three alignment marks 1400 or at least four alignment marks 1400. For example, as shown in Figure 1F, via location 162 may be adjacent to first alignment mark 1400A, second alignment mark 1400B, third alignment mark 1400C, and fourth alignment mark 1400D. In some embodiments, the alignment accuracy of the via location 162 can be determined by interpolation between offsets associated with each of the first alignment mark 1400A, the second alignment mark 1400B, the third alignment mark 1400C, and the fourth alignment mark 1400D. In some embodiments, other algorithms may be performed, in addition to or instead of interpolation, to estimate or predict the alignment accuracy of the via location 162. Based on the calculated alignment accuracy of the via location 162, nonlinear alignment distortion can be fed forward to the lithography process that forms the via opening associated with the via location 162. The nonlinear alignment distortion can be fed forward as part of the alignment accuracy value, which also includes linear offsets (e.g., translation, rotation, expansion).

[0035] In Figure 1G, each alignment mark 1400 may be or include a "box-in-box" shape, including a first ring or box and a second ring or box. The first ring (alignment feature 1023) may be located in a first RDL 102R described with reference to Figure 1E, and the second ring (alignment feature 1043) may be located in a second RDL 104R. Each of the first ring (alignment feature 1023) and the second ring (alignment feature 1043) may have a square, a rectangle, or other suitable shape. In Figure 1G, the first ring (alignment feature 1023) and the second ring (alignment feature 1043) are depicted as having a square shape.

[0036] The first ring (alignment feature 1023) has a first width W1 in the first direction D1 and a first length L1 in the second direction D2. The second ring (alignment feature 1043) has a second width W2 in the first direction D1 and a second length L2 in the second direction D2. In some embodiments, the first width W1 exceeds the second width W2, and the first length L1 exceeds the second length L2. In some embodiments, the first width W1 and the second width W2, and the first length L1 and the second length L2 have dimensions in the range of about 15 μm to about 60 μm. The reduced size of the alignment mark 1400 facilitates positioning the alignment mark 1400 within the lithography field 114, such as in the active circuit region of the IC die region 110 in the lithography field 114.

[0037] The first ring (alignment feature 1023) has a first thickness T1, and the second ring has a second thickness T2. In some embodiments, the first thickness T1 is substantially equal to the second thickness T2. The first ring (alignment feature 1023) and the second ring (alignment feature 1043) are separated by a first distance S241 in the first direction D1 and by a second distance S242 in the second direction D2.

[0038] The misalignment between the first wafer 102 and the second wafer 104 can be determined at least in part based on the relative position and angular offset between the first ring (alignment feature 1023) and the second ring (alignment feature 1043). Translation along the first direction D1 causes an increase or decrease in the first distance S241. Translation along the second direction D2 causes an increase or decrease in the second distance S242. Rotational misalignment causes an angular offset between adjacent sides of the first ring (alignment feature 1023) and the second ring (alignment feature 1043), making these sides non-parallel to each other.

[0039] In Figure 1H, each alignment mark 1400 may be or include a diffraction-based optics (DBO) or a micro-DBO (μDBO) pattern. The DBO pattern may include: a first region 1410 including a vertical stripe 1412 extending along a second direction D2; and a second region 1420 including a horizontal stripe 1422 extending along a first direction D1. Each first region 1410 may be horizontally adjacent to and vertically adjacent to the second region 1420. Each second region 1420 may be horizontally adjacent to and vertically adjacent to the first region 1410. The first DBO pattern may be located in a first RDL 102R, and a second corresponding DBO pattern may be located in a second RDL 104R. Alignment accuracy may be determined based on diffraction caused by the offset between the corresponding vertical stripe 1412 and horizontal stripe 1422 of the directly overlapping first and second DBO patterns. The width and length of the alignment mark 1400 described with reference to Figure 1H may be similar to those described with reference to Figure 1G, such as being in the range of about 15 μm to about 60 μm.

[0040] Figures 1I, 1J and 1K depict the determination of the first nonlinear alignment term and the second nonlinear alignment term, corresponding to actions 212 and 214 in Figure 2.

[0041] In Figure 1I, raw data associated with each alignment mark 1400 is obtained. The raw data may include a first vector 1450 indicating the direction and magnitude of the misalignment associated with each alignment mark 1400. In the description of Figure 1I, for simplicity, only the raw data of a single lithography field 114 is depicted. Typically, the raw data is determined for the alignment marks 1400 distributed across all lithography fields 114.

[0042] In Figure 1J, for example, determining linear alignment terms based on the original data obtained in Figure 1I may correspond to action 210 in Figure 2. Linear alignment terms may include translation, rotation, and expansion / contraction, and are represented as a second vector 1460 in Figure 1I. Determining linear alignment terms may include performing model fitting, least squares analysis, numerical analysis, algebraic calculations, and combinations thereof. In some embodiments, the determination is performed iteratively.

[0043] In Figure 1K, residuals or distortions are determined by subtracting linear alignment terms from the original data. The residuals are depicted as a second vector 1460 in Figure 1J. The residuals may include a first nonlinear alignment term and a second nonlinear alignment term. In some embodiments, the first nonlinear alignment term is associated with a high-order wafer alignment (HOWA) process. In some embodiments, the second nonlinear alignment term is referred to as a correction per exposure (CPE) term.

[0044] HOWA can address misalignments beyond simple linear transformations (e.g., translation, rotation, uniform scaling) by considering higher-order distortions, including nonlinear distortions (e.g., pincushion distortion or barrel distortion) that may occur due to lens aberrations or mechanical stress, field-dependent distortion, etc. HOWA may include measuring alignment marks 1400 across the entire lithography field 114 or even across the entire stack of two wafers 102, 104 to capture higher-order distortion information. In some embodiments, one or more models are generated that can predict and correct distortions, which may involve polynomial fitting or more complex mathematical models to describe nonlinearity. Corrections can then be implemented in subsequent exposure processes, which may include one or more of the following: (i) adjusting the magnification mask or mask (e.g., moving or deforming the mask image in real time to compensate for distortion); (ii) performing stage correction (e.g., adjusting wafer stage movement during exposure); and (iii) performing lens or mirror adjustments. In the exposure process, lithography systems (such as steppers) can dynamically apply corrections based on HOWA data. These corrections may include: changing the path of the wafer stage; modifying the scanning or stepping method of the mask pattern on the wafer; and fine-tuning the focusing or imaging system to address field-related distortions.

[0045] The CPE term may be an alignment term associated with each individual lithography field 114. The CPE term may be or include linear distortion or misalignment of each exposed lithography field 114. That is, linear distortion or misalignment at a local exposed lithography field 114 may be considered a nonlinear alignment term relative to the entire wafer stack of the first wafer 102 and the second wafer 104. The CPE term may be determined based on measurements of the alignment marks 1400 within each exposed lithography field 114. Corrections associated with the CPE term may be applied directly using a linear transformation model.

[0046] Since each lithography field 114 includes at least four alignment marks 1400, the CPE item can be determined with higher accuracy, which is beneficial for correcting overlays in subsequent lithography processes, such as for forming TSV.

[0047] In Figure 1L, a thinned wafer 104' is formed by thinning a second wafer 104, corresponding to action 216 in Figure 2. The second wafer 104 may be thinned by one or more removal operations. In some embodiments, the thickness of the thinned wafer 104' is in the range of about 1 μm to about 50 μm, such as about 1 μm to about 30 μm, about 1 μm to about 15 μm, or another suitable range.

[0048] The second wafer 104 may be thinned from, for example, 775 micrometers to 1 to 15 micrometers, such as when the second wafer 104 is or includes a backside illuminated (BSI) image sensor. Thinning may include a series of operations to maintain the integrity of the second wafer 104 and the devices fabricated on its front side.

[0049] First, the second wafer 104 can be placed on a grinder with a coarse grinding wheel, in which the upper surface 104a is exposed (e.g., by means of a tape or carrier). This operation can reduce the thickness of the second wafer 104 to about 100-200 micrometers. Then, fine grinding can be performed to further thin the wafer using a finer grinding wheel or pad, such as to about 50-100 micrometers. To polish the wafer to remove any subsurface damage, achieve the target thickness with high precision, and provide a very smooth surface, chemical mechanical planarization (CMP) can be performed. CMP may include the use of a polishing pad and an abrasive slurry. The second wafer 104 is pressed against the pad while rotating, and the slurry uniformly removes material. The slurry contains both the chemical components for etching silicon and the mechanical abrasive components for polishing silicon. CMP can further thin the wafer, and can effectively thin it to about 10-50 micrometers, thereby providing a high degree of flatness and uniformity. In some embodiments, a dry etching process, such as plasma etching, may be employed. This may include reactive ion etching (RIE) or deep reactive ion etching (DRIE), which offers the advantage of improved precision. RIE or DRIE processes can use plasma to etch silicon atom by atom, allowing control down to the micrometer or even submicrometer level. Etching can be isotropic (uniform in all directions) or anisotropic (oriented, typically vertical). After significant thinning, the thinned wafer 104' may undergo processes to mitigate the mechanical stress introduced by the thinning process, such as low-temperature annealing or gentle polishing. When the thinned wafer 104' includes a BSI sensor, the exposed side of the thinned wafer 104' may undergo further processing after thinning, such as applying an anti-reflective coating, passivation layer, or back-side metallization to improve sensitivity and performance.

[0050] In Figure 1M, a lithography operation 190 may be performed, which exposes the lithography field 114 of the thinned wafer 104' to prepare the thinned wafer 104' for forming a TSV. In some embodiments, the lithography operation 190 includes the following steps: determining the via location based on the CPE term, corresponding to action 218 in Figure 2.

[0051] Forming a TSV after wafer thinning may include several operations to form a vertical electrical connection via the thinned wafer 104'. A layer of photoresist may be applied to the exposed side of the thinned wafer 104'. The photoresist is then exposed via a mask to define a via pattern in the photoresist layer. Exposure may be performed field-by-field, wherein the via pattern in each lithography field 114 is exposed at least based on a CPE term associated with the corresponding lithography field 114. The exposed photoresist is then developed, leaving openings at the via locations, and the via openings that will form the TSV are etched in subsequent operations. The via openings may be formed by etching an opening in the patterned photoresist layer, which may include RIEs, DRIEs, etc. The etching depth may be controlled to penetrate silicon to reach the interconnect of the second RDL 104R. After etching, the patterned photoresist layer is removed by stripping or another suitable operation. The etched thinned wafer 104' may then be cleaned to remove residues or particles.

[0052] In Figure 1N, corresponding to action 220, a TSV 160 is formed in the via opening at the via location in the thinned wafer 104'. In some embodiments, the step of forming the TSV 160 may include the following steps: depositing a dielectric material (e.g., SiO₂) to line the wall of the via opening. The dielectric material may be deposited by chemical vapor deposition (CVD), plasma-enhanced CVD (PECVD), etc., which is beneficial for improving stage coverage. For example, the dielectric material at the bottom of the via opening may be selectively removed by anisotropic etching to expose the underlying metal layer. Then, an optional barrier layer may be formed by depositing a thin barrier metal (such as titanium nitride (TiN) or tungsten (W)) in the via opening on the dielectric material, which is beneficial for preventing copper from diffusing into the surrounding silicon. In some embodiments, a copper seed layer is then applied, which may be performed via physical vapor deposition (PVD) or another suitable process. The via openings are then filled with copper (e.g., all or part), which may be achieved via an electroplating process. CMP may be performed to remove excess copper and / or barrier metal from the wafer surface of the thinned wafer 104'. In some embodiments, an insulating layer is formed on the wafer surface of the thinned wafer 104' to protect the TSV 160 from oxidation or contamination.

[0053] In Figure 10, an optional RDL 104R2 is formed. In some embodiments, a metal layer 164 is formed to connect the TSVs 160 to each other or to an external bonding pad.

[0054] After forming TSV 160 and an optional insulating layer, a polymer layer, such as polyimide (PI), phenylcyclobutene (BCB), polybenzoxazole (PBO), etc., can be formed by spin coating or lamination. The polymer layer can then be cured to solidify. A photoresist layer is applied to the polymer layer. The photoresist is exposed to, for example, UV light via a mask that defines the RDL pattern. Unexposed or exposed areas of the photoresist layer are removed, thereby defining the pattern in the photoresist layer. The portion of the polymer layer exposed by the patterned photoresist layer is then etched to form an opening for depositing the metal layer 164. The etching method can include dry etching, such as RIE. After etching, the patterned photoresist layer is stripped, and the polymer layer is cleaned. A thin barrier layer (e.g., Ti / TiN, Ta / TaN) can then optionally be deposited to prevent metal diffusion into the polymer layer, which can be performed by PVD or atomic layer deposition (ALD). A thin copper layer can then be applied as a seed layer within the openings of the polymer layer. This can include sputtering or PVD as an initial layer for electroplating. A second photoresist layer can be applied, patterned, and developed to define the metal layer 164. Copper can then be selectively deposited onto the exposed seed layer areas to fill the pattern defined by the second photoresist layer. After electroplating, the second photoresist layer is stripped. Excess seed layer outside the electroplated areas can be etched away, typically via a selective copper etching process that does not significantly erode the electroplated copper. CMP can be performed to planarize the copper layer, thereby removing excess copper and obtaining a flat surface for subsequent layers or bonding. The process described above can be repeated to form additional metal layers for the RDL structure.

[0055] According to some embodiments, Figure 3 illustrates method 300.

[0056] At step 302, method 300 includes the following steps: forming a first wafer.

[0057] At step 304, method 300 includes the following steps: forming a first interconnect structure on a first wafer, the first interconnect structure including at least four first alignment features located in a first top metal layer of the first interconnect structure.

[0058] At step 306, method 300 includes the following steps: forming a second wafer.

[0059] At step 308, method 300 includes the following steps: forming a second interconnect structure on a second wafer, the second interconnect structure including at least four second alignment features located in a second top metal layer of the second interconnect structure.

[0060] At step 310, method 300 includes the following steps: bonding a first wafer to a second wafer by forming a hybrid bond between a first interconnect structure and a second interconnect structure, wherein each first alignment feature overlaps with a corresponding second alignment feature.

[0061] At step 312, method 300 includes the following steps: determining nonlinear alignment distortion of the first and second wafers based on the overlap of the first and second alignment features. In some embodiments, method 300 includes the following steps: after determining nonlinear alignment distortion, thinning the second wafer, and the step of determining nonlinear alignment distortion includes the following steps: imaging the first and second alignment features with light having a wavelength greater than about 750 nanometers. In some embodiments, method 300 includes the following steps: before determining nonlinear alignment distortion, thinning the second wafer, and the step of determining nonlinear alignment distortion includes the following steps: imaging the first and second alignment features with light having a wavelength range between about 500 nanometers and about 750 nanometers. In some embodiments, method 300 includes the following steps: before determining nonlinear alignment distortion, determining linear alignment distortion of the first and second wafers. In some embodiments, the step of determining nonlinear alignment distortion includes the following steps: performing high-order wafer alignment (HOWA) analysis.

[0062] At step 314, method 300 includes the following steps: determining the location of at least one through hole based on nonlinear alignment distortion.

[0063] At step 316, method 300 includes the step of forming a through hole at at least one through hole location.

[0064] According to some embodiments, Figure 4 illustrates method 400.

[0065] At step 402, method 400 includes the following steps: providing a first wafer having a first interconnect structure.

[0066] At step 404, method 400 includes the following steps: providing a second wafer having a second interconnect structure.

[0067] At step 406, method 400 includes the following steps: forming a bonding structure by bonding a first wafer to a second wafer, the forming step including the following steps: forming a hybrid bond between a first interconnect structure and a second interconnect structure, the bonding structure including at least four alignment marks, each alignment mark being located in the first interconnect structure and the second interconnect structure. In some embodiments, the step of bonding the first wafer to the second wafer includes the following steps: forming alignment marks, the alignment marks being box-in-box alignment marks, each box-in-box alignment mark including: a first alignment feature located in the first interconnect structure; and a second alignment feature located in the second interconnect structure. In some embodiments, the step of forming alignment marks includes the following steps: forming box-in-box alignment marks, each box-in-box alignment mark having a width and length not exceeding about 40 micrometers. In some embodiments, the step of bonding the first wafer to the second wafer includes the following steps: forming at least four alignment marks, each alignment mark being associated with the same integrated circuit die defined in the second wafer.

[0068] At step 408, method 400 includes the following steps: determining nonlinear alignment distortion of the first and second wafers based on alignment marks.

[0069] At step 410, method 400 includes the following steps: feeding nonlinear alignment distortion forward to the lithography process.

[0070] At step 412, method 400 includes the following steps: forming at least one via in a second wafer by means of a photolithography process.

[0071] In some embodiments, method 400 includes the step of forming a third interconnect structure on at least one via. In some embodiments, method 400 includes the step of bonding a third wafer to a second wafer via the third interconnect structure.

[0072] One or more embodiments relate to computer-readable media containing processor-executable instructions for implementing one or more of the techniques described herein. Figure 5 illustrates an exemplary computer-readable medium, wherein embodiment 500 includes computer-readable data 508 (e.g., a CD-R, DVD-R, flash drive, hard disk drive disc, etc.) encoded with computer-readable data 506. The computer-readable data 506 further includes a set of processor-executable computer instructions 504 for implementing one or more of the principles described herein when executed by a processor. In some embodiments 500, the processor-executable computer instructions 504 are used to implement method 502, such as at least some of the methods described above, when executed by a processor. In some embodiments, the processor-executable computer instructions 504 are used to implement a system, such as at least some of the systems described above, when executed by a processor. Many such computer-readable media can be designed by those skilled in the art to operate according to the techniques described herein.

[0073] In some embodiments, an integrated circuit device is provided. The integrated circuit device includes: a first substrate; a first interconnect structure located on the first substrate; a second substrate; a second interconnect structure located on the second substrate, the first substrate being bonded to the second substrate by a hybrid bond between the first interconnect structure and the second interconnect structure; an active circuit region located in the second substrate, the active circuit region including a via extending through the second substrate; and at least four alignment patterns offset from the via. Each alignment pattern includes: a first conductive feature located in a first top metal layer of the first interconnect structure; and a second conductive feature located in a second top metal layer of the second interconnect structure, the size of the second conductive feature not exceeding the size of the first conductive feature.

[0074] In some embodiments, at least two alignment marks are located in the active circuit region. In some embodiments, a plurality of second regions of a second substrate directly covered with at least four alignment marks substantially do not scatter light in the infrared spectrum. In some embodiments, a plurality of first regions of a first substrate directly covered with at least four alignment marks substantially do not scatter light in the infrared spectrum. In some embodiments, at least one of these alignment marks is offset from the via by 100 micrometers. In some embodiments, the dimensions of the first conductive feature include: a first dimension ranging from about 15 micrometers to about 60 micrometers; and a second dimension ranging from about 15 micrometers to about 60 micrometers. In some embodiments, the ratio of a first thickness of the first substrate to a second thickness of the second substrate ranges from about 1.5 to about 300.

[0075] In some embodiments, a method for forming an integrated circuit is provided. The method includes the following steps: forming a first wafer; forming a first interconnect structure on the first wafer, the first interconnect structure including at least four first alignment features located in a first top metal layer of the first interconnect structure; forming a second wafer; forming a second interconnect structure on the second wafer, the second interconnect structure including at least four second alignment features located in a second top metal layer of the second interconnect structure; bonding the first wafer to the second wafer by forming a hybrid bond between the first interconnect structure and the second interconnect structure, each first alignment feature overlapping with a corresponding second alignment feature; determining nonlinear alignment distortion of the first and second wafers based on the overlap of the first and second alignment features; determining at least one via location based on the nonlinear alignment distortion; and forming a via at the at least one via location.

[0076] In some embodiments, the method further includes: thinning a second wafer after determining nonlinear alignment distortion. In some embodiments, the step of determining nonlinear alignment distortion includes: imaging the first and second alignment features with light having a wavelength greater than about 750 nanometers. In some embodiments, the method further includes: thinning the second wafer before determining nonlinear alignment distortion. In some embodiments, the step of determining nonlinear alignment distortion includes: imaging the first and second alignment features with light having a wavelength range of about 500 nanometers to about 750 nanometers. In some embodiments, the method further includes: determining linear alignment distortion of the first and second wafers before determining nonlinear alignment distortion. In some embodiments, the step of determining nonlinear alignment distortion includes: performing high-order wafer alignment analysis.

[0077] In some embodiments, a method for forming an integrated circuit is provided. The method includes the following steps: providing a first wafer having a first interconnect structure; providing a second wafer having a second interconnect structure; forming a bonding structure by bonding the first wafer and the second wafer, the forming step including the following steps: forming a hybrid bond between the first interconnect structure and the second interconnect structure, the bonding structure including at least four alignment marks, each alignment mark being located in the first interconnect structure and the second interconnect structure; determining nonlinear alignment distortion of the first and second wafers based on the alignment marks; feeding the nonlinear alignment distortion forward to a lithography process; and forming at least one via in the second wafer by the lithography process.

[0078] In some embodiments, the method further includes: forming a third interconnect structure on at least one via. In some embodiments, the method further includes: bonding a third wafer to a second wafer via the third interconnect structure. In some embodiments, the step of bonding a first wafer to a second wafer includes: forming a plurality of box-in-box alignment marks, each box-in-box alignment mark including: a first alignment feature located in the first interconnect structure; and a second alignment feature located in the second interconnect structure. In some embodiments, the step of forming these alignment marks includes: forming these box-in-box alignment marks, each box-in-box alignment mark having a width and length not exceeding about 40 micrometers. In some embodiments, the step of bonding a first wafer to a second wafer includes: forming at least four alignment marks, each alignment mark being associated with the same integrated circuit die defined in the second wafer.

[0079] Although the subject matter has been described using language specific to structural features or methodological actions, it should be understood that the subject matter of the patent application is not necessarily limited to the specific features or actions described above. Rather, the specific features and actions described above are disclosed as examples of implementing at least some of the claims.

[0080] This document provides various operations of embodiments. The order in which some or all of the operations are described should not be construed as implying that these operations necessarily depend on the order. Alternative orders can be understood with the aid of this description. Furthermore, it should be understood that not all operations are necessarily present in every embodiment provided herein. Furthermore, it should be understood that not all operations are necessary in some embodiments.

[0081] It should be understood that in some embodiments, the layers, features, elements, etc. shown herein are described with respect to specific dimensions (such as structural dimensions or orientations) relative to each other. For example, for the purposes of simplicity and ease of understanding, the actual dimensions are quite different from those shown herein. Furthermore, there are various techniques available for forming the layers, regions, features, elements, etc. mentioned herein, such as at least one of etching techniques, planarization techniques, implantation techniques, doping techniques, spin coating techniques, sputtering techniques, growth techniques, or deposition techniques (such as chemical vapor deposition (CVD)).

[0082] Furthermore, the terms "illustrative" and / or similar terms are used herein to mean as an example, example, illustration, etc., and are not necessarily advantageous. As used in this application, "or" is intended to mean an inclusive "or" rather than an exclusive "or". Furthermore, unless otherwise stated or the context clearly indicates a singular form, "a" and "an" as used in this application and the claims are generally to be interpreted as "one or more". Furthermore, at least one of A and B and / or the like generally means A or B or both A and B. Furthermore, within the scope of the use of "comprising", "having", "having", "with", or variations thereof, these terms are intended to include in a manner similar to the term "comprising". Furthermore, unless otherwise stated, "first", "second", or the like are not intended to imply a temporal state, spatial state, order, etc. Rather, these terms are used only as identifiers, names, etc., of features, elements, items, etc. For example, a first element and a second element generally correspond to element A and element B or two different or two identical elements or the same element.

[0083] Furthermore, although this disclosure has shown and described with respect to one or more embodiments, equivalent changes and modifications will occur to those skilled in the art upon reading and understanding this specification and the accompanying drawings. This disclosure includes all such modifications and changes and is limited only by the scope of the following claims. In particular, with respect to the various functions performed by the aforementioned components (e.g., elements, resources, etc.), the terminology used to describe such components is intended to correspond to any component performing the specified function of said component (e.g., a functionally equivalent component), even if structurally not equivalent to the disclosed structure. Furthermore, although a particular feature of this disclosure may be disclosed only with respect to one of several embodiments, such feature may be combined with one or more other features of other embodiments that may be desirable and advantageous for any given or particular application. [Simplified Explanation of the Diagram]

[0084] The various aspects of this disclosure can be best understood in conjunction with the accompanying drawings and the following detailed description. Note that, according to standard industry practice, the various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or decreased for clarity of discussion. Figures 1A, 1B, 1C, 1D, 1E, 1F, 1G, 1H, 1I, 1J, 1K, 1L, 1M, 1N, and 1O illustrate intermediate schematic diagrams of a method for forming an integrated circuit device according to some embodiments. Figure 2 is a flowchart illustrating a method for forming an integrated circuit device according to some embodiments. Figure 3 is a flowchart illustrating a method for forming an integrated circuit device according to some embodiments. Figure 4 is a flowchart illustrating a method for forming an integrated circuit device according to some embodiments. Figure 5 illustrates an exemplary computer-readable medium according to some embodiments, which may contain processor-executable instructions embodying one or more of the specifications described herein. [Biomaterial Storage]

[0086] Domestic storage information (please note in order of storage institution, date, and number): None. International storage information (please note in order of storage country, institution, date, and number): None.

Claims

1. An integrated circuit device, comprising: a first substrate; a first interconnect structure disposed on the first substrate; a second substrate; a second interconnect structure disposed on the second substrate, the first substrate being bonded to the second substrate via a hybrid bond between the first interconnect structure and the second interconnect structure; and an active circuit region disposed in the second substrate, the active circuit region including a through-hole extending through the second substrate; And an alignment pattern, including at least four alignment marks offset from the through-hole, each alignment mark including: A first conductive feature is located in a first top metal layer of the first interconnect structure; And a second conductive feature, located in a second top metal layer of the second interconnect structure, wherein the size of the second conductive feature does not exceed the size of the first conductive feature.

2. The integrated circuit device as claimed in claim 1, wherein a plurality of second regions of the second substrate directly overlying the at least four alignment marks substantially do not scatter light in an infrared spectrum.

3. The integrated circuit device as claimed in claim 1, wherein at least one of the alignment marks is offset from the via by a distance of 100 micrometers.

4. The integrated circuit device as claimed in claim 1, wherein the dimension of the first conductive feature includes: A first dimension, ranging from about 15 micrometers to about 60 micrometers; And a second size, ranging from about 15 micrometers to about 60 micrometers.

5. A method of forming an integrated circuit, comprising: forming a first wafer; forming a first interconnect structure on the first wafer, the first interconnect structure including at least four first alignment features located in a first top metal layer of the first interconnect structure; forming a second wafer; forming a second interconnect structure on the second wafer, the second interconnect structure including at least four second alignment features located in a second top metal layer of the second interconnect structure; bonding the first wafer to the second wafer by forming a hybrid bond between the first interconnect structure and the second interconnect structure, each first alignment feature overlapping a corresponding second alignment feature; determining a nonlinear alignment distortion of the first wafer and the second wafer based on the overlap of the first alignment features and the second alignment features; determining at least one via location based on the nonlinear alignment distortion; and forming a via at the at least one via location.

6. The method of forming an integrated circuit as described in claim 5 further comprises: after determining the nonlinear alignment distortion, thinning the second wafer.

7. The method for forming an integrated circuit as described in claim 6, wherein the step of determining the nonlinear alignment distortion includes: The first alignment feature and the second alignment feature are imaged using light with a wavelength exceeding approximately 750 nanometers.

8. The method of forming an integrated circuit as claimed in claim 5, further comprising: thinning the second wafer before determining the nonlinear alignment distortion.

9. The method for forming an integrated circuit as described in claim 8, wherein the step of determining the nonlinear alignment distortion includes: The first alignment feature and the second alignment feature are imaged using light with a wavelength range of about 500 nanometers to about 750 nanometers.

10. A method of forming an integrated circuit, comprising: providing a first wafer having a first interconnect structure; providing a second wafer having a second interconnect structure; and forming a bonding structure by bonding the first wafer to the second wafer, comprising: A hybrid bond is formed between the first interconnect structure and the second interconnect structure, the bond structure including at least four alignment marks, each alignment mark being located in the first interconnect structure and the second interconnect structure; based on the alignment marks, nonlinear alignment distortion of the first wafer and the second wafer is determined; the nonlinear alignment distortion is fed forward to a photolithography process; and at least one via is formed in the second wafer by the photolithography process.

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