Frequency mode temperature sensor

Abstract

A frequency mode temperature sensor includes a PTAT (Proportional To Absolute Temperature) current generation circuit, a CTAT (Complementary To Absolute Temperature) current generation circuit, a dual current subtraction circuit, a charge-discharge circuit, and a voltage window comparator circuit. The dual current subtraction circuit receives the PTAT voltage output from the PTAT current generation circuit and the CTAT voltage output from the CTAT current generation circuit, subtracting the CTAT current from the PTAT current to obtain a PTAT subtraction current with enhanced sensitivity. The PTAT subtraction current is then processed by the charge-discharge circuit and the voltage window comparator circuit to output a temperature sensing signal whose frequency is proportional to the absolute temperature.

Description

Technical Field

[0001] This invention relates to a temperature sensor, and more particularly to a frequency-based temperature sensor. Prior Technology

[0002] Frequency-based temperature sensors are characterized by their simple structure, requiring only a PTAT current generator and a current-to-frequency conversion circuit to output a signal whose frequency is proportional to the absolute temperature. However, such frequency-based temperature sensors have a low sensitivity due to their limited current variation of only tens of nA per degree Celsius. Furthermore, because the current variation is small, process variations have a significant impact on the output frequency of frequency-based temperature sensors. Therefore, reducing the impact of process variations and improving sensitivity have become the key development focus for frequency-based temperature sensors. Summary of the Invention

[0003] The main objective of this invention is to obtain a more sensitive PTAT subtraction current by subtracting the CTAT current twice from the PTAT current using a double subtraction circuit.

[0004] A frequency-based temperature sensor of the present invention includes a PTAT current generation circuit, a CTAT current generation circuit, a double current subtraction circuit, a charge / discharge circuit, and a voltage window comparison circuit. The PTAT current generation circuit generates a PTAT voltage, and the CTAT current generation circuit generates a CTAT voltage. The double current subtraction circuit includes a first current subtraction unit, a second current subtraction unit, and a bias voltage generation unit. The first current subtraction unit is electrically connected to the PTAT current generation circuit and the CTAT current generation circuit to receive the PTAT voltage and the CTAT voltage. The first current subtraction unit generates a PTAT current from the PTAT voltage and a first CTAT current from the CTAT voltage. The first current subtraction unit subtracts the first CTAT current from the PTAT current to obtain a first PTAT subtracted current. The second current subtraction unit is electrically connected to the CTAT current generation circuit and the second current subtraction circuit. A current subtraction unit receives the CTAT voltage and the first PTAT subtraction current. A second current subtraction unit generates a second CTAT current using the CTAT voltage. The second current subtraction unit subtracts the second CTAT current from the first PTAT subtraction current to obtain a second PTAT subtraction current. The second PTAT subtraction current generates a bias voltage in the bias generation unit. The charging and discharging circuit has a charging and discharging current generation unit and a charging and discharging capacitor. The charging and discharging current generation unit is electrically connected to the bias generation unit to receive the bias voltage. The charging and discharging capacitor is electrically connected to the charging and discharging current generation unit. The charging and discharging current generation unit selectively provides a charging current or a discharging current to the charging and discharging capacitor. The charging and discharging capacitor outputs a charging voltage. A voltage window comparator circuit is electrically connected to the charging and discharging circuit to receive the charging voltage. The voltage window comparator circuit compares the charging voltage with a high reference voltage and a low reference voltage to output a temperature sensing signal.

[0005] This invention uses the double current subtraction circuit to subtract the CTAT current twice, thereby obtaining a PTAT subtraction current with higher sensitivity to absolute temperature. The temperature sensing signal is then output through the charging and discharging circuit and the voltage window comparison circuit, thereby obtaining a frequency-type temperature sensor with a higher dynamic range and improving the output accuracy of the back-end circuit. Simple Explanation of the Diagram

[0006] Figure 1: Block diagram of a frequency-type temperature sensor according to one embodiment of the present invention. Figure 2: A circuit diagram of a startup circuit, a PTAT current generating circuit and a CTAT current generating circuit according to one embodiment of the present invention. Figure 3: A circuit diagram of a current subtraction circuit according to one embodiment of the present invention. Figure 4: Circuit diagram of a first process drift compensation transistor group according to one embodiment of the present invention. Figure 5: Circuit diagram of a second process drift compensation transistor group according to one embodiment of the present invention. Figure 6: A circuit diagram of a charge / discharge capacitor and a voltage window comparison circuit according to one embodiment of the present invention. Implementation

[0007] Please refer to Figure 1, which is a circuit diagram of a frequency-based temperature sensor 100 according to one embodiment of the present invention. The frequency-based temperature sensor 100 includes a PTAT current generating circuit 110, a CTAT current generating circuit 120, a two-current subtraction circuit 130, a charge / discharge circuit 140, and a voltage window comparator circuit 150. The PTAT current generating circuit 110 generates a PTAT voltage VPTAT, and the CTAT current generating circuit 120 generates a CTAT voltage VCTAT. The two-current subtraction circuit 130 is electrically connected to the PTAT current generating circuit 110 and the CTAT current generating circuit 120 to receive the PTAT voltage VPTAT and the CTAT voltage VCTAT, and outputs a bias voltage. The charge / discharge circuit 140 is electrically connected to the two-current subtraction circuit 130 to receive the bias voltage, and outputs a charging voltage VC. The voltage window comparator circuit 150 is electrically connected to the charge / discharge circuit 140 to receive the charging voltage VC, and the voltage window comparator circuit 150 outputs a temperature sensing signal Stem.

[0008] Please refer to Figures 1 and 2. The PTAT current generating circuit 110 includes a PTAT current mirror 111, a first operational amplifier 112, a first variable resistor 113, and a bipolar transistor pair 114. The first operational amplifier 112 is electrically connected to the PTAT current mirror 111 and outputs the PTAT voltage VPTAT. The first variable resistor 113 is electrically connected to the PTAT current mirror 111 and the first operational amplifier 112. The bipolar transistor pair 114 is electrically connected to the PTAT current mirror 111 and the first variable resistor 113. When different current densities are applied to the two bipolar transistors of the bipolar transistor pair 114, the voltage difference between the emitters of the two bipolar transistors is proportional to the absolute temperature. This voltage difference is then transferred to the first variable resistor 113 via the first operational amplifier 112 and the first variable resistor 113, generating a PTAT current IPTAT and a PTAT voltage VPTAT that are proportional to the absolute temperature. The first variable resistor 113 receives and is controlled by a process drift compensation control signal to provide different resistance values ​​at different process corners. This improves the linearity of the ratio between the PTAT current IPTAT and the absolute temperature at different process corners. In this embodiment, the process drift compensation control signal includes a first control signal s1 and a second control signal s2, which are used to change the resistance value of the first variable resistor 113. Furthermore, when the PTAT current generation circuit 110 is not yet activated, this embodiment uses a startup circuit S to provide a startup current to the bipolar transistor pair 114 to activate the PTAT current generation circuit 110 and enable it to operate normally.

[0009] Please refer to Figure 2. The CTAT current generating circuit 120 has a second operational amplifier 121, a current transistor 122, a current mirror transistor 123, and a second variable resistor 124. The positive terminal of the second operational amplifier 121 is electrically connected to the first variable resistor 113 and the bipolar transistor pair 114. The negative terminal of the second operational amplifier 121 is electrically connected to the second variable resistor 124. The current transistor 122 is electrically connected to the output terminal of the second operational amplifier 121. The current mirror transistor 123 is electrically connected to the current transistor 122, and the current mirror transistor 123 outputs the CTAT voltage VCTAT. The second variable resistor 124 is electrically connected to the current transistor 122. The second operational amplifier 121 receives the base-emitter voltage of the bipolar transistor from the bipolar transistor pair 114. Since the base-emitter voltage of the bipolar transistor is inversely proportional to the absolute temperature, a CTAT current ICTAT is generated in the current transistor 122, and the CTAT voltage VCTAT is generated in the current mirror transistor 123. The second variable resistor 124 is controlled by the first and second control signals s1 and s2 of the process drift compensation control signal to provide different resistance values ​​at different process corners, thereby improving the linearity of the ratio of the CTAT current ICTAT to the absolute temperature at different process corners.

[0010] Please refer to Figures 1 and 3. The two current subtraction circuit 130 has a first current subtraction unit 131, a second current subtraction unit 132, and a bias voltage generating unit 133. The first current subtraction unit 131 is electrically connected to the PTAT current generating circuit 110 and the CTAT current generating circuit 120 to receive the PTAT voltage VPTAT and the CTAT voltage VCTAT. The first current subtraction unit 131 generates the PTAT current IPTAT by the PTAT voltage VPTAT and generates a first CTAT current ICTAT1 by the CTAT voltage VCTAT. The first current subtraction unit 131 subtracts the first CTAT current ICTAT1 from the PTAT current IPTAT to obtain a first PTAT subtraction current I01. Please refer to Figure 3. In this embodiment, the first current subtraction unit 131 has a first current mirror crystal Mf1, a second current mirror crystal Mf2, a third current mirror crystal Mf3, and a fourth current mirror crystal Mf4. The first current mirror crystal Mf1 is electrically connected to the current mirror crystal 123 of the CTAT current generation circuit 120 to receive the CTAT voltage VCTAT and generate the first CTAT current ICTAT1. The first current mirror crystal Mf1 and the current mirror crystal 123 form a current mirror, and the CTAT current ICTAT is mirrored onto the first current mirror crystal Mf1 to become the first CTAT current ICTAT1. The second current mirror transistor Mf2 is electrically connected to the PTAT current mirror 111 of the PTAT current generating circuit 110 to receive the PTAT voltage VPTAT and generate the PTAT current IPTAT. The second current mirror transistor Mf2 and the PTAT current mirror 111 form a current mirror, and the PTAT current IPTAT is reflected to the second current mirror transistor Mf2.

[0011] The third current mirror transistor Mf3 is electrically connected to the first current mirror transistor Mf1 to receive the first CTAT current I CTAT1. The fourth current mirror transistor Mf4 is electrically connected to the third current mirror transistor Mf3 and the second current mirror transistor Mf2 to receive the PTAT current I PTAT. The third current mirror transistor Mf3 and the fourth current mirror transistor Mf4 constitute a current mirror. The first CTAT current I CTAT1 is mirrored from the third current mirror transistor Mf3 to the fourth current mirror transistor Mf4, allowing the second current mirror transistor Mf2 to output the first PTAT subtraction current I O1. The first PTAT subtraction current I O1 is the PTAT current I PTAT minus the first CTAT current I CTAT1, thereby obtaining a first PTAT subtraction current I O1 that is more sensitive to absolute temperature.

[0012] Please refer to Figure 3. The second current subtraction unit 132 is electrically connected to the CTAT current generating circuit 120 and the first current subtraction unit 131 to receive the CTAT voltage VCTAT and the first PTAT subtraction current IO1. The second current subtraction unit 132 generates a second CTAT current ICTAT2 by the CTAT voltage VCTAT. The second current subtraction unit 132 subtracts the second CTAT current ICTAT2 from the first PTAT subtraction current IO1 to obtain a second PTAT subtraction current IO2. The second PTAT subtraction current IO2 generates a bias voltage in the bias generation unit 133. In this embodiment, the second current subtraction unit 132 includes a first stacked current mirror 132a, a second stacked current mirror 132b, a first current mirror 132c, and a third stacked current mirror 132d. The first stacked current mirror 132a is electrically connected to the first current subtraction unit 131 and the second stacked current mirror 132b. The first stacked current mirror 132a receives the first PTAT subtraction current IO1 and mirrors the first PTAT subtraction current IO1 to the second stacked current mirror 132b. The first current mirror 132c receives the CTAT voltage VCTAT and generates the second CTAT current ICTAT2. The third stacked current mirror 132d is electrically connected to the first current mirror 132c and the second stacked current mirror 132b to receive the second CTAT current I CTAT2. The third stacked current mirror 132d is used to mirror the second CTAT current I CTAT2, and the second stacked current mirror 132b outputs the second PTAT subtraction current IO2. The second PTAT subtraction current IO2 is the first PTAT subtraction current IO1 minus the second CTAT current I CTAT2, thereby obtaining the second PTAT subtraction current IO2 with higher sensitivity.

[0013] The first stacked current mirror 132a includes a first stacked transistor Ms1, a second stacked transistor Ms2, a third stacked transistor Ms3, and a fourth stacked transistor Ms4. The first stacked transistor Ms1 is electrically connected to the first current subtraction unit 131 to receive the first PTAT subtraction current IO1. The second stacked transistor Ms2 is electrically connected to the first stacked transistor Ms1, the third stacked transistor Ms3 is electrically connected to the first stacked transistor Ms1, and the fourth stacked transistor Ms4 is electrically connected to the second and third stacked transistors Ms2 and Ms3. The first and third stacked transistors Ms1 and Ms3 are used to mirror the first PTAT subtraction current IO1 to the second and fourth stacked transistors Ms2 and Ms4. In this embodiment, the current mirroring through the stacked current mirror can make the current magnitude more stable, thereby improving the linearity of the frequency temperature sensor 100.

[0014] The second stacked current mirror 132b has a fifth stacked transistor Ms5, a sixth stacked transistor Ms6, a seventh stacked transistor Ms7, an eighth stacked transistor Ms8, and a first process drift compensation transistor group 132f. The fifth stacked transistor Ms5 is electrically connected to the second stacked transistor Ms2 of the first stacked current mirror 132a to receive the first PTAT subtraction current IO1. The sixth stacked transistor Ms6 is electrically connected to the fifth stacked transistor Ms5. The seventh stacked transistor Ms7 is electrically connected to the fifth stacked transistor Ms5. The eighth stacked transistor Ms8 is electrically connected to the sixth and seventh stacked transistors Ms6 and Ms7. The first process drift compensation transistor group 132f is electrically connected to the sixth, seventh, and eighth stacked transistors Ms6, Ms7, and Ms8. The fifth and seventh stacked transistors Ms5 and Ms7 are used to mirror the first PTAT phase subtraction current IO1 to the sixth and eighth stacked transistors Ms6 and Ms8. The first process drift compensation transistor group 132f is controlled by the first control signal s1 and the second control signal s2 of the process drift compensation control signal to perform current compensation on the second stacked current mirror 132b. In this embodiment, the current mirroring through the stacked current mirror can make the current magnitude more stable, thereby improving the linearity of the frequency temperature sensor 100.

[0015] Please refer to Figures 3 and 4, where nodes N1 and N2 in Figure 3 correspond to nodes N1 and N2 in Figure 4. In this embodiment, the first process drift compensation transistor group 132f has a first compensation transistor M cf1, a first switching transistor group sw1, a second compensation transistor M cf2, a second switching transistor group sw2, a third compensation transistor M cf3, and a third switching transistor group sw3. The first compensation transistor Mcf1 is electrically connected to the seventh and eighth stacked transistors Ms7 and Ms8. The first switching transistor group sw1 is electrically connected to the first compensation transistor Mcf1 and the sixth stacked transistor Ms6. The first switching transistor group sw1 has a first switching transistor Msw1 and a second switching transistor Msw2. The first switching transistor Msw1 is electrically connected to the first compensation transistor Mcf1. The second switching transistor Msw2 is electrically connected to the first switching transistor Msw1, the eighth stacked transistor Ms8, and the sixth stacked transistor Ms6. The first switching transistor Msw1 is subjected to the inverted second control signal. The second switching transistor Msw2 is controlled by the inverted first control signal. control.

[0016] The second compensation transistor Mcf2 is electrically connected to the seventh and eighth stacked transistors Ms7 and Ms8. The second switching transistor group sw2 is electrically connected to the second compensation transistor Mcf2 and the sixth stacked transistor Ms6. The second switching transistor group sw2 has a third switching transistor Msw3 and a fourth switching transistor Msw4. The third switching transistor Msw3 is electrically connected to the second compensation transistor Mcf2. The fourth switching transistor Msw4 is electrically connected to the third switching transistor Msw3, the eighth stacked transistor Ms8, and the sixth stacked transistor Ms6. The third switching transistor Msw3 is subjected to the inverted second control signal. The fourth switching transistor M sw4 is controlled by the first control signal s1.

[0017] The third compensation transistor Mcf3 is electrically connected to the seventh and eighth stacked transistors Ms7 and Ms8. The third switching transistor group sw3 is electrically connected to the third compensation transistor Mcf3 and the sixth stacked transistor Ms6. The third switching transistor group sw3 has a fifth switching transistor Msw5 and a sixth switching transistor Msw6. The fifth switching transistor Msw5 is electrically connected to the third compensation transistor Mcf3. The sixth switching transistor Msw6 is electrically connected to the fifth switching transistor Msw5, the eighth stacked transistor Ms8, and the sixth stacked transistor Ms6. The fifth switching transistor Msw5 is controlled by the second control signal s2, and the sixth stacked transistor Ms6 is controlled by the inverted first control signal. control.

[0018] In this embodiment, when the process corner is SS (Slow, Slow), both the first and second control signals s1 and s2 are high. When the process corner is TT (Typical, Typical) or FS (Fast, Slow), the first control signal s1 is high and the second control signal s2 is low. When the process corner is SF (Slow, Fast), the first control signal s1 is low and the second control signal s2 is high. When the process corner is FF (Fast, Fast), both the first and second control signals s1 and s2 are low. This allows the first compensation transistor Mcf1, the first switching transistor group sw1, the second compensation transistor Mcf2, the second switching transistor group sw2, and the third compensation transistor Mcf1 to communicate with the process corner. cf3 and the third switching transistor group sw3 provide different compensation currents at different process corners, so that the current mirrored by the second stacked current mirror 132b can maintain linearity at different process corners.

[0019] Please refer to Figure 3. The third stacked current mirror 132d has a ninth stacked transistor Ms9, a tenth stacked transistor Ms10, an eleventh stacked transistor Ms11, a twelfth stacked transistor Ms12, and a second process drift compensation transistor group 132g. The ninth stacked transistor Ms9 is electrically connected to the first current mirror 132c to receive the second CTAT current ICTAT2. The tenth stacked transistor Ms10 is electrically connected to the ninth stacked transistor Ms9. The eleventh stacked transistor Ms11 is electrically connected to the ninth stacked transistor Ms9. The twelfth stacked transistor Ms12 is electrically connected to the tenth and eleventh stacked transistors Ms10 and Ms11. The second process drift compensation transistor group 132g is electrically connected to the tenth, eleventh, and twelfth stacked transistors Ms10, Ms11, and Ms12. The ninth and eleventh stacked transistors Ms9 and Ms11 are used to mirror the second CTAT current ICTAT2 to the tenth and twelfth stacked transistors Ms10 and Ms12, thereby subtracting the second CTAT current ICTAT2 from the first PTAT subtraction current I01 to obtain the second PTAT subtraction current I. O2, since the second PTAT phase subtraction current IO2 is the PTAT current IPTAT minus the first CTAT current ICTAT1 and the second CTAT current ICTAT2, the second PTAT phase subtraction current IO2 that is more sensitive to absolute temperature can be obtained.

[0020] Please refer to Figures 3 and 5. Nodes N3 and N4 in Figure 3 correspond to nodes N3 and N4 in Figure 5. The second process drift compensation transistor group 132g is controlled by the first control signal s1 and the second control signal s2 of the process drift compensation control signal to perform current compensation. In this embodiment, the second process drift compensation transistor group 132g has a fourth switching transistor group sw4 and a fourth compensation transistor Mcf4. The fourth switching transistor group sw4 is electrically connected to the tenth and twelfth stacked transistors Ms10 and Ms12, and the fourth switching transistor group sw4 is controlled by the process drift compensation control signals s1 and s2. The fourth compensation transistor Mcf4 is electrically connected to the fourth switching transistor group sw4 and the eleventh and twelfth stacked transistors Ms11 and Ms12. The fourth transistor group sw4 has a seventh transistor M sw7 and an eighth transistor M sw8. The seventh transistor M sw7 is electrically connected to the tenth and twelfth stacked transistors Ms10 and Ms12. The eighth transistor M sw8 is electrically connected to the seventh transistor M sw7 and the fourth compensation transistor M cf4. The fourth compensation transistor M cf4 is electrically connected to the eleventh and twelfth stacked transistors Ms11 and Ms12. The first control signal s1 of the process drift compensation control signal controls the seventh transistor M sw7, and the second control signal s2 of the process drift compensation control signal controls the eighth transistor M sw8. Similarly, the first control signal s1 and the second control signal s2 can control the magnitude of the compensation current provided by the second process drift compensation transistor group 132g to the third stacked current mirror 132d, so as to maintain linearity at different process corners.

[0021] Referring to Figure 3, the bias generation unit 133 has a first switching transistor Mc1 and a second switching transistor Mc2. The first switching transistor Mc1 is electrically connected to the sixth stacked transistor Ms6 to receive the second PTAT phase subtraction current IO2. The second switching transistor Mc2 is electrically connected to the first switching transistor Mc1. The second PTAT phase subtraction current IO2 flows through the first switching transistor Mc1 and the second switching transistor Mc2 to generate a first bias voltage Vb1 and a second bias voltage Vb2.

[0022] Referring to Figure 6, the charging / discharging circuit 140 includes a charging / discharging current generating unit 141 and a charging / discharging capacitor 142. The charging / discharging current generating unit 141 is electrically connected to the bias generating unit 133 to receive the bias voltage and selectively provide a charging current or a discharging current. The charging / discharging capacitor 142 is electrically connected to the charging / discharging current generating unit 141 and is charged by the charging current or discharged by the discharging current. In this embodiment, the charging / discharging current generating unit 141 includes a charging transistor pair 141a, a discharging transistor pair 141b, and an inverting transistor pair 141c. The charging transistor pair 141a is electrically connected to the second stacked current mirror 132b to receive a third bias voltage Vb3 generated by the second stacked current mirror 132b. The charging transistor pair 141a is used to generate a charging current. The discharge transistor pair 141b is electrically connected to the bias generation unit 133 to receive the first bias voltage Vb1 and the second bias voltage Vb2, and the discharge transistor pair 141b is used to generate a discharge current. The inverting transistor pair 141c is electrically connected to the charging transistor pair 141a and the discharge transistor pair 141b, and the inverting transistor pair 141c is used to selectively charge the charge / discharge capacitor 142 with the charging current or discharge the charge / discharge capacitor 142 through the discharge current, and the charge / discharge capacitor 142 outputs the charging voltage VC.

[0023] Please refer to Figure 6. The voltage window comparator circuit 150 is electrically connected to the charge / discharge circuit 140 to receive the charging voltage VC. The voltage window comparator circuit 150 compares the charging voltage VC with a high reference voltage VrH and a low reference voltage VrL to output the temperature sensing signal Stem. In this embodiment, the voltage window comparator circuit 150 has a first comparator 151, a second comparator 152, a latch 153, and a buffer 154. The first comparator 151 is electrically connected to the charge / discharge capacitor 142 of the charge / discharge circuit 140 to receive the charging voltage VC. The first comparator 151 compares the charging voltage VC with the high reference voltage VrH to output a first comparison signal Scom1 to the input terminal of the latch 153. The second comparator 152 is electrically connected to the charging / discharging capacitor 142 of the charging / discharging circuit 140 to receive the charging voltage VC. The second comparator 152 compares the charging voltage VC with the low reference voltage VrL and outputs a second comparison signal Scom2 to the reset terminal of the latch 153. The latch 153 outputs the temperature sensing signal Stem through the buffer 154. The temperature sensing signal Stem is fed back to the inverting transistor pair 141c for control.

[0024] Please refer to Figure 6. The operation of the charging / discharging circuit 140 and the voltage window comparison circuit 150 is as follows: When a reset signal rst is high, a reset transistor MRt is turned on, allowing the charging voltage VC of the charging / discharging capacitor 142 to discharge to a low potential through the reset transistor MRt. Then, when the reset signal rst drops to a low potential, the reset transistor MRt is turned off. At this time, the charging voltage VC is less than the high reference voltage VrH and the low reference voltage VrL. The first comparison signal Scom1 is low, and the second comparison signal Scom2 is high, causing the temperature sensing signal Stem to be low. The temperature sensing signal Stem is fed back to the inverting transistor pair 141c, which turns on the charging current path of the charging transistor pair 141a, causing the charging voltage VC to be charged and rise. When the charging voltage VC exceeds the high reference voltage VrH, the first comparison signal Scom1 rises to a high potential, and the second comparison signal Scom2 falls to a low potential, causing the temperature sensing signal Stem to rise to a high potential. The temperature sensing signal Stem is then fed back to the inverting transistor pair 141c, which conducts the discharge current path of the discharge transistor pair 141b, causing the charging voltage VC to be discharged and decrease. In this way, the frequency of the temperature sensing signal Stem is proportional to the magnitude of the charging and discharging current of the charging and discharging current generation unit 141, and the charging and discharging current of the charging and discharging current generation unit 141 is also proportional to the subtraction current IO2 of the second PTAT, thereby obtaining the temperature sensing signal Stem whose frequency is proportional to the absolute temperature.

[0025] The present invention uses the two current subtraction circuit 130 to subtract the CTAT current twice to obtain a PTAT subtraction current with higher sensitivity to absolute temperature. Then, the temperature sensing signal is output through the charging and discharging circuit 140 and the voltage window comparison circuit 150, thereby obtaining the frequency temperature sensor 100 with a higher dynamic range and improving the output accuracy of the back-end circuit.

[0026] The scope of protection of this invention shall be determined by the appended claims. Any changes and modifications made by those skilled in the art without departing from the spirit and scope of this invention shall fall within the scope of protection of this invention.

[0027] 100: Frequency-based temperature sensor 110: PTAT Current Generation Circuit 111:PTAT Current Mirror 112: First operational amplifier 113: First variable resistor 114: Bipolar transistor pair 120: CTAT Current Generation Circuit 121: Second operational amplifier 122: Current Transistor 123: Current Mirror Transistor 124: Second variable resistor 130: Two current subtraction circuits 131: First Current Subtraction Unit S: Start-up circuit 132: Second current subtraction unit 132a: First stacked current mirror 132b: Second stacked current mirror 132c: First current mirror 132d: Third stacked current mirror 132f: First-process drift compensation transistor group; 132g: Second-process drift compensation transistor group 133: Bias Generation Unit 140: Charging and discharging circuit 141: Charge / discharge current generation unit 141a: Charged transistor pair 141b: Discharge transistor pair 141c: Inverting transistor pair 142: Charging and discharging capacitor 150: Voltage window comparator circuit 151: First comparator 152: Second comparator 153: Latch 154: Buffer rst: Reset signal V PTAT: PTAT voltage V CTAT: CTAT voltage I PTAT: PTAT current I CTAT1: First CTAT current I O1: First PTAT phase subtraction current I O2: Second PTAT phase subtraction current M f1: First current mirror transistor M f2: Second current mirror transistor M f3: Third current mirror transistor Mf4: Fourth current mirror transistor I CTAT2: Second CTAT current Ms1: First stacked transistor M s2: Second stacked transistor M s3: Third stacked transistor Ms4: Fourth stacked transistor Ms5: Fifth stacked transistor Ms6: Sixth stacked transistor Ms7: Seventh stack transistor M s8: Eighth stacked transistor Ms9: Ninth stacked transistor M s10: Tenth stacked transistor M s11: Eleventh stacked transistor M s12: Twelfth stacked transistor M cf1: First compensation transistor Mcf2: Second compensation transistor Mcf3: Third compensation transistor SW1: First switching transistor group SW2: Second switching transistor group SW3: Third switching transistor group M sw1: First switching transistor M sw2: Second switching transistor M sw3: Third switching transistor M sw4: Fourth switching transistor M sw5: Fifth switching transistor M sw6: Sixth switching transistor M sw7: Seventh Switch Transistor M sw8: Eighth switching transistor SW4: Fourth Switching Transistor Group Mcf4: Fourth Compensating Transistor Mc1: First switching transistor Mc2: Second switching transistor Mrt: Reset Transistor s1: First control signal s2: Second control signal Inverted first control signal Inverted second control signal I CTAT: CTAT current VrH: High reference voltage VrL: Low reference voltage VC: Charging voltage S tem: Temperature sensing signal S com1: First comparison signal S com2: Second comparison signal N1, N2, N3, N4: Nodes Vb1: First bias voltage Vb2: Second bias voltage Vb3: Third bias voltage

Claims

1. A frequency-based temperature sensor, comprising: a PTAT current generating circuit for generating a PTAT voltage; and a CTAT current generating circuit for generating a CTAT voltage. A current subtraction circuit includes a first current subtraction unit, a second current subtraction unit, and a bias voltage generation unit. The first current subtraction unit is electrically connected to the PTAT current generation circuit and the CTAT current generation circuit to receive the PTAT voltage and the CTAT voltage. The first current subtraction unit generates a PTAT current using the PTAT voltage and a first CTAT current using the CTAT voltage. The first current subtraction unit subtracts the first CTAT current from the PTAT current to obtain a first PTAT subtraction current. The second current subtraction unit is electrically connected to the CTAT current generation circuit and the first current subtraction unit to receive the CTAT voltage and the first PTAT subtraction current. The second current subtraction unit generates a second CTAT current using the CTAT voltage. The second current subtraction unit subtracts the second CTAT current from the first PTAT subtraction current to obtain a second PTAT subtraction current. The second PTAT subtraction current generates a bias voltage in the bias voltage generation unit. A charging / discharging circuit includes a charging / discharging current generating unit and a charging / discharging capacitor. The charging / discharging current generating unit is electrically connected to the bias generating unit to receive the bias voltage. The charging / discharging capacitor is electrically connected to the charging / discharging current generating unit. The charging / discharging current generating unit selectively provides a charging current or a discharging current to the charging / discharging capacitor. The charging / discharging capacitor outputs a charging voltage. A voltage window comparison circuit is electrically connected to the charging / discharging circuit to receive the charging voltage. The voltage window comparison circuit compares the charging voltage with a high reference voltage and a low reference voltage to output a temperature sensing signal.

2. The frequency-type temperature sensor as claimed in claim 1, wherein the first current subtraction unit has a first current mirror crystal, a second current mirror crystal, a third current mirror crystal, and a fourth current mirror crystal, the first current mirror crystal receiving the CTAT voltage and generating the first CTAT current, the second current mirror crystal receiving the PTAT voltage and generating the PTAT current, the third current mirror crystal being electrically connected to the first current mirror crystal to receive the first CTAT current, and the fourth current mirror crystal being electrically connected to the third current mirror crystal and the second current mirror crystal to receive the PTAT current, wherein the third current mirror crystal is used to mirror the first CTAT current to the fourth current mirror crystal, and the second current mirror crystal outputs the first PTAT subtraction current.

3. The frequency-type temperature sensor as claimed in claim 1, wherein the second current subtraction unit has a first stacked current mirror, a second stacked current mirror, a first current mirror and a third stacked current mirror, the first stacked current mirror being electrically connected to the first current subtraction unit and the second stacked current mirror, the first stacked current mirror receiving the first PTAT subtraction current and reflecting the first PTAT subtraction current to the second stacked current mirror, the first current mirror receiving the CTAT voltage and generating a second CTAT current, the third stacked current mirror being electrically connected to the first current mirror and the second stacked current mirror to receive the second CTAT current, the third stacked current mirror being used to mirror the second CTAT current and the second stacked current mirror outputting the second PTAT subtraction current.

4. The frequency-type temperature sensor as claimed in claim 3, wherein the first stacked current mirror has a first stacked transistor, a second stacked transistor, a third stacked transistor and a fourth stacked transistor, the first stacked transistor being electrically connected to the first current subtraction unit to receive the first PTAT subtraction current, the second stacked transistor being electrically connected to the first stacked transistor, the third stacked transistor being electrically connected to the first stacked transistor, and the fourth stacked transistor being electrically connected to the second and third stacked transistors, wherein the first and third stacked transistors are used to direct the first PTAT subtraction current mirror to the second and fourth stacked transistors.

5. The frequency-based temperature sensor of claim 3, wherein the second stacked current mirror has a fifth stacked transistor, a sixth stacked transistor, a seventh stacked transistor, an eighth stacked transistor, and a first process drift compensation transistor group, the fifth stacked transistor being electrically connected to the first stacked current mirror to receive the first PTAT subtraction current, the sixth stacked transistor being electrically connected to the fifth stacked transistor, the seventh stacked transistor being electrically connected to the fifth stacked transistor, the eighth stacked transistor being electrically connected to the sixth and seventh stacked transistors, and the first process drift compensation transistor group being electrically connected to the sixth, seventh, and eighth stacked transistors, wherein the fifth and seventh stacked transistors are used to direct the first PTAT subtraction current mirror to the sixth and eighth stacked transistors, and wherein the first process drift compensation transistor group is controlled by a process drift compensation control signal to perform current compensation.

6. The frequency-type temperature sensor as claimed in claim 5, wherein the first process drift compensation transistor group has a first compensation transistor, a first switching transistor group, a second compensation transistor, a second switching transistor group, a third compensation transistor, and a third switching transistor group, the first compensation transistor being electrically connected to the seventh and eighth stacked transistors, the first switching transistor group being electrically connected to the first compensation transistor and the sixth stacked transistor, the second compensation transistor being electrically connected to the seventh and eighth stacked transistors, the second switching transistor group being electrically connected to the second compensation transistor and the sixth stacked transistor, the third compensation transistor being electrically connected to the seventh and eighth stacked transistors, and the third switching transistor group being electrically connected to the third compensation transistor and the sixth stacked transistor, wherein the first, second, and third switching transistor groups are controlled by the process drift compensation control signal.

7. The frequency-type temperature sensor as claimed in claim 6, wherein the first switching transistor group has a first switching transistor and a second switching transistor, the second switching transistor group has a third switching transistor and a fourth switching transistor, the third switching transistor group has a fifth switching transistor and a sixth switching transistor, the first switching transistor is electrically connected to the first compensation transistor, the second switching transistor is electrically connected to the first switching transistor and the sixth stacked transistor, the third switching transistor is electrically connected to the second compensation transistor, and the fourth switching transistor is electrically connected to the first compensation transistor. The third switching transistor and the sixth stacked transistor are connected. The fifth switching transistor is electrically connected to the third compensation transistor. The sixth switching transistor is electrically connected to the fifth switching transistor and the sixth stacked transistor. The process drift compensation control signal control has a first control signal and a second control signal. The first control signal is used to control the fourth switching transistor. The inverted first control signal is used to control the second and sixth switching transistors. The second control signal is used to control the fifth switching transistor. The inverted second control signal is used to control the first and third switching transistors.

8. The frequency-based temperature sensor as claimed in claim 3, wherein the third stacked current mirror has a ninth stacked transistor, a tenth stacked transistor, an eleventh stacked transistor, a twelfth stacked transistor, and a second process drift compensation transistor group; the ninth stacked transistor is electrically connected to the first current mirror to receive the second CTAT current; the tenth stacked transistor is electrically connected to the ninth stacked transistor; the eleventh stacked transistor is electrically connected to the ninth stacked transistor; the twelfth stacked transistor is electrically connected to the tenth and eleventh stacked transistors; and the second process drift compensation transistor group is electrically connected to the tenth, eleventh, and twelfth stacked transistors. Two stacked transistors, wherein the ninth and eleventh stacked transistors are used to mirror the second CTAT current to the tenth and twelfth stacked transistors, wherein the second process drift compensation transistor group is controlled by a process drift compensation control signal to perform current compensation, wherein the second process drift compensation transistor group has a fourth switching transistor group and a fourth compensation transistor, the fourth switching transistor group is electrically connected to the tenth and twelfth stacked transistors, and the fourth switching transistor group is controlled by the process drift compensation control signal, and the fourth compensation transistor is electrically connected to the fourth switching transistor group and the eleventh and twelfth stacked transistors.

9. The frequency-type temperature sensor of claim 8, wherein the fourth switching transistor group has a seventh switching transistor and an eighth switching transistor, the seventh switching transistor being electrically connected to the tenth and twelfth stacked transistors, the eighth switching transistor being electrically connected to the seventh switching transistor and the fourth compensation transistor, the fourth compensation transistor being electrically connected to the eleventh and twelfth stacked transistors, and the process drift compensation control signal control having a first control signal and a second control signal, wherein the first control signal is used to control the seventh switching transistor, and the second control signal is used to control the eighth switching transistor.

10. The frequency-type temperature sensor of claim 1, wherein the PTAT current generating circuit has a PTAT current mirror, a first operational amplifier, a first variable resistor and a bipolar transistor pair, the first operational amplifier being electrically connected to the PTAT current mirror and outputting the PTAT voltage, the first variable resistor being electrically connected to the PTAT current mirror and the first operational amplifier, the bipolar transistor pair being electrically connected to the PTAT current mirror and the first variable resistor, the CTAT current generating circuit having a second operational amplifier, a current transistor, a current mirror transistor and a second variable resistor, the second operational amplifier being electrically connected to the first variable resistor and the bipolar transistor pair, the current transistor being electrically connected to the second operational amplifier, the current mirror transistor being electrically connected to the current transistor and the first current subtraction unit, and the current mirror transistor outputting the CTAT voltage, the second variable resistor being electrically connected to the current transistor.

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