Display panel and array substrate thereof

Abstract

A display panel and an array substrate are disclosed, including a substrate on which a plurality of pixel units is disposed. Each pixel unit includes two active devices co-constructed to form a device configuration that has a semiconductor layer and a gate electrode overlapping within a projection area of the substrate and insulated from each other and a source electrode located between two drain electrodes, wherein the semiconductor layer electrically connected to the source electrode and the two drain electrodes. A transparent electrode layer has two conductive regions electrically connected to the drain electrodes. A reflective layer partially overlaps the two drain electrodes. A passivation structure is disposed between the transparent electrode layer and the substrate and has two passivation regions opposite the two conductive regions. The source electrode forms a symmetrical pattern in the projected area of the substrate. Thus, it can achieve better display performance.

Description

Technical Field

[0001] This invention relates to a display device, and more particularly to a display panel and its array substrate suitable for a transflective display. Prior Technology

[0002] In the architecture of a semi-reflective liquid crystal display (LCD), the pixel voltage shared by each pixel is difficult to simultaneously meet the individual photoelectric needs of the reflective and transmissive areas. Although there have been some related technologies in the past, there is still room for improvement.

[0003] In view of this, it is necessary to provide a technical solution that differs from the previous one in order to solve the problems existing in the conventional technology. Summary of the Invention

[0004] In view of this, the present invention provides a display panel and its array substrate to effectively improve the display performance of a transflective display.

[0005] To achieve the above objectives, one aspect of the present invention provides an array substrate, comprising: a substrate having a plurality of pixel units disposed thereon, at least one of the plurality of pixel units comprising: two active elements co-constructing an element configuration having a semiconductor layer, a gate, a source, a first drain, and a second drain, the semiconductor layer and the gate overlapping and insulated from each other within the projection area of ​​the substrate, the source being located between the first drain and the second drain, the source, the first drain, and the second drain being electrically connected to the semiconductor layer; a transparent electrode layer having a first conductive region and a second conductive region, the first conductive region being electrically connected to the first drain, and the second conductive region being electrically connected to the second drain; a reflective layer partially overlapping the first drain and the second drain; and a planarization structure disposed between the transparent electrode layer and the substrate, the planarization structure having a first planarization region and a second planarization region, the first planarization region corresponding to the first conductive region, and the second planarization region corresponding to the second conductive region; wherein the source forms a symmetrical pattern in the projection area of ​​the substrate.

[0006] To achieve the above objectives, another aspect of the present invention provides a display panel, comprising: an array substrate; a color filter substrate disposed opposite to the array substrate; and a display medium layer disposed between the array substrate and the color filter substrate; wherein the array substrate includes a substrate having a plurality of pixel units, at least one of the plurality of pixel units comprising: two active elements co-constructing a device configuration, the device configuration having a semiconductor layer, a gate, a source, a first drain and a second drain, the semiconductor layer and the gate overlapping and insulated from each other within the projection range of the substrate, and the source being located at the first drain. Between the source electrode and the second drain electrode, the first drain electrode and the second drain electrode are electrically connected to the semiconductor layer respectively; a transparent electrode layer has a first conductive region and a second conductive region, the first conductive region being electrically connected to the first drain electrode and the second conductive region being electrically connected to the second drain electrode; a reflective layer partially overlaps the first drain electrode and the second drain electrode; and a planar structure is disposed between the transparent electrode layer and the substrate, the planar structure having a first planar region and a second planar region, the first planar region corresponding to the first conductive region and the second planar region corresponding to the second conductive region; wherein, the source electrode forms a symmetrical pattern in the projection area of ​​the substrate.

[0007] In some embodiments of the present invention, the first drain electrode and the second drain electrode form two patterns in the projection area of ​​the substrate, and the two patterns have a virtual dividing line between them. The symmetrical pattern is axially symmetrical about the virtual dividing line.

[0008] In some embodiments of the present invention, the two patterns are symmetrically distributed on both sides of the virtual dividing line.

[0009] In some embodiments of the present invention, the first drain electrode and the second drain electrode form two patterns in the projection area of ​​the substrate, and the two patterns have a virtual center point between them. The symmetrical pattern is point-symmetrical about the virtual center point.

[0010] In some embodiments of the present invention, a virtual dividing line passes through the virtual center point between the two patterns, and the two patterns are symmetrically distributed on both sides of the virtual dividing line.

[0011] In some embodiments of the present invention, the semiconductor layer and the source electrode overlap within the projection range of the reflective layer, and the projection profile of the semiconductor layer does not exceed the projection profile of the reflective layer.

[0012] In some embodiments of the present invention, the gate is electrically connected to one of a plurality of scan lines, the source is electrically connected to one of a plurality of data lines, the plurality of scan lines and the plurality of data lines together define a plurality of pixel units, each pixel unit includes a reflective region and a transmissive region, and the reflective layer is located in the reflective region.

[0013] In some embodiments of the present invention, the first conductive region includes a reflective electrode, the second conductive region includes a first penetrating electrode, the first flat region includes a reflective flat structure, the second flat region includes a penetrating flat structure, the reflective flat structure is located between the reflective electrode and the element configuration, and the penetrating flat structure is located between the first penetrating electrode and the substrate.

[0014] In some embodiments of the present invention, the reflective flat structure and the penetrating flat structure respectively include a first flat layer, a protective layer and a second flat layer, the protective layer being jointly covered by the first flat layer and the second flat layer, the reflective electrode being partially disposed on the second flat layer of the reflective flat structure, and the first penetrating electrode being partially disposed on the second flat layer of the penetrating flat structure.

[0015] In some embodiments of the present invention, the reflective planar structure and the penetrating planar structure respectively include a first planar layer, a protective layer, a second planar layer and a third planar layer. The protective layer is jointly covered by the first planar layer and the second planar layer. The reflective electrode is partially disposed in the third planar layer of the reflective planar structure, and the first penetrating electrode is partially disposed in the third planar layer of the penetrating planar structure. The penetrating planar structure further includes a second penetrating electrode, which is disposed between the second planar layer and the third planar layer of the penetrating planar structure. The first penetrating electrode disposed in the penetrating planar structure has at least one strip-shaped opening structure.

[0016] The present invention discloses a display panel and its array substrate, wherein a plurality of pixel units are disposed on the substrate, and at least one of the pixel units comprises a device configuration formed by co-constructing two active elements. The semiconductor layer and gate of the device configuration overlap and are mutually insulated within the projection area of ​​the substrate. The source is located between two drains, and the source and two drains are electrically connected to the semiconductor layer. The transparent electrode layer has two conductive regions electrically connected to the two drains. The reflective layer partially overlaps the two drains. A planar structure is disposed between the transparent electrode layer and the substrate and has two planar regions corresponding to the two conductive regions. The source forms a symmetrical pattern in the projection area of ​​the substrate. Thus, the dual active elements co-constructed in the device configuration drive the pixel electrodes of the reflective and transmissive regions respectively, enabling the liquid crystals in both the reflective and transmissive regions to be driven with their optimal parameters, thereby achieving better display performance. Simple Explanation of the Diagram

[0017] Figure 1: Schematic diagram of the structure of the display panel associated with the present invention. Figure 2: Top view of the array substrate of the first embodiment of the present invention. Figure 3: A cross-sectional view of the array substrate in Figure 2 along the A-A' line segment. Figure 4: Top view of the array substrate of the second embodiment of the present invention. Figure 5: Top view of the array substrate of the third embodiment of the present invention. Figure 6: Top view of the array substrate of the fourth embodiment of the present invention. Figure 7: Top view of the array substrate of the fifth embodiment of the present invention. Figure 8: A cross-sectional view of the array substrate in Figure 7 along the A-A' line segment. Implementation

[0018] To make the above and other objects, features, and advantages of the present invention more apparent and understandable, preferred embodiments of the present invention will be described in detail below with reference to the accompanying drawings. Furthermore, the directional terms used in this invention, such as up, down, top, bottom, front, back, left, right, inside, outside, side, surrounding, center, horizontal, transverse, vertical, longitudinal, axial, radial, uppermost, or lowermost, are merely for reference to the accompanying drawings. Therefore, the directional terms used are for illustrating and understanding the present invention, and not for limiting the present invention.

[0019] Displays with display media (such as liquid crystal displays, LCDs) have various architectures, including reflective, transmissive, and trans-reflective LCD architectures. Taking a trans-reflective LCD as an example, as shown in Figure 1, a display panel 10 includes an array substrate 11, a color filter substrate 12, and a display medium layer (such as a liquid crystal layer) 13 between them. The array substrate 11 includes several pixels, each pixel being divided into a reflective area Z1 and a transmissive area Z2. The reflective area Z1 and the transmissive area Z2 share the same pixel voltage and liquid crystal cell gap. As for the liquid crystal layer, because the light source (i.e., ambient light) L1 of the reflective area Z1 undergoes an incident and reflection process, while the light source (i.e., the transmitted backlight) L2 of the transmissive area Z2 does not undergo a reflection process, the optical path of the light sources of the reflective area Z1 and the transmissive area Z2 through the liquid crystal layer is different, resulting in different liquid crystal driving voltage requirements for the reflective area Z1 and the transmissive area Z2. Therefore, when the pixels of this architecture need to represent specific gray levels, if the pixel voltage is set only according to the electrical characteristics required by the transmission zone Z2 (such as the voltage transmittance curve, VT curve), the optical performance of the reflection zone Z1 will be sacrificed, and vice versa.

[0020] This paper proposes an array substrate for a display panel, applicable to semi-reflective displays and their derivative display devices. It primarily utilizes a co-constructed dual active element configuration with a single element to drive the pixel electrodes of the reflective and transmissive regions respectively. This allows the liquid crystals in both the reflective and transmissive regions to be driven with their optimal parameters, thereby achieving better display performance. Examples are provided below, but are not limited to these examples.

[0021] In one aspect, embodiments of the present invention provide an array substrate for a display panel, as shown in Figures 2 and 3. For the sake of simplicity, only the array substrate 20 is shown in the display panel, while the color filter substrate disposed opposite to the array substrate 20 and the display medium layer (such as an electroluminescent material including liquid crystal material or electrophoretic material) disposed therebetween are omitted. In this example, the display medium layer and the color filter substrate can be sequentially disposed on the array substrate 20 shown in Figure 3.

[0022] For example, as shown in Figures 2 and 3, the array substrate 20 includes a substrate 21 and circuit components disposed thereon. For instance, the array substrate 20 also includes scan lines SL, data lines DL, and pixel units (or pixel structures) PX disposed on the substrate 21. For simplicity, Figure 2 shows only one pixel unit PX and its associated scan line SL and data line DL. It should be understood that the substrate 21 may be provided with several pixel units PX. For example, several scan lines SL (extending along the X direction and arranged along the Y direction) and several data lines DL (extending along the Y direction and arranged along the X direction) intersect to jointly define several pixel units PX. This architecture is understandable to those skilled in the art and will not be elaborated further.

[0023] As shown in Figures 2 and 3, various material layers (including conductive-insulating-conductive structures) can be disposed on the substrate 21. For example, active elements (such as thin-film transistors) and passive elements (such as capacitors) required for pixel units can be formed by sputtering and etching. These are understandable to those skilled in the art and will not be elaborated upon. In this paper, the implementation scheme of dual active elements configured in a co-construction manner to drive the pixel electrodes of the reflective and transmissive regions respectively is mainly described.

[0024] For example, as shown in Figures 2 and 3, at least one of the several pixel units PX includes a device configuration W formed by co-constructing two active elements (such as thin-film transistors). In this paper, the two active elements in the device configuration W are exemplified by a bottom-gate thin-film transistor, but this is not a limitation, and the relevant description can also be adapted to other active elements, such as top-gate thin-film transistors.

[0025] For example, as shown in Figures 2 and 3, the component configuration W has a semiconductor layer SC, a gate GE, a source SE, a first drain DE1, and a second drain DE2. The semiconductor layer SC and the gate GE overlap within the projection range of the substrate 21 and are insulated from each other. The source SE is located between the first drain DE1 and the second drain DE2. The source SE, the first drain DE1, and the second drain DE2 are electrically connected to the semiconductor layer SC, respectively.

[0026] For example, as shown in Figures 2 and 3, a first metal material may be disposed on a substrate (e.g., a glass substrate) 21 to form a gate GE and a conductor 22 (e.g., a conductive line or a conductive plate) in the same layer; an insulating layer (e.g., SiNx or SiOxNy) 24 may be disposed on the substrate 21, the gate GE and the conductor 22; a semiconductor layer (e.g., low-temperature polycrystalline silicon (LTPS) or indium gallium zinc oxide (IGZO)) SC may be disposed on the insulating layer 24; a second metal material may be disposed on the semiconductor layer SC to form a source SE, a first drain DE1 and a second drain DE2 that are isolated from each other; the first drain DE1 and the second drain DE2 extend from both sides of the semiconductor layer SC to the insulating layer 24, thereby co-constructing a dual active element in the element configuration W.

[0027] It should be understood that, as shown in Figure 3, the area of ​​the gate GE (semiconductor layer SC) between the first drain DE1 and the source SE defines the channel length and channel width of the current channel of the first active element, and the area of ​​the gate GE (semiconductor layer SC) between the second drain DE2 and the source SE defines the channel length and channel width of the current channel of the second active element. The channel current of the first and second active elements is positively correlated with the ratio of channel width and length. Therefore, the ratio of channel width and length of the first and second active elements can be adaptively adjusted. For example, the first spacing between the source SE and the first drain DE1 and the second spacing between the source SE and the second drain DE2 can be finely adjusted so that the two drains of the dual active elements in the conducting state can have different voltages to meet the electrical requirements of the reflection region Z1 and the transmission region Z2.

[0028] Therefore, in this embodiment of the invention, the first drain and the second drain of the dual active elements configured by co-construction can drive the electrical characteristics required by the pixel electrodes of the reflective and transmissive regions respectively, so that the liquid crystals of the reflective and transmissive regions can be driven with their optimal parameters. Compared with related technologies that drive the reflective and transmissive regions with a single shared pixel voltage, this embodiment of the invention can achieve better display performance.

[0029] Of particular note is that, as shown in Figure 2, the source electrodes (SE) of the two active elements in the component configuration W are integrated into one unit. For example, the source electrode (SE) forms a symmetrical pattern (PS) in the projection area of ​​the substrate 21 to meet the electrical requirements of the two active elements. In this paper, the symmetrical pattern (PS) can be an axially symmetric or point-symmetric two-dimensional pattern, such as an H-shaped (double U) pattern (as shown in Figure 2), but is not limited to this; it can also be a T-shaped (as shown in Figure 4), a II-shaped (as shown in Figure 5), and a Z-shaped (double L) pattern (as shown in Figure 6), etc., to meet display requirements. It should be understood that the symmetrical pattern of the source electrode can be adjusted in detail (such as the overall outline, overall length, width, height, or local branches, etc.) according to individual display requirements to meet the electrical specifications required by the individual active elements in the component configuration. Examples are given below, but are not limited to this.

[0030] Optionally, in some embodiments, as shown in Figures 2 and 3, the first drain DE1 and the second drain DE2 form two patterns P1 and P2 in the projection area of ​​the substrate 21 (as shown in Figure 2). A virtual boundary line VL exists between the two patterns P1 and P2. The symmetrical pattern PS is approximately axially symmetrical (or mirror-symmetrical) with respect to the virtual boundary line VL. For example, it can be formed by combining U-shaped features on both sides of the virtual boundary line VL into a H-shaped feature (as shown in Figure 2). However, this is not a limitation; other patterns can also be formed by combining U-shaped features on both sides of the virtual boundary line VL. The L-shaped pattern can be combined into a T-shaped pattern (as shown in Figure 4), or the I-shaped pattern on both sides of the virtual boundary line VL can be combined into a II-shaped pattern (as shown in Figure 5). In this example, as shown in Figures 2, 4, and 5, the two patterns P1 and P2 are symmetrically distributed on both sides of the virtual boundary line VL. For example, the two patterns P1 and P2 are axially symmetrical about the virtual boundary line VL. The length or width of the local branch structures of the two patterns P1 and P2 on both sides of the virtual boundary line VL can be adjusted to have different contours according to individual driving requirements. In this way, the contour shape and detailed size of the symmetrical pattern can be finely adjusted to meet the driving voltage requirements of the reflective and transmissive areas in the pixel units of different displays. Furthermore, the dual active elements configured in the single element formed by co-construction can share the gate and source to control the pixel electrodes of the reflective and transmissive areas respectively, and the reflective and transmissive areas can also share the scan lines and data lines.

[0031] Alternatively, in some embodiments, as shown in Figures 3 and 6, the first drain DE1 and the second drain DE2 form two patterns P1 and P2 in the projection area of ​​the substrate 21 (as shown in Figure 6). The two patterns P1 and P2 have a virtual center point VP. The symmetrical pattern PS is approximately symmetrical (or rotationally symmetrical) with respect to the virtual center point VP. For example, it can be formed by connecting the L-shaped patterns on both sides of the virtual center point VP into a Z-shaped pattern (as shown in Figure 6), but it is not limited thereto. In addition, there is a virtual dividing line VL between the two patterns passing through the virtual center point VP. The two patterns P1 and P2 are symmetrically distributed on both sides of the virtual dividing line VL. For example, the two patterns P1 and P2 are axially symmetrical with respect to the virtual dividing line VL or point symmetrical with respect to the virtual center point VP. The length or width of the local branch structures of the two patterns P1 and P2 located on both sides of the virtual dividing line VL can be adjusted to have different contours according to individual driving requirements. This allows for fine-tuning of the outline and detailed dimensions of the symmetrical pattern to meet the driving voltage requirements of the reflective and transmissive areas in the pixel units of different displays. Furthermore, the dual active elements configured in the co-constructed single element can share the gate and source to control the pixel electrodes of the reflective and transmissive areas respectively, and the reflective and transmissive areas can also share the scan lines and data lines.

[0032] Furthermore, as shown in Figures 2 and 3, after the element configuration W is formed in the array substrate 20, a passivation structure 27 can be provided above the array substrate 20 to provide a transparent electrode layer 23 formed of a transparent conductive material (such as ITO). A reflective layer 25 and a display medium layer can also be provided above the transparent electrode layer 23.

[0033] In some embodiments, as shown in Figures 2 and 3, the structure in the array substrate 20, in addition to the element configuration W, includes at least a transparent electrode layer 23, a reflective layer 25, and a planar structure 27. The transparent electrode layer 23 has a first conductive region 23A1 and a second conductive region 23A2. The first conductive region 23A1 is electrically connected to the first drain DE1, and the second conductive region 23A2 is electrically connected to the second drain DE2. For example, the conductive region (23A1 or 23A2) of the transparent electrode layer 23 and the drain (DE1 or DE2) are electrically connected to each other through a via TH. The reflective layer 25 partially overlaps the first drain DE1 and the second drain DE2. For example, the first drain DE1 is located within the projection range of the reflective layer 25 on the substrate 21, and the second drain DE2 is partially located within the projection range of the reflective layer 25 on the substrate 21. However, this is not a limitation, and its arrangement can be finely adjusted according to the actual application. The planar structure 27 is disposed between the transparent electrode layer 23 and the substrate 21. The planar structure 27 has a first planar region 27A1 and a second planar region 27A2. The first planar region 27A1 corresponds to the first conductive region 23A1, and the second planar region 27A2 corresponds to the second conductive region 23A2.

[0034] For example, as shown in Figures 2 and 3, a single pixel unit PX is divided into a reflective region Z1 and a transmissive region Z2. The transparent electrode layer 23 is correspondingly formed with a first conductive region 23A1 (for the reflective region Z1) and a second conductive region 23A2 (for the transmissive region Z2). The transparent electrode material of the first conductive region 23A1 (forming a reflective electrode 28A) is electrically connected to the first drain DE1 via a via TH, and the transparent electrode material of the second conductive region 23A2 (forming a first transmissive electrode 28B) is electrically connected to the second drain DE2 via a via TH.

[0035] Accordingly, as shown in Figures 2 and 3, the flat structure 27 below the transparent electrode layer 23 forms two flat regions. For example, the first flat region 27A1 includes a reflective flat structure 27S1 (for the reflective region Z1), which is located between the reflective electrode 28A and the element arrangement W; the second flat region 27A2 includes a penetrating flat structure 27S2 (for the transmissive region Z2), which is located between the first penetrating electrode 28B and the substrate 21.

[0036] For example, as shown in Figures 2 and 3, the reflective planar structure 27S1 and the penetrating planar structure 27S2 respectively include a first planarization layer (including inorganic material) 271, a protective layer (including OC organic material layer) 272 and a second planarization layer 273.

[0037] For example, as shown in Figure 3, a portion of the reflective planar structure 27S1 and the penetrating planar structure 27S2 is separated by a via TH. For instance, the protective layer 272 is jointly covered by the first planar layer 271 and the second planar layer 273. The reflective electrode 28A is partially disposed on the second planar layer 273 of the reflective planar structure 27S1, and the reflective electrode 28A is electrically connected to the first drain DE1 via TH. The first penetrating electrode 28B is partially disposed on the second planar layer 273 of the penetrating planar structure 27S2, and the first penetrating electrode 28B is electrically connected to the first drain DE1 via TH. The hole TH is electrically connected to the second drain DE2. In order to improve the liquid crystal control effect in the reflective and transmissive regions, the first transmissive electrode 28B and the reflective electrode 28A are laid under the liquid crystal material as large as possible. In order to meet the different driving voltage requirements of the reflective and transmissive regions, for example, the reflective electrode 28A and the first transmissive electrode 28B are separated from each other on the reflective flat structure 27S1. There is a gap g between the reflective electrode 28A and the first transmissive electrode 28B. The size of the gap g is sufficient to make the reflective electrode 28A and the first transmissive electrode 28B electrically insulated.

[0038] On the other hand, as shown in Figure 2, the remaining part between the reflective flat structure 27S1 and the penetrating flat structure 27S2 without the via TH, the first flat layer 271, the protective layer 272 and the second flat layer 273 are stacked sequentially in the Z direction to provide the reflective electrode 28A and the first penetrating electrode 28B.

[0039] Subsequently, as shown in Figures 2 and 3, a reflective layer (such as a metal or alloy material including silver and aluminum) 25 is provided on the reflective electrode 28A to provide the light reflection structure required for the reflective area Z1.

[0040] In some embodiments, as shown in Figures 2 and 3, the gate GE is electrically connected to one of several scan lines SL, and the source SE is electrically connected to one of several data lines DL. The scan lines SL and the data lines DL together define several pixel units PX. Each pixel unit PX includes a reflective region Z1 and a transmissive region Z2, and the reflective layer 25 is located in the reflective region Z1. This allows light entering the reflective region to be reflected by the reflective layer.

[0041] In some embodiments, as shown in FIG3, the semiconductor layer SC and the source electrode SE overlap within the projection range of the reflective layer 25, and the projection outline of the semiconductor layer SC does not exceed the projection outline of the reflective layer 25. In this way, the reflective layer 25 can not only reflect light sources from the outside, but also help block light sources from shining on the semiconductor layer, thereby reducing the photoelectric effect caused by the influence of light sources on the semiconductor layer.

[0042] In some embodiments, as shown in FIG3, the first conductive region 23A1 includes a reflective electrode 28A (i.e., the pixel electrode of the reflective region), the second conductive region 23A2 includes a first transmissive electrode 28B (i.e., the pixel electrode of the transmissive region), the first flat region 27A1 includes a reflective flattening structure 27S1, and the second flat region 27A2 includes a transmissive flattening structure 27S2. The reflective flattening structure 27S1 is located between the reflective electrode 28A and the component arrangement W, and the transmissive flattening structure 27S2 is located between the first transmissive electrode 28B and the substrate 21. In this example, there is a spacing g between the reflective electrode 28A and the first transmissive electrode 28B. The spacing g is a reasonable distance to ensure that the two conductors, such as the pixel electrodes of the reflective region and the transmissive region, can be electrically isolated.

[0043] Optionally, in some embodiments, as shown in FIG3, the reflective flat structure 27S1 and the penetrating flat structure 27S2 respectively include a first flat layer 271, a protective layer 272 and a second flat layer 273. The protective layer 272 is jointly covered by the first flat layer 271 and the second flat layer 273. The reflective electrode 28A is partially disposed on the second flat layer 273 of the reflective flat structure 27S1, and the first penetrating electrode 28B is partially disposed on the second flat layer 273 of the penetrating flat structure 27S2.

[0044] Alternatively, in some embodiments, as shown in Figures 7 and 8, the reflective planar structure 27S1' and the penetrating planar structure 27S2' respectively include a first planar layer 271, a protective layer 272, a second planar layer 273, and a third planar layer 274. The protective layer 272 is jointly covered by the first planar layer 271 and the second planar layer 273. The reflective electrode 28A is partially disposed in the third planar layer 274 of the reflective planar structure 27S1, and the first penetrating electrode 28B is partially disposed in the third planar layer 274 of the penetrating planar structure 27S2. The penetrating planar structure 27S2 also includes a second penetrating electrode 29B, which is disposed between the second planar layer 273 and the third planar layer 274 of the penetrating planar structure 27S2. The first penetrating electrode 28B disposed in the penetrating planar structure 27S2 has at least one strip-shaped opening structure (e.g., a finger-shaped hollow structure) F. In this way, the dual active elements configured in the single element formed by co-construction can share the gate and source to control the pixel electrodes of the reflective and transmissive regions respectively, and the reflective and transmissive regions can also share the scan lines and data lines; furthermore, the transmissive region has two layers of transmissive electrodes (ITO) separated by a third planarization layer, wherein the upper ITO (i.e. the first transmissive electrode) has a finger-cut structure, so that the liquid crystal in the transmissive region can also be driven in the form of FFS.

[0045] On the other hand, embodiments of the present invention provide a display panel, including: an array substrate, a color filter substrate, and a display medium layer. The color filter substrate and the array substrate are disposed opposite to each other, and the display medium layer is disposed between the array substrate and the color filter substrate. The array substrate can be any of the array substrate embodiments described above, which will not be repeated here.

[0046] The display panel and its array substrate of the present invention consist of two active elements in the element configuration sharing a gate (connecting to the scan line) and a source (connecting to the data line), and two drains respectively connecting to the pixel electrodes of the transmissive and reflective regions. By adjusting parameters such as the channel length and width of the two active elements in the element configuration, the two drains of the two active elements in the element configuration can have different voltages in the conducting state, which can meet the electrical requirements of the transmissive and reflective regions.

[0047] Furthermore, since the two drains of the dual active elements in the component configuration can have different voltages to meet the electrical requirements of the transmissive and reflective regions, the design parameters can be adjusted according to the liquid crystal characteristics and cell gaps of different display products. Without the need for a dual cell gap design, the pixel voltage can be precisely matched to the liquid crystal parameters of both the reflective and transmissive regions. This allows for optimal pixel voltage driving of the liquid crystal material within both the reflective and transmissive regions, achieving better optical performance. Increased optical efficiency also improves panel contrast. Moreover, the elimination of a dual cell gap design avoids the difficulties associated with directional rubbing.

[0048] Furthermore, since the two drains of the dual active elements in the component configuration can have different voltages to meet the electrical requirements of the transmission and reflection regions, the ratio of the transmission and reflection regions can also be individually designed according to product characteristics or usage environment requirements.

[0049] The display panel and its array substrate of the above embodiments of the present invention include a plurality of pixel units disposed on a substrate. At least one of the plurality of pixel units includes a component configuration formed by two active elements. The semiconductor layer and the gate of the component configuration overlap and are mutually insulated within the projection area of ​​the substrate. The source is located between two drains. The source and the two drains are electrically connected to the semiconductor layer. The two conductive regions of the transparent electrode layer are electrically connected to the two drains. The reflective layer partially overlaps the two drains. The planar structure is disposed between the transparent electrode layer and the substrate and has two planar regions corresponding to the two conductive regions. The source forms a symmetrical pattern in the projection area of ​​the substrate.

[0050] Therefore, the above embodiments of the present invention use dual active elements configured as a single element to drive the pixel electrodes of the reflective and transmissive regions respectively, so that the liquid crystals in the reflective and transmissive regions can be driven with their optimal parameters, thereby achieving better display performance.

[0051] 10: Display Panel 11, 20: Array substrate 12: Color film substrate 13: Display media layer 21:Substrate 22: Conductor 23: Transparent electrode layer 23A1: First conductive region 23A2: Second conductive region 24: Insulation layer 25: Reflective layer 27: Flat structure 271: First flattening layer 272: Protective layer 273: Second flattening layer 274: Third flat layer 27A1: First flat area 27A2: Second flat area 27S1, 27S1': Reflective flat structure 27S2, 27S2': Penetrating flat structures 28A: Reflective electrode 28B: First Penetrating Electrode 29B: Second Penetrating Electrode F: Strip-shaped opening structure L1, L2: Light source SC: Semiconductor layer GE: Gate SE: Source DE1: First Absorption DE2: Second Absorption Pole P1, P2: Patterns PS: Symmetrical pattern PX: Pixel Unit DL: Data Line SL: Scan line TH: Via VL: Virtual Boundary Line VP: Virtual Center Point W: Component Configuration X, Y, Z: Direction Z1: Reflection Zone Z2: Transmission zone g: Spacing

Claims

1. An array substrate, comprising: A substrate is provided with a plurality of pixel units, at least one of which includes: two active elements co-constructing a device configuration having a semiconductor layer, a gate, a source, a first drain, and a second drain, the semiconductor layer and the gate overlapping and insulated from each other within the projection area of ​​the substrate, the source being located between the first drain and the second drain, and the source, the first drain, and the second drain being electrically connected to the semiconductor layer; a transparent electrode layer having a first conductive region and a second conductive region, the first conductive region being electrically connected to the first drain, and the second conductive region being electrically connected to the second drain; a reflective layer partially overlapping the first drain and the second drain; and a planarization structure disposed between the transparent electrode layer and the substrate, the planarization structure having a first planarization region and a second planarization region, the first planarization region corresponding to the first conductive region, and the second planarization region corresponding to the second conductive region; wherein the source forms a symmetrical pattern in the projection area of ​​the substrate.

2. The array substrate as claimed in claim 1, wherein the first drain and the second drain form two patterns in the projection area of ​​the substrate, the two patterns having a virtual dividing line, and the symmetrical pattern being axially symmetrical about the virtual dividing line.

3. The array substrate as described in claim 2, wherein the two patterns are symmetrically distributed on both sides of the virtual dividing line.

4. The array substrate as claimed in claim 1, wherein the first drain and the second drain form two patterns in the projection area of ​​the substrate, the two patterns having a virtual center point, and the symmetrical pattern being point-symmetrical about the virtual center point.

5. The array substrate as claimed in claim 4, wherein a virtual dividing line passes through the virtual center point between the two patterns, and the two patterns are symmetrically distributed on both sides of the virtual dividing line.

6. The array substrate as claimed in claim 1, wherein the semiconductor layer overlaps with the source electrode within the projection range of the reflective layer, and the projection profile of the semiconductor layer does not exceed the projection profile of the reflective layer.

7. The array substrate as claimed in claim 1, wherein the gate is electrically connected to one of a plurality of scan lines, the source is electrically connected to one of a plurality of data lines, the plurality of scan lines and the plurality of data lines together define a plurality of pixel units, each pixel unit including a reflective region and a transmissive region, the reflective layer being located in the reflective region.

8. The array substrate as claimed in claim 1, wherein the first conductive region includes a reflective electrode, the second conductive region includes a first penetrating electrode, the first flat region includes a reflective flattening structure, the second flat region includes a penetrating flattening structure, the reflective flattening structure being located between the reflective electrode and the element arrangement, and the penetrating flattening structure being located between the first penetrating electrode and the substrate.

9. The array substrate as claimed in claim 8, wherein the reflective planarization structure and the penetrating planarization structure each include a first planarization layer, a protective layer and a second planarization layer, the protective layer being covered by the first planarization layer and the second planarization layer, the reflective electrode being partially disposed on the second planarization layer of the reflective planarization structure, and the first penetrating electrode being partially disposed on the second planarization layer of the penetrating planarization structure.

10. The array substrate as claimed in claim 8, wherein the reflective planarization structure and the penetrating planarization structure each include a first planarization layer, a protective layer, a second planarization layer and a third planarization layer, the protective layer being jointly covered by the first planarization layer and the second planarization layer, the reflective electrode being partially disposed in the third planarization layer of the reflective planarization structure, the first penetrating electrode being partially disposed in the third planarization layer of the penetrating planarization structure, the penetrating planarization structure further including a second penetrating electrode, the second penetrating electrode being disposed between the second planarization layer and the third planarization layer of the penetrating planarization structure, and the first penetrating electrode disposed in the penetrating planarization structure having at least one strip-shaped opening structure.

11. A display panel, comprising: One array substrate; A color filter substrate is disposed opposite to the array substrate; and a display medium layer is disposed between the array substrate and the color filter substrate; wherein the array substrate includes a substrate having a plurality of pixel units, at least one of the plurality of pixel units including: two active elements co-constructing a device configuration having a semiconductor layer, a gate, a source, a first drain and a second drain, the semiconductor layer and the gate overlapping and insulated from each other within the projection range of the substrate, the source being located between the first drain and the second drain, and the source, the first drain and the second drain being electrically connected to the semiconductor layer; a transparent electrode layer having a first conductive region and a second conductive region, the first conductive region being electrically connected to the first drain and the second conductive region being electrically connected to the second drain; A reflective layer partially overlaps the first drain and the second drain; and a planar structure is disposed between the transparent electrode layer and the substrate, the planar structure having a first planar region and a second planar region, the first planar region corresponding to the first conductive region and the second planar region corresponding to the second conductive region; wherein the source electrode forms a symmetrical pattern in the projection area of ​​the substrate.

12. The display panel as claimed in claim 11, wherein the first drain and the second drain form two patterns in the projection area of ​​the substrate, the two patterns having a virtual dividing line, and the symmetrical pattern being axially symmetrical about the virtual dividing line.

13. The display panel as described in claim 12, wherein the two patterns are symmetrically distributed on both sides of the virtual dividing line.

14. The display panel as claimed in claim 11, wherein the first drain electrode and the second drain electrode form two patterns in the projection area of ​​the substrate, the two patterns having a virtual center point, and the symmetrical pattern being point-symmetrical about the virtual center point.

15. The display panel as described in claim 14, wherein a virtual dividing line passes through the virtual center point between the two patterns, and the two patterns are symmetrically distributed on both sides of the virtual dividing line.

16. The display panel as claimed in claim 11, wherein the semiconductor layer overlaps with the source electrode within the projection range of the reflective layer, and the projection profile of the semiconductor layer does not exceed the projection profile of the reflective layer.

17. The display panel as claimed in claim 11, wherein the gate is electrically connected to one of a plurality of scan lines, the source is electrically connected to one of a plurality of data lines, the plurality of scan lines and the plurality of data lines together define a plurality of pixel units, each pixel unit including a reflective area and a transmissive area, the reflective layer being located in the reflective area.

18. The display panel as claimed in claim 11, wherein the first conductive region includes a reflective electrode, the second conductive region includes a first penetrating electrode, the first flat region includes a reflective flattening structure, the second flat region includes a penetrating flattening structure, the reflective flattening structure being located between the reflective electrode and the element arrangement, and the penetrating flattening structure being located between the first penetrating electrode and the substrate.

19. The display panel as claimed in claim 18, wherein the reflective planar structure and the transmissive planar structure each include a first planar layer, a protective layer and a second planar layer, the protective layer being covered by the first planar layer and the second planar layer, the reflective electrode being partially disposed on the second planar layer of the reflective planar structure, and the first transmissive electrode being partially disposed on the second planar layer of the transmissive planar structure.

20. The display panel as claimed in claim 18, wherein the reflective planar structure and the transmissive planar structure each include a first planar layer, a protective layer, a second planar layer and a third planar layer, the protective layer being covered by the first planar layer and the second planar layer, the reflective electrode being partially disposed on the third planar layer of the reflective planar structure, the first transmissive electrode being partially disposed on the third planar layer of the transmissive planar structure, the transmissive planar structure further including a second transmissive electrode disposed between the second planar layer and the third planar layer of the transmissive planar structure, and the first transmissive electrode disposed on the transmissive planar structure having at least one strip-shaped opening structure.

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