Graphic card device, computing device, and noise reduction method for power supply

Abstract

A graphic card device, a computer device, and a noise reduction method for a power supply are provided. The noise reduction method includes: detecting a decrease change of a power consumption of a computing load; and, when the decrease change of the power consumption of the computing load exceeds a first predetermined consumption rate, enabling a dummy load and providing a power difference between the first predetermined consumption rate and the power consumption of the computing load to the dummy load, in order to reduce a current variation in at least one inductor of the power supply.

Description

[Technical Field]

[0001] This case relates to a power supply technology for computer devices, and more particularly to a noise reduction method for a display card device, a computer device, and a power supply. [Previous Technology]

[0002] Power supplies that power computer devices (such as data center servers, personal computers, laptops, graphics cards, etc.) use many passive components. Some passive components (such as inductors) inevitably generate noise due to changes in the current passing through them. The greater the change in current through the inductor, the greater the noise will inevitably be, causing inconvenience to the user. Although noise can be reduced by changing the material of the inductor, the improvement is limited. Therefore, how to reduce or improve the noise emitted by power supplies is one of the research directions. [Summary of the Invention]

[0003] This invention provides a noise reduction method for a display card device, a computer device, and a power supply, which can delay the current change on the inductor in the power supply, so that the current on the inductor can be slowly unloaded, reducing the current change on the inductor, thereby reducing or improving the noise emitted by the power supply.

[0004] The display card device of this invention includes a power supply, a computing load, and a dummy load. The power supply includes a power controller and a power supply circuit. The power supply circuit has at least one inductor and is controlled by the power controller. The computing load is coupled to the power supply. The dummy load is coupled to the power supply. The power controller controls the dummy load via a first control signal. The power controller detects a decrease in the power of the computing load. When the decrease in the power of the computing load is greater than a first predetermined consumption rate, the power controller enables the dummy load via the first control signal and provides the dummy load with a power difference between the first predetermined consumption rate and the power of the computing load to reduce the current change of the at least one inductor.

[0005] The computer device of this case includes a power supply, a computing load, and a dummy load. The power supply includes a power controller and a power supply circuit. The power supply circuit has at least one inductor and is controlled by the power controller. The computing load is coupled to the power supply. The dummy load is coupled to the power supply. The power controller controls the dummy load via a first control signal. The power controller detects a decrease in the power of the computing load. When the decrease in the power of the computing load is greater than a first predetermined consumption rate, the power controller enables the dummy load via the first control signal and provides the dummy load with the power difference between the first predetermined consumption rate and the power of the computing load to reduce the current change of the at least one inductor.

[0006] The noise reduction method of the power supply in this case includes the following steps: detecting a decrease in the power of a computing load; and when the decrease in the power of the computing load is greater than a first predetermined consumption rate, enabling a virtual load and providing a power difference between the first predetermined consumption rate and the power of the computing load to the virtual load to reduce the current change of at least one inductor in the power supply.

[0007] Based on the above, this embodiment detects changes in the power supply of the computing load by detecting one of the current monitoring pins of the computing load (e.g., the graphics processing unit (GPU) in a graphics card device), the compensation pins of the computing load, and the output voltage of the power supply circuit. When the decrease in the power supply of the load (e.g., from a current consumption of 100A to 0A per unit time) is greater than a predetermined consumption rate (the change in current consumption per unit time is less than 50A), a virtual load is enabled, and the power difference between the predetermined consumption rate and the power supply of the computing load (e.g., 50A) is provided to the virtual load, thereby reducing the current variation of the inductors in the power supply circuit and thus reducing or improving the noise emitted by the power supply. Furthermore, the duty cycle of the high-side switch or the low-side switch in the power supply circuit can be adjusted to reduce the current conduction rate in the high-side switch or the low-side switch and extend the conduction time in the high-side switch or the low-side switch, thereby reducing the current variation of at least one inductor in the power supply circuit.

Implementation Method

[0008] FIG1 is a schematic diagram of a graphics card device 100 according to an embodiment of the present invention. The graphics card device 100 mainly includes a power supply 105, a graphics processing unit (GPU) 130 as a computing load, and a virtual load 140. The graphics processing unit 130 and the virtual load 140 are respectively coupled to the power supply 105.

[0009] Power supply 105 includes power controller 110 and power supply circuit 120. Power supply 105 is, for example, a pulse width modulation (PWM) integrated circuit (IC) used in a power supply. Power supply circuit 120 is controlled by power controller 110. Power supply circuit 120 may include multiple phase adapter circuits 122-1 to 122-N. Each phase adapter circuit 122-1 to 122-N may include a control transistor and an inductor connected in series with the control transistor. In other words, power supply circuit 120 has at least one inductor.

[0010] The virtual load 140 may include multiple transistors (e.g., transistors MOS1 and MOS2). In this embodiment, transistors MOS1 and MOS2 are connected in parallel with the computing load (e.g., graphics processor 130) so that when the virtual load 140 is enabled, they can help dissipate the energy stored in multiple inductors in the power supply circuit 120.

[0011] The power controller 110 controls the virtual load 140 via a first control signal CS1. For example, the first control signal CS1 includes multiple sub-control signals, each of which is coupled to the gate terminals of transistors MOS1 and MOS2 respectively. Users of this embodiment can adjust the circuit structure used to implement the virtual load 140 according to their needs. The power controller 110 controls the power supply circuit 120 via a second control signal CS2.

[0012] The power controller 110 can detect changes in the power supply of the graphics processor 130 (e.g., rising or falling changes) by detecting one of the current monitoring pin (e.g., 'imon pin') of the graphics processor 130, the compensation pin (e.g., 'comp pin') of the graphics processor 130, and the output voltage of the power supply circuit 120.

[0013] Figure 2 is a schematic diagram of a display card device 100 according to the first embodiment of this invention. When the power controller 110 detects that the power consumption of the graphics processor 130 decreases (e.g., from 100A to 0A per unit time) greater than a first predetermined consumption rate (the change in current consumption per unit time is less than 50A), the power controller 110 enables the virtual load 140 through the first control signal CS1 to provide the power difference (e.g., 50A) between the first predetermined consumption rate and the power consumption of the calculated load to the virtual load (as shown by the dashed arrow 210), and slowly consumes the energy stored in the multiple inductors of the multiple phase adaptation circuits 122-1 to 122-N in the power supply circuit 120 by controlling the conduction time of multiple transistors (e.g., transistors MOS1 and MOS2) in the virtual load 140. In this way, the current change of the inductors in the power supply circuit 120 can be reduced, thereby reducing the noise of the inductors. Users of this embodiment can adjust the aforementioned first predetermined consumption rate according to their needs or the type of inductor in the power supply circuit 120.

[0014] In other words, when the current consumption of the graphics processor 130 decreases from 100A to 0A per unit time, this embodiment consumes 50A of current per unit time by activating the virtual load 140 (this 50A current is the power difference between the aforementioned consumption rate and the power supply of the graphics processor 130), and the current consumption on the multiple inductors in the power supply 105 decreases from 100A to 50A (rather than from 100A to 0A). In this way, the rate of current consumption on the multiple inductors in the power supply 105 is reduced, thereby reducing the current variation of the inductors in the power supply circuit 120.

[0015] FIG3 is a schematic diagram of a display card device 100 according to the second embodiment of the present invention. When the power consumption of the graphics processor 130 decreases more than the second predetermined consumption rate, the power controller 110, in addition to performing the operations described in FIG2 and the first embodiment, can also appropriately reduce the duty cycle of the high-side switch in the power supply circuit 120 by adjusting the second control signal CS2, thereby reducing the current conduction rate of the high-side switch and extending the conduction time of the high-side switch, so as to realize the slow unloading of the current in the inductor and reduce the rate of change of the current flowing through the inductor.

[0016] On the other hand, when the power consumption of the graphics processor 130 increases more than the third predetermined consumption rate, the power controller 110 can reduce the duty cycle of the low-side switch in the power supply circuit 120 by adjusting the second control signal CS2, thereby reducing the current conduction rate of the low-side switch and extending the conduction time of the low-side switch, so as to achieve slow unloading of the current in the inductor and reduce the rate of change of the current flowing through the inductor.

[0017] FIG4 is a schematic diagram of a computer device 400 according to an embodiment of the present invention. The difference between the computer device 400 of FIG4 and the display card device 100 of FIG1 is that the computer device 400 of FIG4 uses a central processing unit (CPU) 430 as the computing load. The power controller 110 detects changes in the power supply of the central processing unit 430.

[0018] When the decrease in power consumption of the central processing unit 430 exceeds a first predetermined consumption rate, the power controller 110 enables the virtual load 140 via the first control signal CS1 and provides the power difference between the first predetermined consumption rate and the power consumption of the central processing unit 430 to the virtual load 140 to reduce the current variation of the inductor in the power supply circuit 120. When the decrease in power consumption of the central processing unit 430 exceeds a second predetermined consumption rate, the power controller 110 further reduces the duty cycle of the high-side switch in the power supply circuit 120 by adjusting the second control signal CS2. When the increase in power consumption of the central processing unit 430 exceeds a third predetermined consumption rate, the power controller 110 reduces the duty cycle of the low-side switch in the power supply circuit 120 by adjusting the second control signal CS2.

[0019] FIG5 is a flowchart of a noise reduction method for a power supply according to an embodiment of the present invention. The noise reduction method of FIG5 can be applied to the display card device 100 of FIG1 or the computer device 400 of FIG4. Here, the display card device 100 of FIG1 and the noise reduction method of FIG5 are used as examples for illustration. Referring to FIG1 and FIG5 simultaneously, in step S510, the power controller 110 in the power supply 105 detects the change in power supply power of the computing load (e.g., graphics processor 130).

[0020] In step S520, the power controller 110 determines whether the decrease in power consumption of the computing load (e.g., graphics processor 130) is greater than a first predetermined consumption rate or a second predetermined consumption rate. For ease of explanation, this embodiment equates the first predetermined consumption rate to the second predetermined consumption rate. If step S520 is true, the process proceeds to step S530, where the power controller 110 enables the virtual load 140 and provides the power difference between the first predetermined consumption rate and the power consumption of the computing load (e.g., graphics processor 130) to the virtual load 140 to reduce the current variation of at least one inductor in the power supply 105. Furthermore, in step S540, the power controller 110 further reduces the rate of change of current flowing through the inductor by adjusting the second control signal CS2 to reduce the duty cycle of the high-side switch in the power supply circuit 120. After step S540 is completed, the process returns to step S520.

[0021] If step S520 is negative, proceed to step S530, where the power controller 110 determines whether the increase in power consumption of the computing load (e.g., graphics processor 130) exceeds a third predetermined consumption rate. If step S530 is positive, proceed to step S560, where the power controller 110 adjusts the second control signal CS2 to reduce the duty cycle of the low-side switch in the power supply circuit 120, thereby further reducing the rate of change of current flowing through the inductor. When step S560 is completed or step S550 is negative, return to step S520.

[0022] In summary, this embodiment detects changes in the power supply of the computing load by detecting one of the following: the current monitoring pin of the computing load (e.g., the graphics processing unit (GPU) in a graphics card device), the compensation pin of the computing load, and the output voltage of the power supply circuit. When the decrease in the power supply of the load (e.g., from a current consumption of 100A to 0A per unit time) is greater than a predetermined consumption rate (the change in current consumption per unit time is less than 50A), a virtual load is enabled, and the power difference between the predetermined consumption rate and the power supply of the computing load (e.g., 50A) is provided to the virtual load, thereby reducing the current change of the inductor in the power supply circuit and thus reducing or improving the noise emitted by the power supply. Furthermore, the duty cycle of the high-side switch or low-side switch in the power supply circuit can be adjusted to reduce the current conduction rate in the high-side switch or low-side switch and extend the conduction time in the high-side switch or low-side switch, thereby reducing the current change of at least one inductor in the power supply circuit.

[0023] Although the present invention has been disclosed above by way of embodiments, it is not intended to limit the present invention. Anyone with ordinary knowledge in the art may make some modifications and refinements without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be determined by the appended claims. [Simplified Explanation of the Diagram]

[0024] FIG1 is a schematic diagram of a display card device according to an embodiment of the present invention. FIG2 is a schematic diagram of a display card device according to a first embodiment of the present invention. FIG3 is a schematic diagram of a display card device according to a second embodiment of the present invention. FIG4 is a schematic diagram of a computer device according to an embodiment of the present invention. FIG5 is a flowchart of a noise reduction method for a power supply according to an embodiment of the present invention.

Claims

1. A display card device, comprising: A power supply includes a power controller and a power supply circuit, wherein the power supply circuit has at least one inductor and is controlled by the power controller; a computing load coupled to the power supply; and a dummy load coupled to the power supply, wherein the power controller controls the dummy load via a first control signal, wherein the power controller detects a decrease in the power of the computing load, and when the decrease in the power of the computing load is greater than a first predetermined consumption rate, the power controller enables the dummy load via the first control signal and provides the dummy load with a power difference between the first predetermined consumption rate and the power of the computing load to reduce the current change of the at least one inductor.

2. The display card device as claimed in claim 1, wherein the power controller detects the decrease in power of the computing load by detecting one of a current monitoring pin of the computing load, a compensation pin of the computing load, and an output voltage of the power supply circuit.

3. The display card device as claimed in claim 1, wherein the power controller controls the power supply circuit via a second control signal, and when the decrease in the power of the computing load is greater than a second predetermined consumption rate, the power controller further reduces the duty cycle of a high-side switch in the power supply circuit by adjusting the second control signal.

4. The display card device as claimed in claim 3, wherein, When a rise in the power of the computing load exceeds a third predetermined consumption rate, the power controller reduces the duty cycle of a low-side switch in the power supply circuit by adjusting the second control signal.

5. The display card device as claimed in claim 1, wherein the computational load is a graphics processor.

6. A computer device, comprising: A power supply includes a power controller and a power supply circuit, wherein the power supply circuit has at least one inductor and is controlled by the power controller; a computing load coupled to the power supply; and a dummy load coupled to the power supply, wherein the power controller controls the dummy load via a first control signal, wherein the power controller detects a decrease in the power of the computing load, and when the decrease in the power of the computing load is greater than a first predetermined consumption rate, the power controller enables the dummy load via the first control signal and provides the dummy load with the power difference between the first predetermined consumption rate and the power of the computing load, thereby reducing the current change of the at least one inductor.

7. The computer apparatus as claimed in claim 6, wherein the computational load is a central processing unit.

8. A noise reduction method for a power supply, comprising: Detect and calculate a decrease in the power supply of the load; And when the decrease in the power supply of the computational load is greater than a first predetermined consumption rate, a virtual load is enabled, and a power difference between the first predetermined consumption rate and the power supply of the computational load is provided to the virtual load to reduce the current variation of at least one inductor in the power supply.

9. The noise reduction method as described in claim 8, wherein the detection of the decrease in the power supply of the computing load is based on detecting one of a current monitoring pin of the computing load, a compensation pin of the computing load, and an output voltage of the power supply.

10. The noise reduction method as described in claim 8 further includes: When the decrease in the power supply of the computing load exceeds a second predetermined consumption rate, the duty cycle of a high-side switch in the power supply is also reduced; and when the increase in the power supply of the computing load exceeds a third predetermined consumption rate, the duty cycle of a low-side switch in the power supply is reduced.

Images