Arithmetic combination operation

Abstract

There is provided an apparatus comprising decoder circuitry, responsive to a mixed-element-combination instruction specifying one or more first registers and a one or more second registers, to trigger the processing circuitry to perform at least one arithmetic operation to combine each first element of a set of first elements from contiguous positions in the first registers with a corresponding second element of a set of second elements selected from the second registers according to the element information to generate a set of intermediate result elements, and to combine the intermediate result elements to generate a result element. A first element size of each first element is different to a second element size of each second element.

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