Method and computer program product and apparatus for garbage collection in flash storage device

Abstract

The invention is related to a method, a computer program product and an apparatus for garbage collection in a flash device. The method, performed by a processing unit, includes: regarding multiple data blocks with hot-data scores lower than the threshold as multiple block candidates according to multiple records in a hot-data scoring table; sorting the block candidates in ascending order based on valid page counts of the block candidates; selecting the block candidates having valid user data that can be filled with one destination block as source blocks; and programming user data of valid pages in the source blocks into a destination block in a flash module.

Description

[Technical Field]

[0001] This invention relates to storage devices, and more particularly to a garbage collection method, computer program product, and apparatus operating in a flash memory device. [Previous Technology]

[0002] Flash memory is generally divided into NOR flash memory and NAND flash memory. NOR flash memory is a random access device. The host side can provide any address to access the NOR flash memory on the address pins and obtain the data stored at that address from the data pins of the NOR flash memory in a timely manner. In contrast, NAND flash memory is not random access, but sequential access. Unlike NOR flash memory, NAND flash memory cannot access any random address. Instead, the host side needs to write sequential bytes of values ​​into the NAND flash memory to define the type of request command (e.g., read, write, discard, erase, etc.) and the address used for this command. The address can point to a page (the smallest data block in flash memory for a write operation) or a block (the smallest data block in flash memory for an erase operation).

[0003] After multiple accesses, a physical block may contain valid and invalid pages (also known as expired pages). Valid pages store valid user data, while invalid pages store invalid (old) user data. When the flash memory controller detects that the available space of the flash memory module is below a threshold, it can issue a read command to instruct the flash memory module to read and collect the user data of valid pages in several physical blocks (referred to as source blocks). Then, it issues a write command to instruct the flash memory module to rewrite the collected valid user data to an empty block (referred to as a destination block). Subsequently, the source block containing only invalid pages can provide new data storage space after erasure. The process described above is called garbage collection (GC). However, poorly designed garbage collection can affect the overall performance of the flash memory device. [Summary of the Invention]

[0004] In view of this, how to alleviate or eliminate the deficiencies in the above-mentioned related fields is a problem that needs to be solved.

[0005] This specification relates to a garbage collection method in a flash memory device, executed by a processing unit, comprising: treating multiple data blocks with thermal data scores below a threshold as multiple candidate blocks based on multiple records in a thermal data integral table; sorting the candidate blocks in ascending order based on multiple valid page counts of the candidate blocks; selecting multiple source blocks from the multiple sorted candidate blocks, starting from the candidate block with the smallest valid page count, that can fill a destination block; and writing user data of valid pages in the source blocks into the destination block in the flash memory module.

[0006] This specification also relates to a computer program product containing program code. When the processing unit executes the program code, it implements the garbage collection method in the flash memory device as described above.

[0007] This specification also relates to a garbage collection device in a flash memory device, comprising: a flash memory interface coupled to a flash memory module; and a processing unit coupled to the flash memory interface. The processing unit is configured to, based on multiple records in a thermal data integral table, treat multiple data blocks with thermal data scores below a threshold as multiple candidate blocks; sort the candidate blocks in ascending order based on multiple valid page counts of the candidate blocks; starting from the candidate block with the smallest valid page count, select multiple source blocks from the multiple sorted candidate blocks that can fill a destination block; and drive the flash memory interface to write user data of valid pages in the source blocks into the destination block in the flash memory module.

[0008] One of the advantages of the above embodiments is that by selecting candidate blocks based on the thermal data integration table as described above, the write amplification factor (WAF) is avoided in the garbage collection process due to the large amount of thermal data migration.

[0009] Other advantages of the present invention will be explained in more detail with reference to the following description and figures.

Implementation Method

[0010] Embodiments of the present invention will now be described with reference to the accompanying drawings. In these drawings, the same reference numerals denote the same or similar components, steps, or operations.

[0011] Several aspects and embodiments of this disclosure are provided below. Some embodiments can be implemented independently, while others can be combined and implemented by those skilled in the art where readily apparent. The following description is for illustrative purposes only, and specific details are provided to enable a complete understanding of the various aspects of this application. However, it will be apparent that these embodiments are not necessarily such exhaustive complete implementations. The accompanying drawings and description are not intended to limit the invention.

[0012] The following description is merely illustrative of various aspects and is not intended to limit the scope, application, or setting of this disclosure. Rather, the various aspects of the description will provide a framework for implementation by those skilled in the art. It should be understood that the function and arrangement of the elements may be changed without departing from the scope and spirit of the claims.

[0013] Referring to Figure 1. The electronic device 10 includes a host side 110, a flash memory controller 130, and a flash memory module 150, and the flash memory controller 130 and the flash memory module 150 can be collectively referred to as the device side. The electronic device 10 can be implemented in electronic products such as external storage devices, personal computers, laptop PCs, tablet computers, mobile phones, digital cameras, digital camcorders, smart TVs, smart refrigerators, and automotive electronic systems. The host interface 131 of the host 110 and the flash controller 130 can communicate with each other using protocols such as Universal Serial Bus (USB), Advanced Technology Attachment (ATA), Serial Advanced Technology Attachment (SATA), Peripheral Component Interconnect Express (PCI-E), Universal Flash Storage (UFS), and Embedded Multi-Media Card (eMMC). The flash interface 139 of the flash controller 130 and the flash module 150 can communicate with each other using Double Data Rate (DDR) protocols, such as Open NAND Flash Interface (ONFI), DDR Toggle, or other protocols. The flash memory controller 130 includes a processing unit 134, which can be implemented in various ways, such as using general-purpose hardware (e.g., a single processor, a microcontroller unit, a multiprocessor with parallel processing capabilities, a graphics processor, or other processor with computing power), and provides the functionality described later when executing software and / or firmware instructions. The processing unit 134 receives host commands, such as write commands and read commands, through a host interface 131, schedules and executes these commands.The flash memory controller 130 further includes random access memory (RAM) 136, which can be implemented as dynamic random access memory (DRAM), static random access memory (SRAM), or a combination of the two. This RAM is used to configure space as a data buffer, storing user data (also referred to as host data) read from the host 110 and about to be written to the flash memory module 150, as well as user data read from the flash memory module 150 and about to be output to the host 110. The RAM 136 can also store data required during execution, such as variables, data tables, host-address to flash-address mapping (H2F table), flash-address to host-address mapping (F2H table), etc. The flash interface 139 includes a NAND flash controller (NFC) that provides the functions required to access the flash module 150, such as a command sequencer and low-density parity check (LDPC).

[0014] The flash memory controller 130 is configurable with a bus architecture 132 for coupling components to each other to transfer data, addresses, control signals, etc. These components include a host interface 131, a processing unit 134, RAM 136, a flash memory interface 139, etc. Direct Memory Access (DMA) circuits in the components can migrate data between components through the bus architecture 132 according to instructions or control signals. For example, the DMA circuits in the host interface 131 or the flash memory interface 139 can move data from the data buffer to a specific address in RAM 136, or move data from a specific address in RAM 136 to a specific data buffer.

[0015] The flash memory module 150 provides a large amount of storage space, typically hundreds of gigabytes (GB) or even several terabytes (TB), for storing large amounts of user data, such as high-resolution images and videos. The flash memory module 150 includes control circuitry and a memory array. The memory cells in the memory array can be configured as single-level cells (SLCs), multiple-level cells (MLCs), triple-level cells (TLCs), quad-level cells (QLCs), or any combination thereof. The processing unit 134 writes user data to a specified address (destination address) in the flash memory module 150 via the flash memory interface 139, and reads user data from a specified address (source address) in the flash memory module 150. The flash interface 139 uses several electronic signals to coordinate the data and command transmission between the flash controller 130 and the flash module 150, including data lines, clock signals, and control signals. Data lines can be used to transmit commands, addresses, read and write data; control signal lines can be used to transmit control signals such as Chip Enable (CE), Address Latch Enable (ALE), Command Latch Enable (CLE), and Write Enable (WE).

[0016] Referring to Figure 2, the interface 151 in the flash memory module 150 may include four input / output channels (I / O channels, hereinafter referred to as channels) CH#0 to CH#3, each channel connecting four NAND flash memory cells. For example, channel CH#0 connects NAND flash memory cells 153#0, 153#4, 153#8, and 153#12. Each NAND flash memory cell may be packaged as an independent die. The flash memory interface 139 can enable NAND flash memory cells 153#0 to 153#3, 153#4 to 153#7, 153#8 to 153#11, or 153#12 to 153#15 by issuing one of the enable signals CE#0 to CE#3 through the interface 151. Then, user data is read from the enabled NAND flash memory cells or written to the enabled NAND flash memory cells in parallel.

[0017] Refer to Figure 3 for a partial hardware architecture of a NAND flash memory cell. Each NAND flash memory cell may contain memory blocks 300, which contain multiple memory cells, such as floating gate transistors 310 or other charge trap devices. The structure of memory blocks 300 includes multiple bit lines and multiple word lines. For simplicity, Figure 3 only shows bit lines BL1 to BL3 and word lines WL0 to WL5. For example, the floating gate transistor on any of the word lines WL0 to WL5 can store one or more pages of data.

[0018] Each NAND flash memory cell may contain multiple data planes, and each data plane may contain multiple physical blocks. To improve the efficiency of data writing and reading, physical pages in multiple data planes of multiple NAND flash memory cells can be organized into a super page (SP). For example, in the example setup shown in Figure 2, each flash memory cell contains four data planes, and each data plane contains a 4-kilobyte (KB) physical page. A super page can store 256KB of user data (= 4 channels * 4 CEs * 4 data planes * 4KB). Multiple super pages can form a super block (SB). In some embodiments, any super block can be configured as a Single Level Cell (SLC) super block, and each super page in the SLC SB is an SLC SP. In other embodiments, any superblock can be configured as a Multiple Level Cell (MLC SB), where each superpage in the MLC SB can be either the Most Significant Bit (MSB SP) or the Least Significant Bit (LSB SP). In other embodiments, any superblock can be configured as a Triple Level Cell (TLC SB), where each superpage in the TLC SB can be an MSB SP, a Center Significant Bit (CSB SP), or an LSB SP. In other embodiments, any superblock can be configured as a Quad-Level Cell (QLC SB), where each superpage in the QLC SB can be a Top Significant Bit (TSB Page), an MSB SP, a CSB SP, or an LSB SP.

[0019] In some embodiments, a Logical Block Address (LBA) managed by the host 110 can represent 512 bytes (B) of user data, and each physical page can be further divided into 8 512B sections. The LBA number can be referred to as the logical address managed by the host 110. Superblocks, physical pages, and sections can be identified using Super-block Number, Physical Page Number, and Section Number, respectively, and the combination of these numbers can be referred to as the physical address of the flash memory module 150. In other embodiments, a Host Page Number managed by the host 110 can represent 4KB of user data, and each physical page does not need to be further subdivided into sections. The Host Page Number can be referred to as the logical address managed by the host 110. Superblocks and physical pages can be identified using Super-block Number and Physical Page Number, respectively, and the combination of these numbers can be referred to as the physical address of the flash memory module 150.

[0020] Each superblock can be divided into a data block or a current block according to its function. The processing unit 134 can select an empty superblock as the current block to prepare for writing user data received from the host 110. To improve the efficiency of data writing, the user data provided by the host 110 can be written in parallel to specific physical pages in a superblock spanning multiple NAND flash memory cells. The processing unit 134 can maintain a flash-to-host (F2H) table for each current block in RAM 136, containing multiple records that store information about which logical address each physical page in the current block is associated with (or mapped to) according to the page number order. The logical address can be represented using a logical block address (LBA), host page number, or other methods and is managed by the host 110. For example, each logical block address or host page is associated with 4KB of user data. After all entity pages in a current block are filled with user data, or after the remaining pages in a current block are filled with dummy values, the processing unit 134 can drive the flash interface 139 to write the corresponding F2H table in RAM 136 into the data area of ​​a specified entity page (e.g., the last entity page) in the current block. Once the corresponding F2H table has been written to the flash module 150, this current block becomes a data block, and the user data stored in the data block will no longer change. Since user data at the same logical address may be written to different entity pages in a current block sequentially, some entity pages containing invalid data may appear in the current block. The processing unit 134 can calculate the valid page count (VPC) in the current block. Then, the processing unit 134 can select another empty superblock as the new current block.

[0021] In some embodiments, in addition to the corresponding F2H table, the processing unit 134 may also drive the flash interface 139 to write the initial VPC to the metadata area of ​​a designated entity page (e.g., the last entity page) of the current block. In other embodiments, the processing unit 134 may maintain a VPC table in RAM 136 to store the VPCs of all data blocks. Each time a new data block is generated, the processing unit 134 may update the contents of the VPC table to add a new record for storing the VPC of the new data block. After updating the VPC table for a preset number of data blocks, the processing unit 134 may drive the flash interface 139 to write the latest VPC table to a designated entity address in the flash module 150.

[0022] In addition to writing the F2H table to the specified entity page in the current block, the processing unit 134 also needs to update the H2F table according to the contents of the F2H table in the current block. This is so that when a host read command is executed in the future, the information on which entity address the user data associated with a specific logical address is actually stored can be quickly found from the H2F table. The H2F table contains multiple records, storing information on which logical address the user data of each logical address is actually stored in the order of logical addresses. However, since RAM 136 cannot provide enough space to store the entire H2F table for the processing unit 134 to quickly look up in the future during data read operations, the H2F table can be divided into multiple H2F sub-tables and stored in the flash memory module 150, so that the corresponding H2F sub-table can be read from the flash memory module 150 to RAM 136 in the future during data read operations.

[0023] After multiple accesses, a physical block may contain valid and invalid pages (also known as expired pages). Valid pages store valid user data, while invalid pages store invalid (old) user data. When the flash memory controller 130 (specifically, processing unit 134) detects that the available space of the flash memory module 150 is below a threshold, it can issue a read command to instruct the flash memory module 150 to read and collect the user data of valid pages in several data blocks (referred to as source blocks). Then, it issues a write command to instruct the flash memory module to rewrite the collected valid user data to an empty superblock (referred to as a destination block). Subsequently, the source block containing only invalid pages can provide new data storage space after erasure. The process described above is called garbage collection (GC) processing. The entire GC process includes three stages: selection and sequential arrangement of source blocks; arrangement of valid user data in the destination block; and migration of valid user data and release of source blocks. However, if the selected source block contains a lot of hot data (frequently updated data), the hot data newly written to the destination block will quickly become invalid again due to updates on the host side. Therefore, the large amount of hot data migration in GC processing increases the Write Amplification Factor (WAF), thereby reducing the overall performance of the device.

[0024] To avoid increasing WAF due to the migration of large amounts of hot data during GC processing, this embodiment of the invention proposes a mechanism to avoid selecting data blocks containing a large amount of valid hot data (also known as hot data blocks) as source blocks. In addition to the VPC table, the processing unit 134 can also maintain a hot-data scoring table, which contains multiple records, each storing the hot-data score of the corresponding data block. A higher hot-data score indicates that the corresponding data block contains more hot data.

[0025] In a data write operation for executing a host write command, the processing unit 134 updates the hot data fraction of the current block based on the access frequency information carried in the host write command. When the access frequency information indicates that the logical address range indicated by the host write command has infrequent writes and infrequent reads, the hot data fraction of the current block is added to a first value. When the access frequency information indicates that the logical address range indicated by the host write command has infrequent writes and frequent reads, the hot data fraction of the current block is added to a second value. When the access frequency information indicates that the logical address range indicated by the host write command has frequent writes and frequent reads, the hot data fraction of the current block is added to a third value. The first, second, and third values ​​are integers greater than 0, the first value is less than the second value, and the second value is less than the third value.

[0026] For example, according to the NVM Command Set Specification, Revision 1.0 released on May 18, 2021, bits 0 to 3 of the Command Dword 13 of the host write command contain an access frequency attribute. A value of "0h" indicates that no frequency information is provided. A value of "1h" indicates that this LBA range is expected to have a moderate number of reads and writes. A value of "2h" indicates that the specified LBA range will have infrequent writes and infrequent reads. A value of "3h" indicates that the specified LBA range will have infrequent writes and frequent reads. A value of "4h" indicates that the specified LBA range will have frequent writes and infrequent reads. A value of "5h" indicates that the specified LBA range will have frequent writes and frequent reads. A value of "6h" for the access frequency attribute represents a one-time write. When the access frequency attribute value in the executed host write command is "3h", the processing unit 134 increments the hot data fraction of the current block by 1. When the access frequency attribute value in the executed host write command is "4h", the processing unit 134 increments the hot data fraction of the current block by 2. When the access frequency attribute value in the executed host write command is "5h", the processing unit 134 increments the hot data fraction of the current block by 3.

[0027] In other embodiments, when the access frequency information indicates that the logical address range to which the host write command indicates writing has infrequent writes and infrequent reads, the hot data fraction of the current block is added to the product of a first value and the length of the logical address range. When the access frequency information indicates that the logical address range to which the host write command indicates writing has infrequent writes and frequent reads, the hot data fraction of the current block is added to the product of a second value and the length of the logical address range. When the access frequency information indicates that the logical address range to which the host write command indicates writing has frequent writes and frequent reads, the hot data fraction of the current block is added to the product of a third value and the length of the logical address range. The first, second, and third values ​​are integers greater than 0, the first value is less than the second value, and the second value is less than the third value.

[0028] In some embodiments, the processing unit 134 may drive the flash interface 139 to write the last hot data score of the current block into the metadata area of ​​a designated entity page (e.g., the last entity page) of the current block. In other embodiments, the processing unit 134 may maintain a hot data integration table in RAM 136 to store the hot data scores of all data blocks. Each time a new data block is generated, the processing unit 134 may update the contents of the hot data integration table to add a new record for storing the hot data score of the new data block. After updating the hot data integration table for a preset number of data blocks, the processing unit 134 may drive the flash interface 139 to write the latest hot data integration table into a designated entity address in the flash module 150.

[0029] In some embodiments, the processing unit 134 may further update the hot data score table based on the access frequency information carried in the host read command during the data read operation for executing the host read command. When the access frequency information indicates that the logical address range indicated by the host read command has infrequent writes and infrequent reads, a first value is added to the hot data score associated with all read data blocks. When the access frequency information indicates that the logical address range indicated by the host read command has infrequent writes and frequent reads, a second value is added to the hot data score associated with all read data blocks. When the access frequency information indicates that the logical address range indicated by the host read command has frequent writes and frequent reads, a third value is added to the hot data score associated with all read data blocks. The first, second, and third values ​​are integers greater than 0, the first value is less than the second value, and the second value is less than the third value.

[0030] For example, according to the Non-volatile Memory Command Set Specification, Revision 1.0 released on May 18, 2021, bits 0 to 3 of the command double word 13 of the host read command contain an access frequency attribute. A value of "0h" for the access frequency attribute indicates that no frequency information is provided. A value of "1h" indicates that this LBA range is expected to have a normal number of reads and writes. A value of "2h" indicates that the specified LBA range will have infrequent writes and infrequent reads. A value of "3h" indicates that the specified LBA range will have infrequent writes and frequent reads. A value of "4h" indicates that the specified LBA range will have frequent writes and infrequent reads. A value of "5h" indicates that the specified LBA range will have frequent writes and frequent reads. A value of "6h" indicates a single read. When the access frequency attribute value in the executed host read command is "3h", the processing unit 134 increments the thermal data score associated with all read data blocks in the thermal data integration table by 1. When the access frequency attribute value in the executed host read command is "4h", the processing unit 134 increments the thermal data score associated with all read data blocks in the thermal data integration table by 2. When the access frequency attribute value in the executed host read command is "5h", the processing unit 134 increments the thermal data score associated with all read data blocks in the thermal data integration table by 3.

[0031] In other embodiments, when the access frequency information indicates that the logical address range read by this host read command has infrequent writes and infrequent reads, the hot data fraction associated with all read data blocks is added to the product of a first value and the length of this logical address range. When the access frequency information indicates that the logical address range read by this host read command has infrequent writes and frequent reads, the hot data fraction associated with all read data blocks is added to the product of a second value and the length of this logical address range. When the access frequency information indicates that the logical address range read by this host read command has frequent writes and frequent reads, the hot data fraction associated with all read data blocks is added to the product of a third value and the length of this logical address range. The first, second, and third values ​​are integers greater than 0, the first value is less than the second value, and the second value is less than the third value.

[0032] Each time a new host read command is executed, the processing unit 134 can update the hot data score associated with all read data blocks. After updating the hot data score table for a preset number of data blocks, the processing unit 134 can drive the flash interface 139 to write the latest hot data score table to a specified physical address in the flash module 150.

[0033] An example of a thermal data integration table is shown in Table 1 below: Table 1 Block number thermal data fractions #1 2200 #2 599 #3 1242 #4 805 Table 1 shows that the hot data fractions for data blocks (DBK) #1, #2, #3 and #4 are 2200, 599, 1242 and 805, respectively.

[0034] When the flash memory controller 130 (specifically, the processing unit 134) detects that the number of available superblocks (or empty superblocks) in the flash memory module 150 is lower than a threshold, a GC processing method is executed. Referring to Figure 4, the processing unit 134 implements the GC processing method when loading and executing the Firmware Translation Layer (FTL) code. A detailed explanation follows:

[0035] Step S410: Based on the records in the thermal data integration table, select data blocks with thermal data scores below a threshold as candidate blocks. For example, referring to the example in Table 1, if the threshold is set to 1000, data blocks DBK#2 and DBK#4 are selected as candidate blocks. In other words, data blocks DBK#1 and DBK#3 (that is, data blocks containing more thermal data) are excluded from the candidate blocks to avoid increasing WAF due to unnecessary thermal data migration. In some embodiments, the processing unit 134 may drive the flash interface 139 to read the thermal data integration table from a specified physical address in the flash module 150, and obtain the thermal data scores of all data blocks from the thermal data integration table. Then, the processing unit 134 selects candidate blocks from all data blocks based on the obtained thermal data scores and the above-mentioned filtering conditions.

[0036] Step S420: Sort the candidate blocks in ascending order according to their VPCs, and select a preset number of candidate blocks (MaxNumSBLK, e.g., 16) starting from the candidate block with the fewest VPCs. In some embodiments, the processing unit 134 may drive the flash interface 139 to read the VPC of each data block from the metadata area of ​​a specified entity page (e.g., the last entity page) in the flash module 150. In other embodiments, the processing unit 134 may drive the flash interface 139 to read the VPC table from a specified entity address in the flash module 150, and obtain the VPCs of all data blocks from the VPC table. Then, the processing unit 134 sorts all data blocks in ascending order according to the obtained VPCs.

[0037] Step S430: Set variables i, VPCtemp, and VPCtotal to 0. Processing unit 134 uses variable i to record the number of the source block currently being processed, and uses VPCtemp and VPCtotal to record the VPCs of the currently accumulated source blocks. Throughout the process, processing unit 134 ensures that VPCtotal does not exceed twice the maximum number of pages that can be written to a destination block, MaxPDBLK.

[0038] Step S440: Determine whether variable i is greater than the preset number MaxNumSBLK-1. If yes, it means that user data of all valid pages in the source block can be written to the destination block, and this process ends. Otherwise, the process continues to step S445.

[0039] Step S445: Set the data block associated with VPCi as the source block.

[0040] Step S450: Calculate VPCtemp = VPCtemp + VPCi, where VPCi represents the VPC of the i-th source block.

[0041] Step S460: Determine whether the variable VPCtemp is greater than the maximum number of pages that can be written to a destination block, MaxPDBLK. If yes, it means that the accumulated VPCs up to the i-th source block have exceeded the maximum number of pages that can be written to a destination block, MaxPDBLK, and the process continues to proceed to step S490. Otherwise, the process continues to proceed to step S470.

[0042] Step S470: Calculate VPCtotal = VPCtotal + VPCi, where VPCi represents the VPC of the i-th source block.

[0043] Step S480: Increment variable i by 1.

[0044] Step S490: Use multiple batches to write user data of valid pages in the source block to the destination block in the flash memory module 150. In some embodiments, the processing unit 134 may perform a preset time in each batch to sequentially write user data of valid pages in the source block that have not yet been written to empty pages in the destination block in the flash memory module 150. In other embodiments, the processing unit 134 may sequentially write user data of a preset number of valid pages in the source block that have not yet been written to empty pages in the destination block in each batch.

[0045] Step S495: Update the corresponding F2H table to reflect the operation result of GC processing. The updated F2H table contains the F2H tables corresponding to the source block and the destination block. Then, update the contents of the H2F table according to the updated F2H table.

[0046] In some embodiments, each source block is an SLC SB, and the destination block is a non-SLC SB (e.g., MLC SB, TLC SB, or QLC SB). With this setup, through the candidate block selection described above, hot data is minimized from being migrated to non-SLC SBs during GC processing. Since most of the hot data is still stored in SLC blocks, better read performance can be achieved at the device end.

[0047] Although the present invention has been described and illustrated herein with reference to specific embodiments, the invention is not intended to be limited to the details shown. Rather, various modifications to the details may be made within the scope and equivalents of the claims without departing from the invention. It should be understood that the above description is illustrative and should not be construed as limiting the invention. Various modifications, applications, and / or combinations of the embodiments will be apparent to those skilled in the art without departing from the scope of the invention as defined by the claims.

[0048] It will be readily understood by those skilled in the art that the invention discussed above can be implemented using different configurations of hardware elements than those disclosed. Therefore, although the invention has been described based on these preferred embodiments, certain modifications, variations, and alternative constructions will be apparent to those skilled in the art, and are also within the scope of the invention.

[0049] It must be understood that the words “comprising” and “including” used in this specification are used to indicate the presence of specific technical features, values, method steps, work processes, elements and / or components, but do not exclude the addition of more technical features, values, method steps, work processes, elements, components, or any combination thereof.

[0050] The use of terms such as “first,” “second,” and “third” in the claims is to modify the elements in the claims and is not intended to indicate that there is a priority order, a preceding relationship, or that one element precedes another, or the chronological order of the execution of the method steps. They are only used to distinguish elements with the same name.

[0051] It must be understood that when an element is described as "connected" or "coupled" to another element, it can be a direct connection or coupling to other elements, and intermediate elements may be involved. Conversely, when an element is described as "directly connected" or "directly coupled" to another element, there are no intermediate elements. Other terms used to describe the relationship between elements can be interpreted in a similar way, such as "between" versus "directly between," or "adjacent" versus "directly adjacent," and so on.

[0052] The terms "device" or "module" are not limited to one or a specific number of physical objects (e.g., a smartphone, a controller, a processing system, etc.). As used herein, a device can be any electronic device having one or more components that performs at least some of the functions of the invention disclosed herein. Although the description and examples use the terms "device" or "module" to describe various aspects of the invention, the terms "device" or "module" are not limited to a particular configuration, type, or number of entities. Furthermore, the terms "system" or "module" are not limited to multiple components or a particular orientation. For example, a system may be implemented on one or more printed circuit boards or other substrates and may have movable or static components. Although the description and examples use the term "system" to describe various aspects of the invention disclosed herein, the term "system" is not limited to a particular configuration, type, or number of entities.

[0053] Specific details are provided in the above description to aid in a thorough understanding of the various aspects of the invention. However, those skilled in the art will understand that these aspects can be implemented without these specific details. For clarity of explanation, in some instances, the technology may be presented as comprising individual functional blocks, including devices, device components, steps or subroutines embodied in software methods, or combinations of hardware and software. Other additional components, different from those shown in the figures and / or described herein, may also be used. For example, circuits, systems, networks, processes, and other components may be shown as components in block diagram form to avoid obscuring these aspects with unnecessary detail. In other instances, to avoid obscuring these aspects with unnecessary detail, well-known circuits, processes, algorithms, structures, and techniques may be shown without unnecessary detail.

[0054] Some aspects can be described as processes or methods in the text, and can be shown as flowcharts, data flow diagrams, structure diagrams, or block diagrams. Although flowcharts can describe operations as sequential processes, multiple operations can be executed in parallel or simultaneously. Furthermore, the order of these operations can be rearranged. The process terminates when an operation is completed, but there may be other steps not included in the diagram. A process can correspond to a method, function, program, subroutine, subroutine, etc. When a process corresponds to a function, its termination can correspond to the function returning to the calling function or the main function.

[0055] All or part of the steps in the method described in this invention can be implemented using computer instructions, such as a firmware translation layer (FTL) in a storage device, a driver for specific hardware, etc. Furthermore, they can also be implemented in other types of programs. Those skilled in the art can transcribe the methods of the embodiments of this invention into computer instructions, which will not be described further for the sake of brevity. The computer instructions for implementing the methods according to the embodiments of this invention can be stored on a suitable computer-readable medium or placed on a network server accessible via a network (e.g., the Internet, or other suitable carrier).

[0056] Computer-readable storage media includes volatile and non-volatile, removable and non-removable media that store information using any method or technology, such as computer-readable instructions, data structures, program modules, or other data. Computer-readable storage media includes, but is not limited to, RAM, ROM, EEPROM, flash memory or other memory, CD-ROM, DVD, Blu-ray disc or other optical storage, magnetic cards, magnetic tape, magnetic disks or other magnetic storage, or other carriers that can be used to store information required and accessed by an instruction execution system. It should be noted that computer-readable storage media can be paper or other suitable media used to print program code so that the program code can be obtained electrically, such as by optical scanning of paper or other media, and then, if necessary, compiled, decoded or otherwise processed, and then stored in the memory of an electronic device.

[0057] The code can be executed by a processor, which may include one or more processors, such as one or more Digital Signal Processors (DSPs), general-purpose microprocessors, application-specific integrated circuits, field-programmable logic arrays (FPGAs), or other equivalent integrated or discrete logic circuits. Such a processor can be configured to perform any of the techniques described in the disclosure. A general-purpose processor may be a microprocessor; however, in alternative instances, the processor may be any conventional processor, controller, microprocessor, or state machine. The processor may be implemented as a combination of multiple computing devices, such as DSPs and microprocessors, multiple microprocessors, one or more microprocessors paired with a DSP core, or any other similar configuration. Accordingly, the term "processor" as used herein may refer to any of the foregoing structures, any combination of the foregoing structures, or any other structure or device suitable for implementing the counts described herein.

[0058] The various illustrative logic blocks, modules, engines, circuits, and algorithm steps described herein can be implemented as electronic hardware, computer software, firmware, or any combination thereof. To clearly illustrate the interchangeability of hardware and software, the various illustrative components, blocks, modules, engines, circuits, and steps have been generally described above in terms of their functions. Whether these functions are implemented in hardware or software depends on the specific application scenario and the design constraints imposed on the entire system. Those skilled in the art can implement the described functions in different ways for each specific application scenario, but such implementation decisions should not be construed as departing from the scope of this application.

[0059] Although Figures 1 to 3 include the elements described above, it is not excluded that more additional elements may be used to achieve better technical effects without departing from the spirit of the invention. Furthermore, although the flowchart in Figure 4 is executed in a specified order, those skilled in the art can modify the order of these steps to achieve the same effect without departing from the spirit of the invention. Therefore, the present invention is not limited to using only the order described above. Moreover, those skilled in the art can also integrate several steps into one step, or perform more steps sequentially or in parallel in addition to these steps, and the present invention is not limited thereto.

[0060] Although the present invention has been described using the above embodiments, it should be noted that these descriptions are not intended to limit the invention. On the contrary, this invention covers obvious modifications and similar arrangements that will be apparent to those skilled in the art. Therefore, the scope of the claims should be interpreted in the broadest possible sense to include all obvious modifications and similar arrangements. [Simplified Explanation of the Diagram]

[0061] Figure 1 is a system architecture diagram of an electronic device according to an embodiment of the present invention.

[0062] Figure 2 is a schematic diagram of a flash memory module according to an embodiment of the present invention.

[0063] Figure 3 is a schematic diagram of a portion of the hardware architecture of a NAND flash memory cell according to an embodiment of the present invention.

[0064] Figure 4 is a flowchart of a waste recycling and treatment method according to an embodiment of the present invention.

Claims

1. A garbage collection method in a flash memory device, executed by a processing unit, the method comprising: classifying multiple data blocks with thermal data scores below a threshold as multiple candidate blocks based on multiple records in a thermal data integration table, wherein, Each hot data score in the plurality of records represents the frequency of access to a specific data block; a higher hot data score indicates that the corresponding data block contains more hot data. The plurality of candidate blocks are sorted in ascending order based on the plurality of effective page counts of the plurality of candidate blocks. Starting with the candidate block with the smallest effective page count, multiple source blocks are selected from the plurality of sorted candidate blocks whose effective user data can fill a destination block. The user data of the effective pages in the plurality of source blocks is written into the destination block in the flash memory module.

2. The garbage collection method in the flash memory device as described in claim 1, comprising: updating a plurality of flash-host lookup tables associated with the plurality of source blocks and the destination block to reflect write results; and updating the contents of the host-flash lookup table based on the updated flash-host lookup table.

3. The garbage collection method in the flash memory device as described in claim 1, wherein, Each record stores the hot data fraction of the corresponding data block.

4. The garbage collection method in the flash memory device as described in claim 3, comprising: during a data write operation for executing a host write command, updating the hot data score of the current block based on first access frequency information carried in the host write command; and after the current block is filled and becomes a new data block, adding a record to the hot data score table to store the hot data score of the new data block.

5. A garbage collection method in a flash memory device as described in claim 4, comprising: when the first access frequency information indicates that a first logical address range to be written to by the host write command has infrequent writes and infrequent reads, adding a first value to the hot data fraction of the current block, or adding the product of the first value and the length of the first logical address range; when the first access frequency information indicates that the first logical address range to be written to by the host write command has infrequent writes and frequent reads, adding a second value to the hot data fraction of the current block, or adding the product of the second value and the length of the first logical address range; and when the first access frequency information indicates that the first logical address range to be written to by the host write command has frequent writes and frequent reads, adding a third value to the hot data fraction of the current block, or adding the product of the third value and the length of the first logical address range, wherein, The first value, the second value, and the third value are all integers greater than 0, the first value is less than the second value, and the second value is less than the third value.

6. The garbage collection method in the flash memory device as described in claim 4, comprising: updating the thermal data integration table in a data read operation for executing a host read command, based on second access frequency information carried in the host read command.

7. A garbage collection method in a flash memory device as claimed in claim 6, comprising: when the second access frequency information indicates that a second logical address range read by the host read command has infrequent writes and infrequent reads, adding a first value to a plurality of hot data fractions associated with a plurality of read data blocks, or adding the product of the first value and the length of the second logical address range; when the second access frequency information indicates that the second logical address range read by the host read command has infrequent writes and frequent reads, adding a second value to the plurality of hot data fractions associated with the plurality of read data blocks, or adding the product of the second value and the length of the second logical address range; and when the second access frequency information indicates that the second logical address range read by the host read command has frequent writes and frequent reads, adding a third value to the plurality of hot data fractions associated with the plurality of read data blocks, or adding the product of the third value and the length of the second logical address range, wherein, The first value, the second value, and the third value are all integers greater than 0, the first value is less than the second value, and the second value is less than the third value.

8. A computer program product comprising program code, wherein, When the processing unit executes the code, it implements the garbage collection method in the flash memory device as described in any one of claims 1 to 7.

9. A garbage collection device in a flash memory device, comprising: a flash memory interface coupled to a flash memory module; and a processing unit coupled to the flash memory interface, configured to, based on multiple records in a thermal data integration table, treat multiple data blocks with thermal data scores below a threshold as multiple candidate blocks, wherein... Each hot data score in the plurality of records represents the frequency of access to a specific data block; a higher hot data score indicates that the corresponding data block contains more hot data. The plurality of candidate blocks are sorted in ascending order based on the plurality of effective page counts of the plurality of candidate blocks. Starting with the candidate block with the smallest effective page count, a plurality of source blocks are selected from the plurality of sorted candidate blocks whose effective user data can fill a destination block. The flash interface is then driven to write the user data of the effective pages in the plurality of source blocks into the destination block in the flash module.

10. A garbage collection device in a flash memory device as described in claim 9, wherein, The processing unit is configured to update multiple flash-host lookup tables associated with the multiple source blocks and the multiple destination blocks to reflect the write results; and to update the contents of the host-flash lookup table based on the updated flash-host lookup table.

11. A garbage collection device in a flash memory device as described in claim 9, wherein, Each record stores the hot data fraction of the corresponding data block.

12. A garbage collection device in a flash memory device as claimed in claim 11, wherein, The processing unit is configured to update the hot data score of the current block based on the first access frequency information carried in the host write command during a data write operation for executing a host write command; and to add a new record to the hot data score table to store the hot data score of the new data block after the current block is filled and becomes a new data block.

13. A garbage collection device in a flash memory device as described in claim 12, wherein, The processing unit is configured to: when the first access frequency information indicates that the first logical address range indicated by the host write command has infrequent writes and infrequent reads, add a first value to the hot data fraction of the current block, or add the product of the first value and the length of the first logical address range; when the first access frequency information indicates that the first logical address range indicated by the host write command has infrequent writes and frequent reads, add a second value to the hot data fraction of the current block, or add the product of the second value and the length of the first logical address range; and when the first access frequency information indicates that the first logical address range indicated by the host write command has frequent writes and frequent reads, add a third value to the hot data fraction of the current block, or add the product of the third value and the length of the first logical address range, wherein the first value, the second value, and the third value are integers greater than 0, the first value is less than the second value, and the second value is less than the third value.

14. A garbage collection device in a flash memory device as described in claim 12, wherein, The processing unit is configured to update the thermal data integration table based on the second access frequency information carried in the host read command during a data read operation for executing a host read command.

15. A garbage collection device in a flash memory device as described in claim 14, wherein, The processing unit is configured to, when the second access frequency information indicates that the second logical address range read by the host read command has infrequent writes and infrequent reads, add a first value to the multiple hot data fractions associated with the multiple read data blocks, or add the product of the first value and the length of the second logical address range; when the second access frequency information indicates that the second logical address range read by the host read command has infrequent writes and frequent reads, add a second value to the multiple hot data fractions associated with the multiple read data blocks, or add the product of the second value and the length of the second logical address range; and when the second access frequency information indicates that the second logical address range read by the host read command has frequent writes and frequent reads, add a third value to the multiple hot data fractions associated with the multiple read data blocks, or add the product of the third value and the length of the second logical address range, wherein the first value, the second value, and the third value are integers greater than 0, the first value is less than the second value, and the second value is less than the third value.

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