Controller for generating customized output data

Abstract

A controller for generating a customized output data is provided. The controller includes a memory circuit, a computing circuit and a timer. The operation circuit receives the first data, obtains a plurality of time lengths of stages of voltage states corresponding to the first data, and obtains a maximum common factor of the time lengths as a sampling time length according to the time lengths, and stores the sampling time length into the memory circuit. The timer samples a second data according to the sampling time length. The computing circuit generates the customized output data according to voltage states of the sampled second data.

Description

[Technical Field]

[0001] The present invention relates to a controller, and more particularly to a controller for generating custom output data. [Previous Technology]

[0002] A controller can be used to control the operation of external components. External components may be, for example, light-emitting elements. Generally, a controller can control external components based on instructions with a preset format. However, when external components are changed or upgraded, the format of the instructions or data used by the external components changes. The controller can no longer control the external components using instructions with a preset format, nor can it interpret feedback data from the external components. Therefore, the controller must also be changed or upgraded.

[0003] Therefore, how to provide a controller that can generate custom output data based on the received data is one of the research focuses of those skilled in the art. [Summary of the Invention]

[0004] The present invention provides a controller capable of generating custom output data based on received data.

[0005] In one embodiment of the present invention, the controller includes a memory circuit, an arithmetic circuit, and a timer. The arithmetic circuit is coupled to the memory circuit. The arithmetic circuit receives first data, obtains multiple time lengths for multiple stages corresponding to multiple voltage states of the first data, obtains the greatest common factor of the multiple time lengths as a sampling time length, and stores the sampling time length in the memory circuit. The timer is coupled to the arithmetic circuit. The timer samples second data according to the sampling time length. The arithmetic circuit generates custom output data based on the multiple voltage states of the sampled second data.

[0006] Based on the above, the arithmetic circuit receives first data and obtains the greatest common factor of the multiple time lengths of the multiple stages corresponding to the multiple voltage states of the first data. The timer samples the second data according to the sampling time length. The arithmetic circuit generates custom output data based on the multiple voltage states of the sampled second data. In this way, the controller can generate custom output data based on the received data.

Implementation Method

[0008] Some embodiments of the present invention will now be described in detail with reference to the accompanying drawings. Component symbols used in the following description are considered to be the same or similar components when they appear in different drawings. These embodiments are only a part of the present invention and do not disclose all possible implementations of the invention. More precisely, these embodiments are merely examples within the scope of the patent application of the present invention.

[0009] Please refer to FIG1, which is a schematic diagram of a controller according to an embodiment of the present invention. In this embodiment, the controller 100 includes a memory circuit 110, an arithmetic circuit 120, and a timer 130. The arithmetic circuit 120 is coupled to the memory circuit 110. The arithmetic circuit 120 receives first data SD1 and obtains the time lengths TL1~TLn of multiple stages corresponding to multiple voltage states of the first data SD1. The arithmetic circuit 120 obtains the greatest common factor GF of the time lengths TL1~TLn based on the time lengths TL1~TLn, uses the greatest common factor GF as the sampling time length TLS, and stores the sampling time length TLS in the memory circuit 110.

[0010] In this embodiment, timer 130 is coupled to arithmetic circuit 120. Timer 130 samples second data SD2 according to sampling time length TLS. Arithmetic circuit 120 generates custom output data SDC based on multiple voltage states of the sampled second data SD2. For example, arithmetic circuit 120 may send the sampling time length TLS stored in memory circuit 110 to timer 130, thereby causing timer 130 to sample second data SD2 according to sampling time length TLS.

[0011] In this embodiment, the first data SD1 may be data received by the arithmetic circuit 120 from external component ED1 (e.g., a controlled component such as a light-emitting element or a fan) and external component ED2 (e.g., a control interface). The second data SD2 may be data generated internally by the controller 100 or data from at least one of the external components ED1 and ED2. Once the first data SD1 from the external component is received, the controller 100 can generate custom output data SDC based on the second data SD2. The controller 100 can provide the custom output data SDC to the external components ED1 and ED2. The custom output data SDC can be recognized by the external components ED1 and ED2.

[0012] It is worth mentioning that the arithmetic circuit 120 receives first data SD1 and obtains the greatest common factor GF of the time lengths TL1~TLn of the multiple voltage states corresponding to the first data SD1. The timer 130 samples the second data SD2 according to the sampling time length TLS stored in the memory circuit 110. The arithmetic circuit 120 generates custom output data SDC based on the multiple voltage states of the sampled second data SD2. In this way, the controller 100 can generate custom output data SDC based on the received first data SD1.

[0013] Furthermore, the custom output data SDC conforms to the data format of external components ED1 and ED2. Therefore, when external components ED1 and ED2 are changed or upgraded, the format of the instructions or data used by external components ED1 and ED2 is changed. The sampling frequency or period may be changed. The sampling frequency of the existing controller may not conform to the sampling frequency of external components ED1 and ED2. The data output by the existing controller cannot be recognized by external components ED1 and ED2. Therefore, when external components ED1 and ED2 are changed or upgraded, the internal logic of the existing controller must be changed. In this embodiment, the controller 100 also changes the sampling time length TLS accordingly to generate the custom output data SDC. The controller 100 can obtain the sampling time length TLS based on the received first data SD1. The control capability of the controller 100 is extended. Therefore, when external components ED1 and ED2 are changed or upgraded, the internal logic of the controller 100 does not need to be changed.

[0014] In this embodiment, the arithmetic circuit 120 may be implemented by at least one of any type of arithmetic logic circuit, decoder, and encoder. The memory circuit 110 may be implemented by any type of memory element capable of storing data.

[0015] Please refer to Figures 1 and 2. Figure 2 is a schematic diagram illustrating the generation of custom output data according to an embodiment of the present invention. In this embodiment, the arithmetic circuit 120 receives first data SD1 and obtains the time lengths TL1 to TL7 of multiple voltage states corresponding to the first data SD1. The arithmetic circuit 120 determines the stages P1 to P7 based on the voltage state transitions. For example, when the voltage state transitions from a low voltage state to a high voltage state, the arithmetic circuit 120 determines the time length TL1 of stage P1 in the low voltage state. Next, when the voltage state transitions from a high voltage state to a low voltage state, the arithmetic circuit 120 determines the time length TL2 of stage P2 in the high voltage state, and so on.

[0016] Therefore, the operational circuit 120 obtains time lengths TL1 to TL7 and obtains the greatest common factor GF of time lengths TL1 to TL7 as the sampling time length TLS. For example, time length TL1 is 5 microseconds. Time length TL2 is 10 microseconds. Time length TL3 is 30 microseconds. Time length TL4 is 15 microseconds. Time length TL5 is 5 microseconds. Time length TL6 is 5 microseconds. Time length TL7 is 20 microseconds. Therefore, the greatest common factor GF is 5 microseconds. The sampling time length TLS is set to 5 microseconds.

[0017] The arithmetic circuit 120 samples the second data SD2 based on the sampling time length TLS to obtain the bit result DB corresponding to the second data SD2. Taking stage P1 as an example, when stage P1 of the second data SD2 is in a low voltage state, the logic value corresponding to the second data SD2 in stage P1 is the first logic value. When stage P1 of the second data SD2 is in a high voltage state, the logic value corresponding to the second data SD2 in stage P1 is the second logic value.

[0018] For example, the first logic value can be a low logic value "0". The second logic value can be a high logic value "1". Therefore, the arithmetic circuit 120 samples the bit value of the second data SD2 based on the sampling time length TLS, as shown in the bit result DB. It should be noted that the number of bits in the bit result DB will change based on the length of the sampling time length TLS. That is, the shorter the sampling time length TLS, the more bits the bit result DB has. The longer the sampling time length TLS, the fewer bits the bit result DB has.

[0019] Next, custom output data SDC can be generated based on the bit result DB. For example, the arithmetic circuit 120 can generate custom output data SDC or notify the external component ED2 to generate custom output data SDC.

[0020] In this embodiment, the arithmetic circuit 120 may include, for example, an arithmetic logic circuit and a decoder (not shown). The arithmetic logic circuit can convert the second data SD2 into a bit result DB based on the one-hot code encoding rules and the sampling time length TLS. The decoder provides the bit result DB to the memory circuit 110.

[0021] Please refer to Figures 1 and 3. Figure 3 is a schematic diagram illustrating the generation of custom output data according to an embodiment of the present invention. In this embodiment, the memory circuit 110 includes memory modules 111 and 112. The number of bits in memory module 111 and memory module 112 is less than the number of bits corresponding to the second data SD2. For example, based on the sampling time length TLS, the number of bits corresponding to the second data SD2 is 18 bits. The number of bits in memory modules 111 and 112 is 8 bits each. Therefore, the arithmetic circuit 120 sequentially stores the first plurality of bits DB1 corresponding to the second data SD2 into memory module 111. When the first plurality of bits DB1 is stored, the capacity of memory module 111 is full. The arithmetic circuit 120 notifies the controller 100 to read the first plurality of bits DB1 stored in memory module 111 and stores the second plurality of bits DB2 corresponding to the second data SD2 into memory module 112.

[0022] When the second plurality of bits DB2 is stored, the capacity of memory 112 is full. The arithmetic circuit 120 notifies the controller 100 to read the second plurality of bits DB2 stored in memory 112 and clear the first plurality of bits DB1 stored in memory 111.

[0023] After clearing the first plurality of bits DB1 stored in memory 111, the arithmetic circuit 120 stores the third plurality of bits DB3 corresponding to the second data SD2 into memory 111. Next, the arithmetic circuit 120 notifies the controller 100 to read the third plurality of bits DB2 stored in memory 111.

[0024] In this embodiment, the first plurality of bits DB1, the second plurality of bits DB2, and the third plurality of bits DB3 are combined to generate custom output data SDC. In this embodiment, the controller 100 can control the decoder (not shown) in the arithmetic circuit 120 to sequentially read the first plurality of bits DB1, the second plurality of bits DB2, and the third plurality of bits DB3, and combine the first plurality of bits DB1, the second plurality of bits DB2, and the third plurality of bits DB3 to generate custom output data SDC. In this embodiment, the controller 100 can also notify the external component ED2 to sequentially read the first plurality of bits DB1, the second plurality of bits DB2, and the third plurality of bits DB3. The external component ED2 combines the first plurality of bits DB1, the second plurality of bits DB2, and the third plurality of bits DB3 to generate custom output data SDC.

[0025] In some embodiments, if the number of bits corresponding to the second data SD2 is less than or equal to 16 bits, the first plurality of bits DB1 and the second plurality of bits DB2 are combined to produce custom output data SDC.

[0026] It is worth mentioning that memories 111 and 112 store the bit result DB in an alternating manner. Memories 111 and 112 are used as ping-pong buffers. Therefore, with limited capacity (e.g., 8 bits), memories 111 and 112 can be used for bit result DBs of any number of bits.

[0027] Please refer to Figures 1 and 4. Figure 4 is a schematic diagram illustrating the generation of custom output data according to an embodiment of the present invention. In this embodiment, the arithmetic circuit 120 receives first data SD1 and obtains the time lengths TL1 to TL6 of multiple voltage states corresponding to the first data SD1. In this embodiment, the arithmetic circuit 120 determines the stages P1 to P6 based on the voltage state transitions. For example, the time length TL1 is 40 microseconds. The time length TL2 is 20 microseconds. The time length TL3 is 10 microseconds. The time length TL4 is 20 microseconds. The time length TL5 is 10 microseconds. The time length TL6 is 10 microseconds. Therefore, the greatest common factor GF is 10 microseconds. The sampling time length TLS is set to 10 microseconds.

[0028] The arithmetic circuit 120 samples the second data SD2 based on the sampling time length TLS to obtain the bit result DB corresponding to the second data SD2. Next, custom output data SDC can be generated based on the bit result DB. For example, the arithmetic circuit 120 can generate custom output data SDC or notify the external component ED2 to generate custom output data SDC.

[0029] The implementation details of the operational circuit 120 have been clearly explained in the various embodiments shown in Figures 2 and 3, and will not be repeated here.

[0030] Please refer to FIG5, which is a schematic diagram of a controller according to an embodiment of the present invention. In this embodiment, the controller 200 includes a memory circuit 210, an arithmetic circuit 220, a timer 230, a transmission circuit 240, and a state machine 250. The transmission circuit 240 is coupled to the arithmetic circuit 220. The transmission circuit 240 receives first data SD1. The arithmetic circuit 220 is coupled to the memory circuit 210. The arithmetic circuit 220 receives the first data SD1 via the transmission circuit 240 and obtains the time lengths TL1~TLn of multiple stages corresponding to multiple voltage states of the first data SD1. The arithmetic circuit 220 obtains the greatest common factor GF of the time lengths TL1~TLn based on the time lengths TL1~TLn as the sampling time length TLS, and stores the sampling time length TLS in the memory circuit 210.

[0031] In this embodiment, state machine 250 is coupled to arithmetic circuit 220. State machine 250 can control arithmetic circuit 220 to perform sampling operations of first data SD1 and second data SD2 to generate one of preset output data SDD and custom output data SDC. State machine 250 can also control data receiving and data output operations of transmission circuit 240.

[0032] The state machine 250 instructs the arithmetic circuit 220 to generate either preset output data SDD or custom output data SDC. The preset output data SDD can be data sampled based on a preset time length TLD. The preset time length TLD is stored in the memory circuit 210.

[0033] The state machine 250 can control the transmission circuit 240 to receive the first data SD1 according to the setting command CMD corresponding to the sampled first data SD1. The state machine 250 can control the transmission circuit 240 to receive the second data SD2 according to the setting command CMD corresponding to the sampled second data SD2.

[0034] State machine 250 instructs arithmetic circuit 220 to generate one of preset output data SDD and custom output data SDC according to setting command CMD. In this embodiment, external component ED2 is operated to provide setting command INS. Memory circuit 210 provides setting command CMD according to setting command INS. State machine 250 instructs arithmetic circuit 220 to generate one of preset output data SDD and custom output data SDC according to setting command CMD. State machine 250 controls transmission circuit 240 to output one of preset output data SDD and custom output data SDC according to setting command CMD.

[0035] When instructed to generate preset output data SDD, timer 230 samples second data SD2 based on preset time length TLD. Therefore, arithmetic circuit 220 generates preset output data SDD based on multiple voltage states of the sampled second data SD2. Arithmetic circuit 220 can send the preset time length TLD stored in memory circuit 210 to timer 230, thereby causing timer 230 to sample second data SD2 based on preset time length TLD.

[0036] When instructed to generate custom output data SDC, timer 230 samples the second data SD2 based on the sampling time length TLS. Therefore, arithmetic circuit 220 generates custom output data SDC based on multiple voltage states of the sampled second data SD2. Arithmetic circuit 220 can send the sampling time length TLS stored in memory circuit 210 to timer 230, thereby causing timer 230 to sample the second data SD2 based on the sampling time length TLS. The implementation details of arithmetic circuit 220 obtaining the sampling time length TLS and generating custom output data SDC have been clearly explained in the various embodiments of Figures 1 to 4, and will not be repeated here.

[0037] In this embodiment, the second data SD2 may be a feedback signal associated with the state of the external component ED1. The preset output data SDD and the custom output data SDC may be sampling results from the second data SD2 of the external component ED1 (e.g., a light-emitting element, a fan, or other controlled element). For example, the state of the external component ED1 may be at least one of operating current, operating voltage, or interrupt notification, but the present invention is not limited thereto.

[0038] In this embodiment, the second data SD2 can be an operation command provided by the external component ED2. For example, the operation command can be at least one of operating current, operating voltage, or interrupt notification, but the invention is not limited thereto. The preset output data SDD and the custom output data SDC can be operation signals used to control the external component ED1.

[0039] It should be noted that when external components ED1 and ED2 are changed or upgraded, the sampling frequency or period may be altered. To prevent sampling errors, the internal logic of the existing controller must also be changed or upgraded accordingly. In this embodiment, the controller 200 can obtain the sampling time length TLS based on the received first data SD1. When external components ED1 and ED2 are changed or upgraded, the internal logic of the controller 200 does not need to be changed. Furthermore, the controller 200 can instruct the arithmetic circuit 220 to generate one of preset output data SDD and custom output data SDC according to the setting command CMD.

[0040] In this embodiment, when the external component ED1 is a light-emitting element, the state machine 250 can also control the color of the output light of the external component ED1 according to the setting command CMD. The state machine 250 can control the transmission circuit 240 to output one of the preset output data SDD and the custom output data SDC according to the setting command CMD corresponding to the color of the output light.

[0041] In this embodiment, the transmission circuit 240 can be implemented using a transmission interface well known to those skilled in the art. The state machine 250 can be implemented using a finite state machine well known to those skilled in the art.

[0042] In summary, the arithmetic circuit receives first data and obtains the greatest common factor of the multiple time lengths of the multiple stages corresponding to the multiple voltage states of the first data. The timer samples the second data according to the sampling time length. The arithmetic circuit generates custom output data based on the multiple voltage states of the sampled second data. In this way, the controller can generate custom output data based on the received data. When external components are changed or upgraded, the internal logic of the controller does not need to be changed.

[0043] Although the present invention has been disclosed above by way of embodiments, it is not intended to limit the present invention. Anyone skilled in the art can make some modifications and refinements without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be determined by the appended claims. [Simplified Explanation of the Diagram]

[0007] Figure 1 is a schematic diagram of a controller according to an embodiment of the present invention. Figure 2 is a schematic diagram of the generation of custom output data according to an embodiment of the present invention. Figure 3 is a schematic diagram of the generation of custom output data according to an embodiment of the present invention. Figure 4 is a schematic diagram of the generation of custom output data according to an embodiment of the present invention. Figure 5 is a schematic diagram of a controller according to an embodiment of the present invention.

Claims

1. A controller, comprising: Memory circuit; A transmission circuit configured to receive first data and second data from at least one external component; An arithmetic circuit, coupled to the memory circuit and the transmission circuit, is configured to receive the first data and the second data via the transmission circuit, obtain multiple time lengths of multiple stages corresponding to multiple voltage states of the first data, obtain the greatest common factor of the multiple time lengths as the sampling time length based on the multiple time lengths, and store the sampling time length in the memory circuit. A timer, coupled to the arithmetic circuit, is configured to sample the second data according to the sampling time length, wherein the arithmetic circuit generates custom output data based on multiple voltage states of the sampled second data.

2. The controller as described in claim 1, wherein: The multiple voltage states of the second data include a high voltage state and a low voltage state. When the first stage of the second data is in the low voltage state, the logic value corresponding to the second data in the first stage is a first logic value, and when the first stage of the second data is in the high voltage state, the logic value corresponding to the second data in the first stage is a second logic value.

3. The controller as described in claim 1, further comprising: A state machine, coupled to the arithmetic circuit, is configured to instruct the arithmetic circuit to generate one of a preset output data and the custom output data.

4. The controller as claimed in claim 3, wherein the state machine instructs the arithmetic circuit to generate one of the preset output data and the custom output data according to a set command.

5. The controller as claimed in claim 3, wherein when instructed to generate the preset output data, the timer samples the second data based on a preset time length, thereby causing the arithmetic circuit to generate the preset output data based on multiple voltage states of the sampled second data.

6. The controller as claimed in claim 3, wherein when instructed to generate the custom output data, the timer samples the second data based on a sampling time length, thereby causing the arithmetic circuitry to generate the custom output data based on multiple voltage states of the sampled second data.

7. The controller as claimed in claim 1, wherein the memory circuitry comprises: First memory; And a second memory, wherein the number of bits in the first memory and the number of bits in the second memory are respectively less than the number of bits corresponding to the second data.

8. The controller as described in claim 7, wherein: The arithmetic circuit stores a first plurality of bits corresponding to the second data into the first memory. When the first plurality of bits are stored, the arithmetic circuit notifies the controller to read the first plurality of bits stored in the first memory and stores a second plurality of bits corresponding to the second data into the second memory. When the second plurality of bits are stored, the arithmetic circuit notifies the controller to read the second plurality of bits stored in the second memory and clear the first plurality of bits stored in the first memory.

9. The controller as claimed in claim 8, wherein after the first plurality of bits stored in the first memory are cleared, the arithmetic circuit stores a third plurality of bits corresponding to the second data into the first memory.

10. The controller as claimed in claim 9, wherein the first plurality of bits, the second plurality of bits, and the third plurality of bits are combined to generate the custom output data.

11. The controller as claimed in claim 7, wherein the number of bits corresponding to the second data is determined by the sampling time length.

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