Memory system

Abstract

A memory system is provided that enhances data transmission processing capabilities. The implemented memory system includes: a memory chip having a first terminal group used for data transmission and reception and a second terminal group used for packet reception; and a memory controller for controlling the memory chip. When performing a single data transmission operation with the memory chip, the memory controller sends a first packet indicating the start of data transmission and a second packet indicating the end of data transmission to the memory chip. When performing two consecutive data transmission operations with the memory chip, the memory controller sends a first packet corresponding to the second data transmission between the first and second data transmissions, but does not send a second packet corresponding to the first data transmission.

Claims

1. A memory system comprising: a memory chip including a first terminal group used for transmitting or receiving data and a second terminal group used for receiving packets, configured to non-volatilely store the data; and a memory controller for controlling the memory chip, configured to transmit or receive the data with the memory chip via the first terminal group and to transmit packets to the memory chip via the second terminal group, wherein when a first data transmission from the memory controller to the memory chip is performed once via the first terminal group within a predetermined period, the memory controller transmits a first packet representing the start of the first data transmission and a second packet representing the end of the first data transmission to the memory chip via the second terminal group. When the second and third data transfers from the memory controller to the memory chip are continuously performed via the first terminal group during the aforementioned pre-set period, the memory controller sends a third packet representing the start of the third data transfer to the memory chip via the second terminal group between the second and third data transfers, and omits the transmission of a fourth packet representing the end of the second data transfer.

2. The memory system as described in claim 1, wherein, The aforementioned memory controller is implemented in parallel via a portion of the transmission of the aforementioned third packet to the aforementioned memory chip via the aforementioned second terminal group and a portion of the aforementioned second data transmission or the aforementioned third data transmission via the aforementioned first terminal group.

3. The memory system as described in claim 1, wherein, Each of the aforementioned third and fourth packets includes a packet header representing the type of information and a packet body representing the content of the information.

4. The memory system as described in claim 3, wherein, The aforementioned types of information include instructions, addresses, or status information.

5. The memory system as described in claim 1, wherein, The aforementioned first terminal group includes a first terminal used in the input / output of the first signal representing the aforementioned data, a second terminal used in the input / output of the select signal of the aforementioned first signal, and a third terminal used in the input of the read enable signal.

6. The memory system as described in claim 5, wherein, The aforementioned second terminal group includes a fourth terminal used in the input / output of the second signal representing the aforementioned first packet and the aforementioned second packet, a fifth terminal used in the transmission of the selected signal of the aforementioned second signal, and a sixth terminal used in the input of the chip enable signal.

7. The memory system as described in claim 6, wherein, The aforementioned memory chip uses the rise and fall of the aforementioned selection signal received via the aforementioned 5th terminal to import the aforementioned 2nd signal received via the aforementioned 4th terminal.

8. The memory system as described in claim 1, wherein, The aforementioned memory chip includes: an input / output circuit connected to the aforementioned first terminal group and configured to input or output the aforementioned data; and a control circuit connected to the aforementioned second terminal group and configured to control the aforementioned memory chip; the aforementioned memory controller includes a memory interface circuit connected to the aforementioned first terminal group and the aforementioned second terminal group.

9. A memory system comprising: a first memory chip and a second memory chip, each including a first terminal group used for transmitting or receiving data and a second terminal group used for receiving packets, configured to non-volatilely store the aforementioned data; and a bridge chip connected to the first terminal group and the second terminal group of the first memory chip via a first channel, and connected to the first terminal group and the second terminal group of the second memory chip via a second channel; and a memory controller connected to the bridge chip, and transmitting or receiving the aforementioned data with the first memory chip or the second memory chip via the bridge chip. When the first data transfer from the memory controller to the bridge chip is performed once within a pre-set period, the memory controller sends a first packet representing the start of the first data transfer and a second packet representing the end of the first data transfer to the bridge chip. When the second and third data transfers from the memory controller to the bridge chip are performed consecutively within the pre-set period, the memory controller sends a third packet representing the start of the third data transfer to the bridge chip between the second and third data transfers, and omits the sending of the fourth packet representing the end of the second data transfer.

10. The memory system as described in claim 9, wherein, The aforementioned memory controller performs the transmission of one portion of the aforementioned third packet of the aforementioned bridging chip and the aforementioned second data transmission or the aforementioned third data transmission in parallel.

11. The memory system as described in claim 9, wherein, When the fourth and fifth data transmissions to the first memory chip are continuously performed within the aforementioned pre-set period, the bridging chip, between the fourth and fifth data transmissions, sends a fifth packet representing the end of the fourth data transmission and a sixth packet representing the start of the fifth data transmission to the first memory chip. The fourth data transmission from the bridging chip to the first memory chip corresponds to the second data transmission from the memory controller to the bridging chip, and the fifth data transmission from the bridging chip to the first memory chip corresponds to the third data transmission from the memory controller to the bridging chip.

12. The memory system as described in claim 9, wherein, The aforementioned bridging chip performs the fourth data transmission portion of the aforementioned first memory chip and the fifth data transmission portion of the aforementioned second memory chip in parallel.

13. The memory system as described in claim 9, wherein, When data is transmitted via the fourth data transmission from the first memory chip to the memory controller via the aforementioned bridging chip, the aforementioned bridging chip transmits a fifth packet representing the start of the transmission of the fourth data before the fourth data transmission.

14. The memory system as described in claim 9, wherein, The data transfer speed between the aforementioned memory controller and the aforementioned bridge chip is faster than the data transfer speed between the aforementioned bridge chip and the aforementioned first memory chip or the aforementioned second memory chip.

15. A memory system comprising: a first memory chip and a second memory chip, each including a first terminal group used for transmitting or receiving data and a second terminal group used for receiving packets, configured to non-volatilely store the aforementioned data; and a bridge chip connected to the first terminal group and the second terminal group of the first memory chip via a first channel, and connected to the first terminal group and the second terminal group of the second memory chip via a second channel; and a memory controller connected to the bridge chip, configured to transmit or receive the aforementioned data with the first memory chip or the second memory chip via the bridge chip. The aforementioned bridging chip is configured to set a threshold data capacity for data transmission between the memory controller and the first memory chip, or between the memory controller and the second memory chip, prior to the bridging chip. The bridging chip includes: a counter for counting the amount of data transmitted in the aforementioned data transmission; a first memory corresponding to the first channel; a second memory corresponding to the second channel; and a switch for selectively connecting one of the first memory and the second memory to the memory controller based on the count of the transmitted data and the threshold data capacity. When the first data transfer from the first memory chip to the memory controller via the aforementioned bridge chip and the second data transfer from the second memory chip to the memory controller via the aforementioned bridge chip are performed continuously, the aforementioned counter is configured such that if the count of the data capacity transferred in the first data transfer reaches the aforementioned threshold data capacity, the aforementioned switch switches the connection between the aforementioned memory controller and the aforementioned memory controller from the aforementioned first memory to the aforementioned second memory. The aforementioned memory controller sends a first packet representing the start of the aforementioned second data transfer to the aforementioned bridge chip during the first data transfer, and omits the sending of a second packet representing the end of the aforementioned first data transfer between the first and second data transfers.

16. The memory system as described in claim 15, wherein, The data transmitted via the aforementioned first data transmission includes a plurality of data frames. The aforementioned memory controller, during the transmission of the last data frame among the plurality of data frames from the aforementioned bridge chip to the aforementioned memory controller, sends the aforementioned first packet to the aforementioned bridge chip to indicate the start of the aforementioned second data transmission.

17. The memory system as described in claim 15, wherein, If the aforementioned bridging chip receives an instruction from the aforementioned memory controller to execute the output action of the aforementioned first data transfer, then the aforementioned bridging chip, before receiving the second packet from the aforementioned memory controller representing the start of the fourth data transfer from the aforementioned bridging chip to the aforementioned memory controller corresponding to the aforementioned output action, first sends to the aforementioned first memory chip the first packet representing the start of the third data transfer from the aforementioned first memory chip to the aforementioned bridging chip corresponding to the aforementioned output action.

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