Display driver integrated circuit structure

Abstract

A display driver integrated circuit structure including a first chip and a second chip is provided. The first chip includes a first semiconductor devices. The first semiconductor devices include a scan driver, a data driver, a gamma adjuster, a power circuit, a one time programmable (OTP) memory, a multiple time programmable (MTP) memory, a digital I / O circuit, an analog I / O circuit, and a power input circuit. The second chip is bonded to the first chip. The second chip includes second semiconductor devices.

Description

Technical Field

[0001] This invention relates to a semiconductor structure, and more particularly to a display driver integrated circuit structure. Prior Technology

[0002] Display driver integrated circuits (DDIs) require the simultaneous use of high-voltage, medium-voltage, and low-voltage components. With the continuous miniaturization of semiconductor components, the difficulty of fabricating high-voltage, medium-voltage, and low-voltage components on a single wafer increases significantly, leading to reduced reliability and increased cost of the DDI structure. Therefore, improving the reliability and reducing the manufacturing cost of DDIs remains a continuous goal. Summary of the Invention

[0003] This invention provides a display driver integrated circuit structure that has high reliability and low manufacturing cost.

[0004] This invention proposes a display driver integrated circuit structure, including a first chip and a second chip. The first chip includes a plurality of first semiconductor elements. These first semiconductor elements include a scan driver, a data driver, a gamma adjuster, a power circuit, one-time programmable (OTP) memory, multiple-time programmable (MTP) memory, a digital I / O circuit, an analog I / O circuit, and a power I / O circuit. The second chip is bonded to the first chip. The second chip includes a plurality of second semiconductor elements.Multiple second semiconductor components include a panel display controller, a power controller, a high-speed interface controller, a high-speed interface receiver, a high-speed interface command decoder, a low-speed interface controller, a low-speed interface receiver, a low-speed interface command decoder, a register read controller, a register write controller, a static random access memory (SRAM) controller, an SRAM bit-cell, an OTP memory controller, an MTP memory controller, an OTP memory bit-cell, an MTP memory bit-cell, a shift register of the scan driver, a shift register of the data driver, and a latch of the scan driver. The scan driver and the latch of the data driver.

[0005] According to an embodiment of the present invention, in the above-described display driver integrated circuit structure, the plurality of first semiconductor elements may further include sensors.

[0006] According to an embodiment of the present invention, in the above-described display driver integrated circuit structure, the plurality of second semiconductor elements may further include at least one of a static random access memory read assistant, a static random access memory write assistant, and a sensor controller.

[0007] According to an embodiment of the present invention, in the above-described display driver integrated circuit structure, a plurality of first semiconductor elements may include high-voltage elements, medium-voltage elements, or combinations thereof.

[0008] According to an embodiment of the present invention, in the above-described display driver integrated circuit structure, the plurality of second semiconductor elements may include a plurality of low-voltage elements.

[0009] According to an embodiment of the present invention, in the above-described display driver integrated circuit structure, the breakdown voltage of a plurality of first semiconductor elements may be higher than the breakdown voltage of a plurality of second semiconductor elements.

[0010] According to an embodiment of the present invention, in the above-described display driver integrated circuit structure, the minimum pitch of a plurality of first semiconductor elements may be greater than the minimum pitch of a plurality of second semiconductor elements.

[0011] According to one embodiment of the present invention, in the above-described display driver integrated circuit structure, the second chip can be hybrid-bonded to the first chip.

[0012] According to one embodiment of the present invention, in the above-described display driver integrated circuit structure, the second wafer can be fusion-bonded to the first wafer.

[0013] According to an embodiment of the present invention, in the above-described display driver integrated circuit structure, the first chip and the second chip can be stacked face-to-back.

[0014] According to an embodiment of the present invention, in the above-described display driver integrated circuit structure, the first chip and the second chip can be stacked face-to-face.

[0015] According to one embodiment of the present invention, in the above-described display driver integrated circuit structure, the first chip and the second chip can be stacked back-to-back.

[0016] Based on the above, the integrated circuit structure of the display driver proposed in this invention includes a first chip and a second chip. The first chip includes a plurality of first semiconductor elements. The plurality of first semiconductor elements include a scan driver, a data driver, a gamma regulator, a power supply circuit, a one-time programmable memory (IPM), a multiple-time programmable memory (MPM), a digital input / output circuit, an analog input / output circuit, and a power input / output circuit. The second chip is bonded to the first chip. The second chip includes a plurality of second semiconductor elements. The plurality of second semiconductor elements include a panel display controller, a power controller, a high-speed interface controller, a high-speed interface receiver, a high-speed interface command decoder, a low-speed interface controller, a low-speed interface receiver, a low-speed interface command decoder, a register read controller, a register write controller, a static random access memory (SRAM) controller, a SRAM bit cell, an IPM controller, a MPM controller, an MPM bit cell, an MPM bit cell, an MPM bit cell, a shift register for the scan driver, a shift register for the data driver, a latch for the scan driver, and a latch for the data driver. Therefore, scan drivers, data drivers, gamma regulators, power supply circuits, one-time programmable memory, multiple-time programmable memory, digital input / output circuits, analog input / output circuits, and power input / output circuits with the same or similar minimum pitch can be located on the same first chip. Furthermore, panel display controllers, power controllers, high-speed interface controllers, high-speed interface receivers, high-speed interface command decoders, low-speed interface controllers, low-speed interface receivers, low-speed interface command decoders, register read controllers, register write controllers, static random access memory controllers, static random access memory bit units, one-time programmable memory controllers, multiple-time programmable memory controllers, one-time programmable memory bit units, multiple-time programmable memory bit units, shift registers for scan drivers, shift registers for data drivers, latches for scan drivers, and latches for data drivers with the same or similar minimum pitch can be located on the same second chip. This reduces the manufacturing complexity of both the first and second wafers, thereby improving the reliability of the display driver integrated circuit structure and reducing its manufacturing cost. Furthermore, it reduces the size of the display driver integrated circuit structure, thus reducing the space required to mount it onto electronic devices (such as displays or smartphones).

[0017] To make the above features and advantages of the present invention more apparent and understandable, specific embodiments are described below in conjunction with the accompanying drawings for detailed explanation. Simple Explanation of the Diagram

[0018] Figure 1 is a schematic diagram of the integrated circuit structure of a display driver according to some embodiments of the present invention. Figure 2 is a schematic diagram of an electronic device according to some embodiments of the present invention. Implementation

[0019] The following description provides detailed examples and accompanying drawings, but these examples are not intended to limit the scope of the invention. For ease of understanding, the same components will be designated with the same symbols in the following description. Furthermore, the drawings are for illustrative purposes only and are not drawn to their original dimensions. In fact, the dimensions of various features may be arbitrarily increased or decreased for clarity of explanation.

[0020] Figure 1 is a schematic diagram of a display driver integrated circuit structure according to some embodiments of the present invention. Figure 2 is a schematic diagram of an electronic device according to some embodiments of the present invention.

[0021] Referring to Figure 1, the display driver integrated circuit structure 10 includes a chip 100 and a chip 200. The display driver integrated circuit structure 10 can be applied to electronic devices (such as displays or smartphones).

[0022] The chip 100 includes a plurality of semiconductor elements 102. The plurality of semiconductor elements 102 include a scan driver, a data driver, a gamma regulator, a power supply circuit, a one-time programmable memory, a multiple-time programmable memory, a digital input / output circuit, an analog input / output circuit, and a power input / output circuit. In some embodiments, the plurality of semiconductor elements 102 may further include a sensor. Furthermore, the number of semiconductor elements 102 shown in FIG1 is merely illustrative and is not intended to limit the invention.

[0023] Chip 200 is bonded to chip 100. Herein, chip 200 is electrically connected to chip 100, and semiconductor element 202 is electrically connected to semiconductor element 102. In some embodiments, semiconductor element 102 and semiconductor element 202 may be electrically connected to each other via conductive components such as interconnect structures, through-silicon vias (TSVs), and / or pads. In some embodiments, chip 200 may be co-bonded to chip 100. In some embodiments, chip 200 may be fused bonded to chip 100. In some embodiments, chip 100 and chip 200 may be stacked face-to-back. In some embodiments, chip 100 and chip 200 may be stacked face-to-face. In some embodiments, chip 100 and chip 200 may be stacked back-to-back. Furthermore, the number of semiconductor elements 202 in FIG. 1 is merely illustrative and is not intended to limit the invention.

[0024] The chip 200 includes a plurality of semiconductor elements 202. The plurality of semiconductor elements 202 include a panel display controller, a power controller, a high-speed interface controller, a high-speed interface receiver, a high-speed interface command decoder, a low-speed interface controller, a low-speed interface receiver, a low-speed interface command decoder, a register read controller, a register write controller, a static random access memory (SRAM) controller, a SRAM bit cell, a once-programmable memory (UPN) controller, a multiple-programmable memory (MPM) controller, a once-programmable memory bit cell, a multiple-programmable memory (MPM) bit cell, a shift register for a scan driver, a shift register for a data driver, a latch for a scan driver, and a latch for a data driver. In some embodiments, the plurality of semiconductor elements 202 may further include at least one of a SRAM read assist, a SRAM write assist, and a sensor controller.

[0025] In some embodiments, the plurality of semiconductor elements 102 may include high-voltage elements, medium-voltage elements, or combinations thereof. In some embodiments, the plurality of semiconductor elements 202 may include a plurality of low-voltage elements. In some embodiments, the breakdown voltage of the plurality of semiconductor elements 102 may be higher than the breakdown voltage of the plurality of semiconductor elements 202. In some embodiments, the minimum pitch of the plurality of semiconductor elements 102 may be greater than the minimum spacing of the plurality of semiconductor elements 202. In this embodiment, the pitch may be defined as the sum of the line width and the line spacing.

[0026] In some embodiments, the display driver integrated circuit structure 10 can be applied to an electronic device 20. In some embodiments, the electronic device 20 is, for example, a display or a smartphone, but the present invention is not limited thereto. In this embodiment, the electronic device 20 is described using a smartphone as an example. As shown in FIG2, the electronic device 20 may include the display driver integrated circuit structure 10 and a panel 12. The display driver integrated circuit structure 10 may be electrically connected to the panel 12. In some embodiments, the panel 12 is, for example, an organic light emitting diode (OLED) panel or a liquid crystal display (LCD) panel.

[0027] As described in the above embodiments, the display driver integrated circuit structure 10 includes a chip 100 and a chip 200. The chip 100 includes a plurality of semiconductor elements 102. The plurality of semiconductor elements 102 include a scan driver, a data driver, a gamma regulator, a power supply circuit, a one-time programmable memory, a multiple-time programmable memory, a digital input / output circuit, an analog input / output circuit, and a power input / output circuit. The chip 200 is bonded to the chip 100. The chip 200 includes a plurality of semiconductor elements 202. Multiple semiconductor components 202 include a panel display controller, a power controller, a high-speed interface controller, a high-speed interface receiver, a high-speed interface command decoder, a low-speed interface controller, a low-speed interface receiver, a low-speed interface command decoder, a register read controller, a register write controller, a static random access memory controller, a static random access memory bit cell, a one-time programmable memory controller, a multiple-time programmable memory controller, a one-time programmable memory bit cell, a multiple-time programmable memory bit cell, a shift register for a scan driver, a shift register for a data driver, a latch for a scan driver, and a latch for a data driver. Therefore, scan drivers, data drivers, gamma regulators, power supply circuits, one-time programmable memory, multiple-time programmable memory, digital input / output circuits, analog input / output circuits, and power input / output circuits with the same or similar minimum spacing can be located on the same chip 100. Furthermore, panel display controllers, power controllers, high-speed interface controllers, high-speed interface receivers, high-speed interface command decoders, low-speed interface controllers, low-speed interface receivers, low-speed interface command decoders, register read controllers, register write controllers, static random access memory controllers, static random access memory bit units, one-time programmable memory controllers, multiple-time programmable memory controllers, one-time programmable memory bit units, multiple-time programmable memory bit units, shift registers for scan drivers, shift registers for data drivers, and latches for scan drivers and data drivers can be located on the same chip 200. This reduces the process complexity of both chip 100 and chip 200, thereby improving the reliability of the display driver integrated circuit structure 10 and reducing its manufacturing cost. Furthermore, the size of the display driver integrated circuit structure 10 can be reduced, thereby reducing the space required to mount the display driver integrated circuit structure 10 to the electronic device 20 (e.g., a display or smartphone). For example, as shown in FIG2, the size of the display driver integrated circuit structure 10 along the Y-axis can be reduced, thereby reducing the space required to mount the display driver integrated circuit structure 10 to the electronic device 20. Additionally, the X-axis direction can be the direction of extension of the electronic device 20 in width, and the Y-axis direction can be the direction of extension of the electronic device 20 in length.

[0028] In summary, the integrated circuit structure of the display driver in the above embodiments includes a first chip and a second chip. The first chip includes a plurality of first semiconductor elements. The plurality of first semiconductor elements includes a scan driver, a data driver, a gamma regulator, a power supply circuit, a one-time programmable memory (IPM), a multiple-time programmable memory (MPM), a digital input / output circuit, an analog input / output circuit, and a power input / output circuit. The second chip is bonded to the first chip. The second chip includes a plurality of second semiconductor elements. The plurality of second semiconductor elements includes a panel display controller, a power controller, a high-speed interface controller, a high-speed interface receiver, a high-speed interface command decoder, a low-speed interface controller, a low-speed interface receiver, a low-speed interface command decoder, a register read controller, a register write controller, a static random access memory (SRAM) controller, a SRAM bit cell, an IPM controller, a MPM controller, an MPM bit cell, an MPM bit cell, an MPM bit cell, a shift register for the scan driver, a shift register for the data driver, a latch for the scan driver, and a latch for the data driver. Therefore, scan drivers, data drivers, gamma regulators, power supply circuits, one-time programmable memory, multiple-time programmable memory, digital input / output circuits, analog input / output circuits, and power input / output circuits with the same or similar minimum pitch can be located on the same first chip. Furthermore, panel display controllers, power controllers, high-speed interface controllers, high-speed interface receivers, high-speed interface command decoders, low-speed interface controllers, low-speed interface receivers, low-speed interface command decoders, register read controllers, register write controllers, static random access memory controllers, static random access memory bit units, one-time programmable memory controllers, multiple-time programmable memory controllers, one-time programmable memory bit units, multiple-time programmable memory bit units, shift registers for scan drivers, shift registers for data drivers, latches for scan drivers, and latches for data drivers with the same or similar minimum pitch can be located on the same second chip. This reduces the manufacturing complexity of both the first and second wafers, thereby improving the reliability of the display driver integrated circuit structure and reducing its manufacturing cost. Furthermore, it reduces the size of the display driver integrated circuit structure, thus reducing the space required to mount it onto electronic devices (such as displays or smartphones).

[0029] Although the present invention has been disclosed above by way of embodiments, it is not intended to limit the present invention. Anyone skilled in the art can make some modifications and refinements without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be determined by the appended claims.

[0030] 10: Display driver integrated circuit structure 12: Panel 20: Electronic devices 100, 200: Chips 102,202: Semiconductor components X, Y: Axes

Claims

1. A display driver integrated circuit structure, comprising: A first chip includes a plurality of first semiconductor elements, wherein the plurality of first semiconductor elements include a scan driver, a data driver, a gamma regulator, a power supply circuit, a single-programmable memory (SPMC), a multiple-programmable memory (MPCM), a digital input / output circuit, an analog input / output circuit, and a power input / output circuit; and a second chip, coupled to the first chip, includes a plurality of second semiconductor elements, wherein the plurality of second semiconductor elements include a panel display controller, a power controller, a high-speed interface controller, a high-speed interface receiver, a high-speed interface command decoder, a low-speed interface controller, a low-speed interface receiver, a low-speed interface command decoder, a register read controller, a register write controller, a static random access memory (SRAM) controller, a SRAM bit cell, a single-programmable memory controller, a multiple-programmable memory controller, a single-programmable memory bit cell, a multiple-programmable memory bit cell, a shift register of the scan driver, a shift register of the data driver, a latch of the scan driver, and a latch of the data driver, and the minimum spacing between the plurality of first semiconductor elements is greater than the minimum spacing between the plurality of second semiconductor elements.

2. The display driver integrated circuit structure as claimed in claim 1, wherein the plurality of the first semiconductor elements further include a sensor.

3. The display driver integrated circuit structure as claimed in claim 1, wherein the plurality of second semiconductor elements further includes at least one of a static random access memory read assist, a static random access memory write assist, and a sensor controller.

4. The display driver integrated circuit structure as claimed in claim 1, wherein the plurality of first semiconductor elements include high-voltage elements, medium-voltage elements, or combinations thereof.

5. The display driver integrated circuit structure as claimed in claim 4, wherein the plurality of second semiconductor elements include a plurality of low-voltage elements.

6. The display driver integrated circuit structure as claimed in claim 1, wherein the breakdown voltage of the plurality of first semiconductor elements is higher than the breakdown voltage of the plurality of second semiconductor elements.

7. The display driver integrated circuit structure as claimed in claim 1, wherein the second wafer is co-bonded to the first wafer.

8. The display driver integrated circuit structure as claimed in claim 1, wherein the second wafer is fused to the first wafer.

9. The display driver integrated circuit structure as claimed in claim 1, wherein the first wafer and the second wafer are stacked face-to-back.

10. The display driver integrated circuit structure as claimed in claim 1, wherein the first wafer and the second wafer are stacked face-to-face.

11. The display driver integrated circuit structure as claimed in claim 1, wherein the first wafer and the second wafer are stacked back to back.

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