Memory structure
Patent Information
- Application Number
- TW114106674
- Authority / Receiving Office
- TW · TW
- Patent Type
- Applications
- Current Assignee / Owner
- Filing Date
- 2025-02-24
- Publication Date
- 2026-09-01
- Estimated Expiration
- 2045-02-23
AI Technical Summary
Existing memory components face challenges in effectively reducing the area of memory cells as they continue to miniaturize.
A memory structure is designed with specific configurations, including a substrate with opposing surfaces, word line structures, bit line structures, and capacitor structures, where certain components are located on different surfaces to minimize area and maximize capacitance.
The proposed structure effectively reduces the memory cell area and increases the capacitance of capacitors, optimizing space utilization and performance.
Smart Images
Figure TWG2TA001073893_001 
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Abstract
Description
Technical Field
[0001] This invention relates to a semiconductor structure, and more particularly to a memory structure. Prior Technology
[0002] Memory components are widely used in electronic products. However, with the continuous miniaturization of memory components, effectively reducing the area of memory cells remains a continuous goal. Summary of the Invention
[0003] This invention provides a memory structure that can effectively reduce the area of memory cells.
[0004] This invention proposes a memory structure, including a substrate, a first word line structure, a second word line structure, a bit line structure, a first contact window structure, a first capacitor structure, a second contact window structure, and a second capacitor structure. The substrate includes a first surface and a second surface opposite to each other. The first word line structure and the second word line structure are located within the substrate. The bit line structure is located on the first surface and between the first word line structure and the second word line structure. The first contact window structure is located on the first surface and to one side of the bit line structure. The first capacitor structure is located on the first surface and on the first contact window structure. The second contact window structure is located on the second surface. The second capacitor structure is located on the second surface and on the second contact window structure.
[0005] According to an embodiment of the present invention, in the above memory structure, the first character line structure and the second character line structure are electrically insulated from the substrate.
[0006] According to an embodiment of the present invention, in the above memory structure, the first character line structure may be located between the bit line structure and the first contact window structure.
[0007] According to an embodiment of the present invention, in the above memory structure, the first character line structure and the second character line structure can extend from the first surface to the second surface.
[0008] According to an embodiment of the present invention, in the above memory structure, the depth of the second character line structure can be greater than the depth of the first character line structure.
[0009] According to one embodiment of the present invention, in the above memory structure, the bit line structure can be connected to the substrate.
[0010] According to one embodiment of the present invention, in the above-described memory structure, the bit line structure may include bit lines and contact windows. The bit lines are located on the substrate. The contact windows are located between the bit lines and the substrate.
[0011] According to an embodiment of the present invention, in the above memory structure, the first contact window structure can be connected to the substrate.
[0012] According to an embodiment of the present invention, in the above-described memory structure, the first contact window structure may include a first contact window, a second contact window, and a barrier layer. The first contact window is connected to the substrate. The second contact window is located on the first contact window. The barrier layer is located between the first contact window and the second contact window.
[0013] According to an embodiment of the present invention, in the above memory structure, the first capacitor structure is electrically connected to the first contact window structure.
[0014] According to an embodiment of the present invention, in the above-described memory structure, the first capacitor structure may include a first electrode layer, a second electrode layer, and a dielectric layer. The first electrode layer is electrically connected to a first contact window structure. The second electrode layer is located on the first electrode layer. The dielectric layer is located between the first electrode layer and the second electrode layer.
[0015] According to one embodiment of the present invention, in the above memory structure, the second contact window structure can be connected to the substrate.
[0016] According to one embodiment of the present invention, in the above-described memory structure, the second contact window structure may extend into the substrate.
[0017] According to an embodiment of the present invention, in the above memory structure, the top view of the second contact window structure can be superimposed on the top view of the second character line structure.
[0018] According to an embodiment of the present invention, in the above-described memory structure, the second contact window structure may include a first contact window, a second contact window, and a barrier layer. The first contact window is connected to the substrate. The second contact window is located on the first contact window. The barrier layer is located between the first contact window and the second contact window.
[0019] According to one embodiment of the present invention, in the above memory structure, the second capacitor structure can be electrically connected to the second contact window structure.
[0020] According to an embodiment of the present invention, in the above-described memory structure, the second capacitor structure may include a first electrode layer, a second electrode layer, and a dielectric layer. The first electrode layer is electrically connected to the second contact window structure. The second electrode layer is located on the first electrode layer. The dielectric layer is located between the first electrode layer and the second electrode layer.
[0021] According to one embodiment of the present invention, the memory structure described above may further include a first dielectric structure and a second dielectric structure. The first dielectric structure and the second dielectric structure are located in a substrate. The first word line structure may be located in the first dielectric structure. The second word line structure may be located in the second dielectric structure.
[0022] According to an embodiment of the present invention, in the above-described memory structure, the first dielectric structure and the second dielectric structure can extend from the first surface to the second surface.
[0023] According to one embodiment of the present invention, in the above memory structure, the depth of the second dielectric structure may be greater than the depth of the first dielectric structure.
[0024] Based on the above, in the memory structure proposed in this invention, since the first contact window structure and the first capacitor structure are located on the first surface, and the second contact window structure and the second capacitor structure are located on the second surface, the area of the memory cell can be effectively reduced. Furthermore, since the first capacitor structure and the second capacitor structure are located on the first and second surfaces respectively, the area of the first capacitor structure and the area of the second capacitor structure can be maximized, thereby increasing the capacitance of the first capacitor structure and the capacitance of the second capacitor structure.
[0025] To make the above features and advantages of the present invention more apparent and understandable, specific embodiments are described below in conjunction with the accompanying drawings for detailed explanation. Simple Explanation of the Diagram
[0026] Figure 1 is a top view of a memory structure according to some embodiments of the present invention. Figures 2A to 2F are cross-sectional views of the manufacturing process of the memory structure along the I-I' section line in Figure 1. Implementation
[0027] The following description provides detailed examples and accompanying drawings, but these examples are not intended to limit the scope of the invention. For ease of understanding, the same components will be designated with the same symbols in the following description. Furthermore, the drawings are for illustrative purposes only and are not drawn to scale. Additionally, features in the top view and sectional views are not drawn to the same scale. In fact, for clarity of explanation, the dimensions of various features can be arbitrarily increased or decreased.
[0028] Figure 1 is a top view of a memory structure according to some embodiments of the present invention. Figures 2A to 2F are cross-sectional views of the manufacturing process of the memory structure along section line I-I' in Figure 1. In Figure 1, some components in Figures 2A to 2F are omitted to clearly illustrate the arrangement relationship between the components in Figure 1.
[0029] Referring to Figures 1 and 2A, a substrate 100 is provided. The substrate 100 includes a first surface S1 and a second surface S2 opposite to each other. In some embodiments, the first surface S1 may be the front side of the substrate 100, and the second surface S2 may be the back side of the substrate 100. In some embodiments, the substrate 100 may be a semiconductor substrate, such as a silicon substrate. In some embodiments, the substrate 100 may have desired doped regions (not shown), the description of which is omitted here.
[0030] Next, dielectric structures 102A and 102B can be formed in the substrate 100. Dielectric structure 102B can define an active region AA in the substrate 100. In some embodiments, dielectric structures 102A and 102B can extend from a first surface S1 to a second surface S2. In some embodiments, the depth D2 of dielectric structure 102B can be greater than the depth D1 of dielectric structure 102A. In some embodiments, dielectric structures 102A and 102B can be shallow trench isolation structures. In some embodiments, the materials of dielectric structures 102A and 102B are, for example, silicon oxide.
[0031] Referring to Figures 1 and 2B, a character line structure 104A can be formed in dielectric structure 102A, and a character line structure 104B can be formed in dielectric structure 102B. Thus, character line structures 104A and 104B can be formed in substrate 100. Character line structures 104A and 104B are electrically insulated from substrate 100. For example, character line structure 104A can be electrically insulated from substrate 100 by dielectric structure 102A, and character line structure 104B can be electrically insulated from substrate 100 by dielectric structure 102B. In some embodiments, character line structures 104A and 104B can extend from a first surface S1 to a second surface S2. In some embodiments, the depth D4 of character line structure 104B can be greater than the depth D3 of character line structure 104A. In some embodiments, the top view of the character line structure 104B does not overlap with the top view of the active area AA.
[0032] In some embodiments, the character line structure 104A may include a character line 106A. The character line 106A is located within the dielectric structure 102A. In some embodiments, the character line structure 104A may further include a barrier layer 108A. The barrier layer 108A is located between the character line 106A and the dielectric structure 102A. In some embodiments, the material of the character line 106A is, for example, tungsten. In some embodiments, the material of the barrier layer 108A is, for example, titanium, titanium nitride, or a combination thereof.
[0033] In some embodiments, the character line structure 104B may include a character line 106B. The character line 106B is located within the dielectric structure 102B. In some embodiments, the character line structure 104B may further include a barrier layer 108B. The barrier layer 108B is located between the character line 106B and the dielectric structure 102B. In some embodiments, the material of the character line 106B is, for example, tungsten. In some embodiments, the material of the barrier layer 108B is, for example, titanium, titanium nitride, or a combination thereof.
[0034] Next, a capping layer 110 can be formed on the substrate 100, dielectric structure 102A, dielectric structure 102B, word line structure 104A, and word line structure 104B. In some embodiments, the material of the capping layer 110 is, for example, silicon nitride.
[0035] Referring to Figures 1 and 2C, a contact window 112 can be formed in the top cover layer 110. The contact window 112 can be connected to the substrate 100. In some embodiments, the material of the contact window 112 is, for example, doped polycrystalline silicon. Next, a bit line 114 can be formed on the contact window 112. In some embodiments, the material of the bit line 114 is, for example, tungsten. By the above method, a bit line structure 116 can be formed on the first surface S1. The bit line structure 116 is located on the first surface S1 and between the word line structure 104A and the word line structure 104B. The bit line structure 116 may include the bit line 114 and the contact window 112. The bit line structure 116 can be connected to the substrate 100. The bit line 114 is located on the substrate 100. The contact window 112 is located between the bit line 114 and the substrate 100. The contact window 112 can be connected to the substrate 100.
[0036] Next, a dielectric layer 118 may be formed on the top cap layer 110 and the bit line structure 116. In some embodiments, the material of the dielectric layer 118 is, for example, silicon nitride.
[0037] Referring to Figures 1 and 2D, a contact window structure 120 can be formed in the dielectric layer 118 and the capping layer 110. This allows the contact window structure 120 to be formed on the first surface S1. The contact window structure 120 is located on one side of the bit line structure 116. The contact window structure 120 can be connected to the substrate 100. Furthermore, the word line structure 104A can be located between the bit line structure 116 and the contact window structure 120. In some embodiments, the contact window structure 120 may include a contact window 122, a contact window 124, and a barrier layer 126. The contact window 122 can be connected to the substrate 100. In some embodiments, the material of the contact window 122 is, for example, doped polycrystalline silicon. The contact window 124 is located on the contact window 122. In some embodiments, the material of the contact window 124 is, for example, tungsten. The barrier layer 126 is located between the contact window 122 and the contact window 124, and may be located between the contact window 124 and the dielectric layer 118. In some embodiments, the material of the barrier layer 126 is, for example, titanium, titanium nitride, or a combination thereof.
[0038] Next, a capacitor structure 128 may be formed on the first surface S1. The capacitor structure 128 is located on the contact window structure 120. The capacitor structure 128 is electrically connected to the contact window structure 120. In some embodiments, the capacitor structure 128 may include an electrode layer 130, an electrode layer 132, and a dielectric layer 134. The electrode layer 130 is electrically connected to the contact window structure 120. In some embodiments, the material of the electrode layer 130 is, for example, titanium, titanium nitride, or a combination thereof. The electrode layer 132 is located on the electrode layer 130. In some embodiments, the material of the electrode layer 132 is, for example, titanium, titanium nitride, or a combination thereof. The dielectric layer 134 is located between the electrode layer 130 and the electrode layer 132. In some embodiments, the material of the dielectric layer 134 is, for example, a high dielectric constant material.
[0039] Then, a dielectric layer 136 may be formed on the dielectric layer 118 and the capacitor structure 128. In some embodiments, the material of the dielectric layer 136 is, for example, silicon oxide.
[0040] Referring to Figure 2E, the dielectric layer 136 can be bonded to the carrier substrate 200. Then, a thinning process can be performed on the second surface S2 of the substrate 100 to reduce the thickness of the substrate 100.
[0041] Referring to Figures 1 and 2F, a dielectric layer 138 can be formed on the second surface S2 and in the substrate 100. The dielectric layer 138 can be a single-layer structure or a multi-layer structure. Next, a contact window structure 140 can be formed in the dielectric layer 138. This allows the contact window structure 140 to be formed on the second surface S2. The contact window structure 140 can be connected to the substrate 100. In some embodiments, the contact window structure 140 can extend into the substrate 100. In some embodiments, the top view of the contact window structure 140 can overlap with the top view of the character line structure 104B. In some embodiments, the contact window structure 140 may include a contact window 142, a contact window 144, and a barrier layer 146. The contact window 142 is connected to the substrate 100. The contact window 142 can be located in the substrate 100. In some embodiments, the material of the contact window 142 is, for example, doped polycrystalline silicon. The contact window 144 is located on the contact window 142. In some embodiments, the material of the contact window 144 is, for example, tungsten. The barrier layer 146 is located between the contact window 142 and the contact window 144, and may be located between the contact window 144 and the dielectric layer 138. In some embodiments, the material of the barrier layer 146 is, for example, titanium, titanium nitride, or a combination thereof.
[0042] Next, a capacitor structure 148 can be formed on the second surface S2. The capacitor structure 148 is located on the contact window structure 140. The capacitor structure 148 is electrically connected to the contact window structure 140. In some embodiments, the capacitor structure 148 may include an electrode layer 150, an electrode layer 152, and a dielectric layer 154. The electrode layer 150 is electrically connected to the contact window structure 140. In some embodiments, the material of the electrode layer 150 is, for example, titanium, titanium nitride, or a combination thereof. The electrode layer 152 is located on the electrode layer 150. In some embodiments, the material of the electrode layer 152 is, for example, titanium, titanium nitride, or a combination thereof. The dielectric layer 154 is located between the electrode layer 150 and the electrode layer 152. In some embodiments, the material of the dielectric layer 154 is, for example, a high dielectric constant material.
[0043] Then, a dielectric layer 156 can be formed on the dielectric layer 138 and the capacitor structure 148. In some embodiments, the material of the dielectric layer 156 is, for example, silicon oxide. Furthermore, the carrier substrate 200 can be removed.
[0044] The memory structure 10 of the above embodiment will be described below with reference to FIG1 and FIG2F. Furthermore, although the method for forming the memory structure 10 is described using the above method as an example, the present invention is not limited thereto.
[0045] Referring to Figures 1 and 2F, the memory structure 10 includes a substrate 100, word line structures 104A and 104B, a bit line structure 116, a contact window structure 120, a capacitor structure 128, a contact window structure 140, and a capacitor structure 148. The memory structure 10 is applicable to wafer-on-wafer (WoW) and through-substrate via (TSV) processes. The substrate 100 includes a first surface S1 and a second surface S2 opposite to each other. Word line structures 104A and 104B are located within the substrate 100. The bit line structure 116 is located on the first surface S1 and between word line structures 104A and 104B. The contact window structure 120 is located on the first surface S1 and to one side of the bit line structure 116. The capacitor structure 128 is located on the first surface S1 and on the contact window structure 120. Contact window structure 140 is located on the second surface S2. Capacitor structure 148 is located on the second surface S2 and on contact window structure 140. Furthermore, memory structure 10 may further include dielectric structure 102A and dielectric structure 102B. Dielectric structure 102A and dielectric structure 102B are located in substrate 100. Word line structure 104A may be located in dielectric structure 102A. Word line structure 104B may be located in dielectric structure 102B.
[0046] Furthermore, the remaining components in the memory structure 10 can be described with reference to the above embodiments. In addition, the details of each component in the memory structure 10 (e.g., materials and forming methods) have been described in detail in the above embodiments, and will not be described again here.
[0047] As can be seen from the above embodiments, in the memory structure 10 proposed in this invention, since the contact window structure 120 and the capacitor structure 128 are located on the first surface S1, and the contact window structure 140 and the capacitor structure 148 are located on the second surface S2, the area of the memory cell can be effectively reduced. Furthermore, since the capacitor structure 128 and the second capacitor structure 148 are located on the first surface S1 and the second surface S2 respectively, the area of the capacitor structure 128 and the area of the second capacitor structure 148 can be maximized, thereby increasing the capacitance of the capacitor structure 128 and the capacitance of the capacitor structure 148.
[0048] In summary, the memory structure of the above embodiments includes a substrate, a first word line structure, a second word line structure, a bit line structure, a first contact window structure, a first capacitor structure, a second contact window structure, and a second capacitor structure. The substrate includes a first surface and a second surface opposite to each other. The first word line structure and the second word line structure are located within the substrate. The bit line structure is located on the first surface and between the first word line structure and the second word line structure. The first contact window structure is located on the first surface and on one side of the bit line structure. The first capacitor structure is located on the first surface and on the first contact window structure. The second contact window structure is located on the second surface. The second capacitor structure is located on the second surface and on the second contact window structure. Therefore, the area of the memory cell can be effectively reduced. Furthermore, the area of the first capacitor structure and the area of the second capacitor structure can be maximized, thereby increasing the capacitance of the first capacitor structure and the capacitance of the second capacitor structure.
[0049] Although the present invention has been disclosed above by way of embodiments, it is not intended to limit the present invention. Anyone skilled in the art can make some modifications and refinements without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be determined by the appended claims.
[0050] 10: Memory Structure 100: Base 102A, 102B: Dielectric structure 104A, 104B: Character line structure 106A, 106B: Character lines 108A, 108B: Barrier Layer 110: Top Cover Layer 112, 122, 124, 142, 144: Contact window 114: Bitline 116: Bitline Structure 118, 134, 136, 138, 154, 156: Dielectric layers 120, 140: Contact window structure 126, 146: Barrier Layer 128, 148: Capacitor Structure 130, 132, 150, 152: Electrode layers 200: Supporting substrate AA: Active Zone D1, D2, D3, D4: Depth S1: First Page S2: Second side
Claims
1. A memory structure, comprising: The base consists of a first surface and a second surface that are opposite to each other; The first character line structure and the second character line structure are located in the substrate; A bit line structure is located on the first surface and between the first bit line structure and the second bit line structure; a first contact window structure is located on the first surface and on one side of the bit line structure; a first capacitor structure is located on the first surface and on the first contact window structure; a second contact window structure is located on the second surface. And a second capacitor structure, located on the second surface and on the second contact window structure, wherein the first character line structure and the second character line structure extend from the first surface to the second surface.
2. The memory structure as claimed in claim 1, wherein the first character line structure and the second character line structure are electrically insulated from the substrate.
3. The memory structure as claimed in claim 1, wherein the projection of the first character line structure onto the first surface is located between the projection of the bit line structure onto the first surface and the projection of the first contact window structure onto the first surface.
4. The memory structure as described in claim 1, wherein the depth of the second character line structure is greater than the depth of the first character line structure.
5. The memory structure as described in claim 1, wherein the bit line structure is connected to the substrate.
6. The memory structure as described in claim 1, wherein the bit line structure includes: Bit lines are located on the substrate; And a contact window, located between the bit line and the substrate.
7. The memory structure as claimed in claim 1, wherein the first contact window structure is connected to the substrate.
8. The memory structure as claimed in claim 1, wherein the first contact window structure comprises: The first contact window is connected to the substrate; The second contact window is located on top of the first contact window; And a barrier layer, located between the first contact window and the second contact window.
9. The memory structure as claimed in claim 1, wherein the first capacitor structure is electrically connected to the first contact window structure.
10. The memory structure as claimed in claim 1, wherein the first capacitor structure comprises: The first electrode layer is electrically connected to the first contact window structure; The second electrode layer is located on the first electrode layer; And a dielectric layer, located between the first electrode layer and the second electrode layer.
11. The memory structure as claimed in claim 1, wherein the second contact window structure is connected to the substrate.
12. The memory structure as claimed in claim 1, wherein the second contact window structure extends into the substrate.
13. The memory structure as claimed in claim 1, wherein the top view of the second contact window structure overlaps the top view of the second character line structure.
14. The memory structure as claimed in claim 1, wherein the second contact window structure comprises: A first contact window is connected to the substrate; The second contact window is located on top of the first contact window; And a barrier layer, located between the first contact window and the second contact window.
15. The memory structure as claimed in claim 1, wherein the second capacitor structure is electrically connected to the second contact window structure.
16. The memory structure as claimed in claim 1, wherein the second capacitor structure comprises: The first electrode layer is electrically connected to the second contact window structure; The second electrode layer is located on the first electrode layer; And a dielectric layer, located between the first electrode layer and the second electrode layer.
17. The memory structure as described in claim 1, further comprising: A first dielectric structure and a second dielectric structure are located in the substrate, wherein the first character line structure is located in the first dielectric structure and the second character line structure is located in the second dielectric structure.
18. The memory structure as claimed in claim 17, wherein the first dielectric structure and the second dielectric structure extend from the first surface to the second surface.
19. The memory structure as claimed in claim 18, wherein the depth of the second dielectric structure is greater than the depth of the first dielectric structure.