Memory device and operating method thereof

TW202636442AInactive Publication Date: 2026-09-01TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
View PDF 0 Cites 0 Cited by

Patent Information

Application Number
TW114119536
Authority / Receiving Office
TW · TW
Patent Type
Applications
Current Assignee / Owner
Priority Date
2025-02-20
Filing Date
2025-05-23
Publication Date
2026-09-01
Estimated Expiration
Not applicable · inactive patent

Smart Images

  • Figure TWG2TA001074194_001
    Figure TWG2TA001074194_001
  • Figure TWG2TA001074194_002
    Figure TWG2TA001074194_002
  • Figure TWG2TA001074194_003
    Figure TWG2TA001074194_003
Patent Text Reader

Abstract

A memory device includes first and second word lines, a bit line, and a memory cell. The memory cell includes first and second semiconductor devices correspondingly of different first and second types. The first semiconductor device includes a gate electrically coupled to the first word line, a first source / drain electrically coupled to the bit line, and a second source / drain electrically coupled to receive a first power supply voltage. The second semiconductor device includes a gate, a first source / drain electrically coupled to the bit line, and a second source / drain. The second word line is electrically coupled to the gate of the second semiconductor device, and the second source / drain of the second semiconductor device is floating. Alternatively, the gate of the second semiconductor device and the second source / drain of the second semiconductor device are electrically coupled to receive a second power supply voltage different from the first power supply voltage.
Need to check novelty before this filing date? Find Prior Art