Fast low-leakage SRAM cell

Abstract

Fast low-leakage SRAM cells, such as for digital display systems, are disclosed herein. In one embodiment, a bit storage circuit includes a latch, a first transistor, and a second transistor. The latch can have a pair of cross-coupled inverters including first and second inverters. The first transistor can have a source coupled to receive a first control signal, a drain coupled to an input of the first inverter, and a gate coupled to receive a wordline select control signal. The second transistor can have a source coupled to receive a second control signal different from the first control signal, a drain coupled to an input of the second inverter, and a gate coupled to receive the wordline select control signal.

Images