DC-DC converter with parallel switch and its control method
Patent Information
- Application Number
- TW114106026
- Authority / Receiving Office
- TW · TW
- Patent Type
- Applications
- Current Assignee / Owner
- Filing Date
- 2025-02-19
- Publication Date
- 2026-09-01
- Estimated Expiration
- 2045-02-18
AI Technical Summary
Existing DC-DC converters with parallel switches suffer from uneven current distribution and require larger inductors to increase output capacity, leading to increased size, weight, and efficiency loss.
Implementing a control method that interleaves the conduction phases of drive signals for parallel switches, ensuring automatic current sharing and thermal equalization, allowing for reduced inductor size and weight while increasing operating frequency.
Improves switch utilization, reduces inductor losses, and enhances power conversion efficiency and density by alternating current through multiple switches.
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Abstract
Description
[Technical Field]
[0001] This invention relates to a DC-DC converter and its control method, particularly a DC-DC converter with parallel switches and its control method. [Previous Technology]
[0002] The switching DC-DC converter circuit belongs to the Switch Mode Power Supply (SMPS). This switching DC-DC converter circuit includes a switch (transistor). By switching the switch, the DC input power can be converted into the required DC output power, realizing the power conversion function. To expand the output capacity of the switching DC-DC converter circuit, the number of switches can be increased to two or more, and the two or more switches can be connected in parallel.
[0003] Referring to the non-isolated boost converter circuit 40 shown in Figure 9 as an example, it includes two switches connected in parallel, namely a first switch 401 and a second switch 402. The gate terminal of the first switch 401 receives a first drive signal S1' from a control unit, and the gate terminal of the second switch 402 receives a second drive signal S2' from the control unit. Referring to Figures 10A and 10B, the first drive signal S1' and the second drive signal S2' are pulse width modulation (PWM) signals, with a period of T' and a frequency of 1 / T' (Hertz, Hz). Generally, the first drive signal S1' and the second drive signal S2' have the same conduction phase, that is, the positions and widths of the pulses P1' and P2' of the first drive signal S1' and the second drive signal S2' are the same.
[0004] Please refer to Figures 9 and 10A to 10C. The non-isolated boost converter circuit 40 has an inductor L'. The inductor current IL' of the inductor L' changes with the position of the pulses P1' and P2' of the first drive signal S1' and the second drive signal S2'. Therefore, the operating frequency of the inductor L' (i.e. the frequency of the inductor current IL') is equal to the frequency of the first drive signal S1' and the second drive signal S2', i.e., 1 / T' (Hertz, Hz).
[0005] However, the different characteristics of the first switch 401 and the second switch 402 will cause uneven current distribution, reducing the utilization rate of the first switch 401 and the second switch 402. Furthermore, when the non-isolated boost converter circuit 40 wants to expand its output capacity, the inductor L' must also be a higher specification and larger inductor, which not only increases the overall size and weight of the circuit product, but also affects the power conversion efficiency due to the loss of the inductor L'. [Summary of the Invention]
[0006] In view of this, the main objective of the present invention is to provide a DC-DC converter with parallel switches and a control method thereof, in order to improve the problems associated with the expansion of output capacity in the prior art circuits and improve circuit performance.
[0007] The DC-DC converter with parallel switches of the present invention comprises: a switching DC-DC converter circuit, comprising at least one switching unit, each switching unit comprising N switches connected in parallel, the N switches including an i-th switch and an i+1-th switch, N being a positive integer greater than or equal to 2, and i being a positive integer from 1 to N-1; and a control unit electrically connected to the drive terminals of the N switches of each switching unit to control the on and off states of the N switches respectively, wherein the control unit outputs an i-th drive signal and an i+1-th drive signal to the i-th switch and the i+1-th switch respectively, and the on phases of the i-th drive signal and the i+1-th drive signal are interleaved.
[0008] The control method of the DC-DC converter with parallel switches of the present invention is implemented in a control unit electrically connected to at least one switching unit of a switching DC-DC conversion circuit. Each switching unit includes N switches connected in parallel. The N switches include an i-th switch and an i+1-th switch, where N is a positive integer greater than or equal to 2, and i is a positive integer from 1 to N-1. The control method includes: outputting an i-th drive signal to the i-th switch; and outputting an i+1-th drive signal to the i+1-th switch, wherein the conduction phases of the i-th drive signal and the i+1-th drive signal are interleaved.
[0009] The present invention utilizes the technical feature of controlling the conduction phases of the i-th driving signal and the (i+1)-th driving signal to alternately conduct. For each switching unit, the N switches are alternately turned on, allowing current to alternately pass through the N switches. This provides the effect of automatic current sharing among the N switches of each switching unit, improves the utilization rate of the N switches of each switching unit, and makes the N switches of each switching unit thermally even. On the other hand, the present invention can increase the operating frequency of a transformer (i.e., a transformer corresponding to an isolated switching circuit) or an inductor (i.e., a transformer corresponding to a non-isolated switching circuit) in the switching DC-DC converter circuit. The inductance value of the transformer or inductor will decrease due to the increase in operating frequency, which means that the size of the transformer or inductor can be reduced and its weight can be reduced. Correspondingly, the cost of the transformer or inductor can be reduced, the losses caused by the transformer or inductor can be reduced, and due to the reduction in losses, the power conversion efficiency and power density of the DC-DC converter can be improved.
Implementation Method
[0010] Please refer to Figure 1. The DC-DC converter with parallel switches of the present invention includes a switching DC-DC conversion circuit 1 and a control unit 20.
[0011] The switching DC-DC converter circuit 1 belongs to the Switch Mode Power Supply (SMPS) and includes at least one switching unit 10. Each switching unit 10 includes N switches 100 connected in parallel, where N is a positive integer greater than or equal to 2. Through the individual switching operations of the N switches 100 of each switching unit 10, the DC input power supply Vin can be converted into the required DC output power supply Vout, thereby realizing the power conversion function. For example, the switching DC-DC converter circuit 1 can be an isolated or non-isolated bridge converter circuit, a boost converter circuit, a buck converter circuit, a buck-boost bidirectional converter circuit, or a flyback converter circuit, etc.
[0012] The switching DC-DC converter circuit 1 shown in Figure 1 is an example of a non-isolated boost converter circuit, but the switching DC-DC converter circuit 1 of the present invention is not limited to this non-isolated boost converter circuit. The non-isolated boost converter circuit includes a switching unit 10, an inductor L, a diode D and a capacitor C. The switching unit 10 includes N switches 100, and the input side of the switching DC-DC converter circuit 1 has a first input terminal 11 and a second input terminal 12. The output side of the switching DC-DC converter circuit 1 has a first output terminal 13 and a second output terminal 14, wherein the second input terminal 12 and the second output terminal 14 are electrically connected to a reference potential terminal 15 (e.g., ground). One end of the inductor L is electrically connected to the first input terminal 11, and the other end of the inductor L is electrically connected to the anode of the diode D. There is a node 16 between the inductor L and the anode of the diode D. The cathode of the diode D and one end of the capacitor C are electrically connected to the first output terminal 13, and the other end of the capacitor C is electrically connected to the reference potential terminal 15. Each switch 100 has a first connection terminal, a second connection terminal, and a driving terminal. The first connection terminal is electrically connected to the node 16, and the second connection terminal is electrically connected to the reference potential terminal 15. The "parallel connection" of the switches 100 means that the first connection terminals of the N switches 100 are electrically connected to each other (i.e., connected to the node 16), and the second connection terminals of the N switches 100 are electrically connected to each other (i.e., connected to the reference potential terminal 15). Each of the switches 100 is a transistor, such as an insulated gate bipolar transistor (IGBT), a metal-oxide-semiconductor field-effect transistor (MOSFET), or a bipolar junction transistor (BJT). The switch 100 shown in Figure 1 is an example of an IGBT, with its first connection terminal being the collector, its second connection terminal being the emitter, and its driving terminal being the gate.
[0013] The control unit 20 is electrically connected to the driving terminals of the N switches 100 of the switching unit 10 to control the ON and OFF states of the N switches 100 of the switching unit 10 respectively. The control unit 20 may be a single driver chip with N output terminals to be electrically connected to the driving terminals of the N switches 100 of the switching unit 10 respectively; or the control unit 20 may include multiple driver chips to be electrically connected to the driving terminals of the N switches 100 of the switching unit 10 respectively.
[0014] In one embodiment, the control unit 20 outputs N drive signals to the drive terminals of the N switches 100 of the switching unit 10, respectively. The N drive signals are pulse width modulation (PWM) signals with the same period and the same pulse width. It is understood that each period of each PWM signal includes a conduction segment and a cutoff segment. For example, the potential of the conduction segment of each PWM signal can be high to form a pulse, and the potential of the cutoff segment can be low. Each switch 100 is in the conduction segment and in the cutoff segment. The conduction segments of the N switches 100 cannot be repeated. In one embodiment, the duty cycle of each PWM signal is less than (1 / N)×100%.
[0015] From the perspective of phase, the phase of each cycle of the pulse width modulation signal is from 0 degrees to 360 degrees. The conduction segment corresponds to a conduction phase. The control unit 20 can modulate the occurrence position (i.e., pulse position) and time width (i.e., pulse width) of the conduction segment in each pulse width modulation signal, and make the responsibility period of each pulse width modulation signal less than (1 / N)×100%, so as to realize that the conduction phases of the N drive signals are staggered. In this way, only one of the N switches 100 is in the conducting state at the same time point, while the other switches 100 are in the cut-off state. Therefore, in this invention, there is no situation where any two switches 100 are conducting at the same time.
[0016] The N switches 100 of the present invention include an i-th switch and an i+1-th switch, where i is a positive integer from 1 to N-1. The control method of the present invention includes the control unit 20 outputting an i-th driving signal to the driving terminal of the i-th switch and outputting an i+1-th driving signal to the driving terminal of the i+1-th switch, wherein the conduction phases of the i-th driving signal and the i+1-th driving signal are interleaved. In one embodiment, the conduction phases of the i-th driving signal and the i+1-th driving signal differ from each other by 360 / N degrees. It should be noted, however, that the pulse phase control means of the control unit 20 for each pulse width modulation signal, such as phase shift or phase delay, are common knowledge in the art.
[0017] As shown in the embodiment of Figure 2, N=2, meaning that the N switches 100 of the switching unit 10 are actually two switches 100, defined as a first switch 101 and a second switch 102 respectively. Referring to Figures 3A and 3B, the control unit 20 outputs a first drive signal S1 and a second drive signal S2 to the drive terminals of the first switch 101 and the second switch 102 respectively. The first drive signal S1 and the second drive signal S2 are pulse width modulation signals, and the duty cycles of both the first drive signal S1 and the second drive signal S2 are less than 50%. (That is: (1 / N)×100%=(1 / 2)×100%=50%), the conduction phases of the first driving signal S1 and the second driving signal S2 are staggered, and the conduction phases of the first driving signal S1 and the second driving signal S2 are 180 degrees apart (that is: 360° / N=360° / 2=180°). In other words, the phase difference θd between the conduction phases of the first driving signal S1 and the second driving signal S2 is 180 degrees. The waveform of the current through the inductor L (hereinafter defined as an inductor current IL) is shown in Figure 3C. The magnitude of the inductor current IL increases in the conduction region Ton of the first driving signal S1 and the second driving signal S2, and decreases in the cutoff region Toff. Therefore, the operating frequency of the inductor L (that is, the frequency of the inductor current IL) is N×f, that is, 2f, where f=1 / T, and T is the period of the first driving signal S1 and the second driving signal S2.
[0018] In this invention, because the conduction phases of the i-th driving signal and the i+1-th driving signal are interleaved, the N switches 100 in each of the switching units 10 are alternately turned on, so that the current alternately passes through the N switches 100, thereby achieving the effect of automatic current sharing, improving the utilization rate of the N switches 100 in each of the switching units 10, and making the N switches 100 in each of the switching units 10 thermally even.
[0019] Comparing the operating frequency of the inductor L of the present invention shown in Figure 3C with the operating frequency of the conventional inductor L' shown in Figure 10C, the operating frequency of the inductor L of the present invention is 2f, while the operating frequency of the conventional inductor L' is only f. Therefore, the control method of the present invention can relatively increase the operating frequency of the inductor L. According to the inductance formula: XL = 2πfL, where XL is the inductance, f is the operating frequency of the inductor, and L is the inductance value of the inductor, under the premise that the inductance (XL) is a constant (i.e., the ripple magnitudes of the inductor current IL in Figure 2 and the inductor current IL' in Figure 9 are the same), the operating frequency (f) and the inductance value (L) of the inductor exhibit a negative correlation. In this way, by means of the control method of the present invention, the inductance value of the inductor L in the present invention will decrease due to the increase in operating frequency, which means that the volume of the inductor L can be reduced, the weight can be reduced, the cost can be reduced, the loss can be reduced, the power conversion efficiency can be improved, and the power density can be improved.
[0020] In other embodiments, the state and function of N>2 can be deduced similarly. For example, N=3 corresponds to three switches, including a first switch, a second switch, and a third switch. The control unit 20 outputs a first drive signal, a second drive signal, and a third drive signal to the first switch, the second switch, and the third switch, respectively. The conduction phases of the first drive signal to the third drive signal are interleaved, and the duty periods of the first drive signal to the third drive signal are all less than (1 / 3)×100%. The conduction phases of the first drive signal and the second drive signal differ by 120 degrees, and the conduction phases of the second drive signal and the third drive signal differ by 120 degrees. In this way, the operating frequency of the inductor L is 3f.
[0021] In other embodiments, the control method of the present invention can be applied to other isolated or non-isolated conversion circuits that also have the switching unit 10, for example: the switching DC-DC conversion circuit 1 shown in FIG4 is a non-isolated buck converter with one switching unit 10; the switching DC-DC conversion circuit 1 shown in FIG5 is a non-isolated buck-boost bidirectional converter with two switching units 10; the switching DC-DC conversion circuit 1 shown in FIG6 is an isolated flyback converter with one switching unit 10; the switching DC-DC conversion circuit 1 shown in FIG7 is an isolated half-bridge converter with multiple switching units 10 respectively disposed on the bridge arm; the switching DC-DC conversion circuit 1 shown in FIG8 is an isolated full-bridge converter. The converter has multiple switching units 10 respectively disposed on the bridge arm, and the corresponding effects can be deduced from the example of the aforementioned non-isolated boost converter circuit. That is, the size of the transformer 30 shown in Figures 6 to 8 and the inductor L shown in Figures 4 and 5 can be reduced and the weight can be reduced. Correspondingly, the cost of the transformer 30 or the inductor L can be reduced, the losses caused by the transformer 30 or the inductor L can be reduced, and due to the reduction of losses, the power conversion efficiency and power density of the DC-DC converter can be improved. [Simplified Explanation of the Diagram]
[0022] Figure 1: A circuit diagram of an embodiment of the DC-DC converter with parallel switches of the present invention (non-isolated boost converter circuit). Figure 2: A circuit diagram of an embodiment of the DC-DC converter with parallel switches of the present invention (non-isolated boost converter circuit). Figure 3A: A waveform diagram of the first drive signal output to the first switch in the present invention. Figure 3B: A waveform diagram of the second drive signal output to the second switch in the present invention. Figure 3C: A waveform diagram of the current through the inductor in the present invention. Figure 4: A circuit diagram of an embodiment of the DC-DC converter with parallel switches of the present invention (non-isolated buck converter circuit). Figure 5: A circuit diagram of an embodiment of the DC-DC converter with parallel switches of the present invention (non-isolated buck-boost bidirectional converter circuit). Figure 6: A circuit diagram of an embodiment of the DC-DC converter with parallel switches of the present invention (isolated flyback converter circuit). Figure 7: A circuit diagram of an embodiment of the DC-DC converter with parallel switches of the present invention (isolated half-bridge converter circuit). Figure 8: A circuit diagram of an embodiment of the DC-DC converter with parallel switches of the present invention (isolated full-bridge converter circuit). Figure 9: A circuit diagram of a conventional non-isolated boost converter circuit. Figure 10A: A waveform diagram of the first drive signal output to the first switch in a conventional circuit. Figure 10B: A waveform diagram of the second drive signal output to the second switch in a conventional circuit. Figure 10C: A waveform diagram of the current through the inductor in a conventional non-isolated boost converter circuit.
Claims
1. A DC-DC converter with parallel switches, comprising: a switching DC-DC conversion circuit, including at least one switching unit, each switching unit including N switches connected in parallel, the N switches including an i-th switch and an (i+1)-th switch, N being a positive integer greater than or equal to 2, and i being a positive integer from 1 to N-1; and a control unit electrically connected to the driving terminals of the N switches of each switching unit, the control unit outputting N driving signals to the driving terminals of the N switches respectively, the N driving signals being pulse width modulation signals having the same period and the same pulse width, to control the on and off states of the N switches respectively, wherein... The control unit outputs an i-th drive signal and an i+1-th drive signal to the i-th switch and the i+1-th switch respectively, and the conduction phases of the i-th drive signal and the i+1-th drive signal are interleaved and do not repeat.
2. A DC-DC converter with parallel switches as described in claim 1, wherein, The conduction phases of the i-th driving signal and the (i+1)-th driving signal differ by 360 / N degrees.
3. A DC-DC converter with parallel switches as described in claim 1 or 2, wherein, The i-th drive signal and the i+1-th drive signal are pulse width modulation signals with a duty period of less than (1 / N)×100%.
4. A control method for a DC-DC converter with parallel switches, implemented in a control unit electrically connected to at least one switching unit of a switching DC-DC converter circuit, each switching unit comprising N switches connected in parallel, the control unit outputting N drive signals to the drive terminals of the N switches respectively, the N drive signals being pulse width modulation signals having the same period and the same pulse width, the N switches including an i-th switch and an (i+1)-th switch, where N is a positive integer greater than or equal to 2, and i is a positive integer from 1 to N-1, the control method comprising: outputting an i-th drive signal to the i-th switch; and outputting an (i+1)-th drive signal to the (i+1)-th switch, wherein... The conduction phases of the i-th driving signal and the (i+1)-th driving signal are interleaved and do not repeat.
5. A control method for a DC-DC converter with parallel switches as described in claim 4, wherein, The conduction phases of the i-th driving signal and the (i+1)-th driving signal differ by 360 / N degrees.
6. A control method for a DC-DC converter with parallel switches as described in claim 4 or 5, wherein, The i-th drive signal and the i+1-th drive signal are pulse width modulation signals with a duty period of less than (1 / N)×100%.