Frequency divider

Abstract

This disclosure proposes a frequency divider, which includes a signal receiving terminal, a frequency division unit, and a signal transmitting terminal. The signal receiving terminal is configured to connect to an incremental encoder and receive an encoded signal from the incremental encoder. The frequency division unit is connected to the signal receiving terminal and performs frequency division on the encoded signal based on a frequency division setting value to generate a frequency-divided encoded signal. The signal transmitting terminal is connected to the frequency division unit and is configured to transmit the frequency-divided encoded signal.

Description

Technical Field

[0001] This case relates to a frequency divider, particularly a frequency divider used in incremental encoders. Prior Technology

[0002] In systems requiring precise control, such as robotic arms and elevators, encoders are needed to detect the rotation angle, speed, and direction of motors so that the control system can precisely control the motor's operation.

[0003] However, when the motor rotates at high speed, the encoder generates a large number of encoded signals, especially for incremental encoders. This is because the encoding process produces both A and B signals, resulting in a substantial amount of encoded signals generated per unit time, significantly increasing the load on the entire system. Therefore, a method is needed to improve the performance of incremental encoders. Summary of the Invention

[0004] In view of the shortcomings of the prior art, this application proposes a frequency divider, including a signal receiving end, a frequency dividing unit, and a signal transmitting end. The signal receiving end is used to connect to an incremental encoder and receive an encoded signal from the incremental encoder. The frequency dividing unit is connected to the signal receiving end, and the frequency dividing unit divides the encoded signal according to a frequency dividing set value to obtain a frequency-divided encoded signal. The signal transmitting end is connected to the frequency dividing unit and is used to transmit the frequency-divided encoded signal.

[0005] In some embodiments, the frequency divider unit includes a counter that counts the encoded signal according to a frequency divider setting value. When the frequency divider setting value is reached, the counter outputs an encoded count signal, and the frequency divider unit uses the encoded count signal as a frequency divider encoded signal.

[0006] In some embodiments, the frequency divider unit includes a delay module connected to a counter. The delay module receives an encoded count signal and outputs the encoded count signal when it is determined that the encoded signal remains stable within a predetermined time.

[0007] In some embodiments, the frequency divider unit includes an inversion module connected to the delay module, and the inversion module inverts the encoded counting signal according to an inversion instruction.

[0008] In some embodiments, the frequency division unit includes a compensation module connected to the inverting module. The compensation module estimates the actual speed of a motor based on the coded counting signal and performs signal compensation on the coded counting signal based on the actual speed of the motor.

[0009] In some embodiments, the encoding signal and the frequency division encoding signal are both transistor-to-transistor logic signals.

[0010] In some embodiments, both the encoded signal and the frequency-divided encoded signal are high-threshold logic signals.

[0011] In some embodiments, an input unit is further included, which is connected to the frequency divider unit and is used to input a frequency divider setting value.

[0012] In some embodiments, the frequency division setting value ranges from 1 to 64.

[0013] In some embodiments, this invention reduces the number of pulses in the encoded signal generated by the encoder using a frequency divider, thereby reducing the computational load on the control unit. In some embodiments, this invention utilizes a delay module to prevent the encoded signal generated when the motor is subjected to external forces from being received, thereby improving the stability of the encoded signal. In some embodiments, this invention uses a reversing module to reverse the encoded signal, thus ensuring that the logic of the control system remains consistent regardless of how the elevator motor rotates. In some embodiments, this invention uses a compensation module to compensate for the encoded signal, ensuring the stability and accuracy of the encoded signal. Simple Explanation of the Diagram

[0014] Figure 1 shows the block diagram of each component in this case. Implementation

[0015] Please refer to Figure 1. This invention relates to a frequency divider 1. The frequency divider 1 is used to connect to an incremental encoder A to perform frequency division on the encoded signal generated by the incremental encoder A. The frequency divider 1 includes a signal receiving end 10, a frequency division unit 20, and a signal transmitting end 30.

[0016] Please refer to Figure 1. The signal receiver 10 is connected to an incremental encoder A. The encoded signal generated by the incremental encoder A is transmitted to the signal receiver 10 for reception. The incremental encoder A is used to detect the motor's operating status. During the detection process, it generates signals A and B. Therefore, the encoded signal includes signals A and B. Since signals A and B are square wave signals with a phase difference of 90°, the motor's operating status can be determined using signals A and B. For example, the phase difference between signals A and B indicates the direction of motor rotation. For instance, when signal A leads signal B, it means the motor is rotating clockwise; conversely, when signal B leads signal A, it means the motor is rotating counterclockwise. Alternatively, by calculating the pulse frequencies of signals A and B, the actual operating speed of the motor can be determined. In some embodiments, the encoded signal is a transistor-transistor logic (TTL) signal. In some embodiments, the encoded signal is a high-threshold logic (HTL) signal.

[0017] Referring to Figure 1, the frequency divider unit 20 is connected to the signal receiver 10. The frequency divider unit 20 divides the encoded signal according to a frequency divider setting value to obtain a frequency-divided encoded signal. For example, when the frequency divider setting value is 2, the frequency of the frequency-divided encoded signal after frequency divider unit 20 divides the encoded signal is half the frequency of the encoded signal. Similarly, when the frequency divider setting value is 2, the frequency of the frequency-divided encoded signal is one-quarter the frequency of the encoded signal. Other frequency divider setting values ​​follow the same principle and will not be described in detail. In some instances, the frequency divider 1 further includes an input unit 40, which is connected to the frequency divider unit 20 and is used to input the frequency divider setting value. The input unit 40 is selected from one of the following: keyboard, touch screen, button, etc. In some embodiments, the frequency divider setting value ranges from 1 to 64. In some embodiments, the frequency-divided encoded signal is a transistor-to-transistor logic signal. In some embodiments, the frequency-divided encoded signal is a high-threshold logic signal. Furthermore, the type of the encoded signal is the same as that of the frequency divider encoded signal. For example, if the encoded signal is a transistor-to-transistor logic signal, then the frequency divider encoded signal is also a transistor-to-transistor logic signal. Similarly, if the encoded signal is a high-threshold logic signal, then the frequency divider encoded signal is also a high-threshold logic signal.

[0018] Referring to Figure 1, the signal transmitter 30 is connected to the frequency divider unit 20, and the signal transmitter 30 is used to transmit the frequency divider encoded signal. In some embodiments, the signal transmitter 30 is connected to a control unit, which is used to grasp the motor's operating status based on the frequency divider encoded signal, thereby controlling the motor's operation. The control unit includes one or more suitable types of general-purpose or special-purpose microprocessors, digital signal processors, artificial intelligence processors, and / or microcontrollers.

[0019] In this invention, the frequency divider 1 operates as follows: when the motor is running, an incremental encoder A generates an encoded signal. The signal receiver 10 receives the encoded signal and transmits it to the frequency divider unit 20. The frequency divider unit 20 divides the encoded signal according to a frequency divider setting value to reduce the number of pulses in the encoded signal, thus obtaining a frequency-divided encoded signal. The signal transmitter 30 then transmits the frequency-divided encoded signal to the control unit, allowing the control unit to monitor the motor's operating status and control its operation. In some embodiments, the motor is an elevator motor used to drive the vertical movement of an elevator.

[0020] Referring to Figure 1, in some embodiments, the frequency divider unit 20 includes a counter 21. The counter 21 counts the encoded signal according to a frequency divider setting value, and outputs an encoded count signal when the frequency divider setting value is reached. The frequency divider unit 20 uses the encoded count signal as the frequency-divided encoded signal. The encoded signal includes a complex number of pulses. The counter 21 counts the number of pulses in the encoded signal. For example, assuming the encoded signal has 1000 pulses, when the frequency divider setting value is 2, the counter 21 will count the number of pulses in the encoded signal. Each time the count is completed, the counter 21 increments by 1. When the counter 21 increments to 2, it outputs one pulse. In this way, after the counter 21 has counted all the pulses in the encoded signal, it will output an encoded count signal with 500 pulses, thus completing the frequency divider operation on the encoded signal. Next, if the frequency divider unit 20 does not need to further process the encoded counting signal (e.g., but not limited to delay processing, inversion processing, compensation processing), the encoded counting signal with 500 pulses is used as the frequency-divided encoded signal for transmission by the signal transmitter 30. Furthermore, the encoded counting signal is the same as the encoded signal, both having A and B signals. And the type of the encoded counting signal is the same as the encoded signal, both being transistor-to-transistor logic signals or high-threshold logic signals.

[0021] Referring to Figure 1, in some embodiments, the frequency divider unit 20 includes a delay module 22 connected to the counter 21. The delay module 22 receives the encoded counting signal and outputs the encoded counting signal when it determines that the encoded signal remains stable within a predetermined time. For example, after receiving the encoded counting signal, the delay module 22 does not output it immediately, but waits for a predetermined time. When it determines that the encoded counting signal is a stable signal, it then outputs the encoded counting signal to the signal transmitter 30 (i.e., the aforementioned delay processing). Since the encoded signal may become chaotic after the motor is subjected to external impact or shaking, the delay module 22 can avoid the above problems and maintain the signal integrity of the frequency divider encoded signal. In some embodiments, the delay module 22 is a circuit or a functional module of the processor.

[0022] Referring to Figure 1, in some embodiments, the frequency divider unit 20 includes a reversing module 23 connected to the delay module 22. The reversing module 23 reverses the encoded counting signal according to a reversing instruction. When the frequency divider 1 of this invention is applied to the elevator motor of an elevator system, the elevator system typically uses a unified direction judgment logic. For example, forward movement (ascending) is set to "clockwise" movement, and reverse movement (descending) is set to "counterclockwise" movement. Without a reversing encoder signal, the elevator motor may cause the elevator system to misjudge the direction when moving in the reverse direction. Therefore, when the elevator changes from ascending to descending, or from ascending to descending, the elevator system issues a reversing instruction. After receiving the reversing instruction, the reversing module 23 reverses the encoded counting signal (i.e., the aforementioned reversing processing). When the elevator is ascending, the phase of signal A in the coded counting signal leads the phase of signal B. When the elevator reverses to descend, the reverse module 23, upon receiving the reverse command, will lag the phase of signal A in the coded counting signal behind the phase of signal B, thus completing the reverse processing of the coded counting signal. Therefore, the reverse module 23 ensures that the logic of the control system remains consistent regardless of how the elevator motor rotates. In some embodiments, the reverse module 23 is a circuit, or it may be a functional module of a processor.

[0023] Referring to Figure 1, in some embodiments, the frequency divider unit 20 includes a compensation module 24 connected to the inverting module 23. The compensation module 24 estimates the actual speed of a motor based on the encoded counting signal and performs signal compensation (i.e., the aforementioned compensation processing) on ​​the encoded counting signal based on the actual motor speed. For example, when the actual motor speed is lower than a threshold, the encoder generates fewer pulses, meaning fewer pulses in the encoded signal, which reduces the system's resolution and affects controllability. In this case, the compensation module 24 increases the number of pulses in the encoded counting signal. Conversely, when the actual motor speed is higher than the threshold, the encoded counting signal is smoothed to ensure its stability. In some embodiments, the compensation module 24 is a circuit or a functional module of a processor.

[0024] In some embodiments, the present invention reduces the number of pulses in the encoded signal generated by the encoder by using a frequency divider 1, thereby reducing the computational load on the control unit. In some embodiments, the present invention uses a delay module 22 to prevent the encoded signal generated when the motor is affected by external forces from being received, thereby improving the stability of the encoded signal. In some embodiments, the present invention uses a reversing module 23 to reverse the encoded signal, thus ensuring that the logic of the control system remains consistent regardless of how the elevator motor rotates. In some embodiments, the present invention uses a compensation module 24 to compensate for the encoded signal to ensure the stability and accuracy of the encoded signal.

[0025] A: Incremental encoder 1: Frequency divider 10: Signal receiving end 20: Frequency divider unit 21: Counter 22: Delay Module 23: Reverse Module 24: Compensation Module 30: Signal Transmitter 40: Input Unit

Claims

1. A frequency divider, comprising: A signal receiver is connected to an incremental encoder and receives an encoded signal from the incremental encoder, which is connected to a motor; a frequency divider is connected to the signal receiver and divides the encoded signal according to a frequency divider setting value to obtain a frequency-divided encoded signal; and a signal transmitter is connected to the frequency divider and transmits the frequency-divided encoded signal; wherein the frequency divider includes a counter that counts the encoded signal according to the frequency divider setting value, and outputs an encoded count signal when the frequency divider setting value is reached; the frequency divider uses the encoded count signal as the frequency-divided encoded signal; the frequency divider includes a delay module connected to the counter, which receives the encoded count signal and outputs the encoded count signal when it is determined that the encoded signal remains stable for a predetermined time.

2. The frequency divider as claimed in claim 1, wherein the frequency divider unit includes an inversion module connected to the delay module, the inversion module inverting the coded count signal according to an inversion instruction.

3. The frequency divider as described in claim 2, wherein the frequency divider unit includes a compensation module connected to the inverting module, the compensation module estimating the actual speed of a motor based on the coded counting signal, and performing signal compensation on the coded counting signal based on the actual speed of the motor.

4. The frequency divider as described in claim 1, wherein the encoded signal and the frequency divider encoded signal are both transistor-to-transistor logic signals.

5. The frequency divider as described in claim 1, wherein the encoded signal and the frequency divider encoded signal are both high threshold logic signals.

6. The frequency divider as described in claim 1 further includes an input unit connected to the frequency divider unit, the input unit being used to input the frequency divider setting value.

7. The frequency divider as described in claim 1, wherein the frequency divider setting value is in the range of 1 to 64.

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