A receiver and data receiving method for performing adaptive correction

Abstract

The receiver's phase interpolator generates multiple interpolated clock signals. Multiple decoders cooperate to demultiplex the input data signal into first demultiplexed data signals provided by themselves, referencing the multiple interpolated clock signals. They then demultiplex the first demultiplexed data signals into second demultiplexed data signals and decode the second demultiplexed data signals into decoded signals. An adaptive controller generates an output data signal based on the decoded output of the decoded signal. When the absolute values ​​of the bit values ​​representing the data portion of the second sample and the data portion representing the third sample are not equal, an adaptive calibration is applied to the phase interpolator to change the phase of the interpolated clock signals. The second and third samples of the decoded signal are generated before and after the first sample, respectively.

Description

[Technical Field]

[0001] This invention relates to a receiver, and more particularly to an adaptively calibrated receiver and a data receiving method. [Previous Technology]

[0002] Serializer / deserializer (SerDes) functions are widely used in communication standards such as Ethernet, Peripheral Component Interconnect Express (PCIe), and Universal Serial Bus (USB). For a receiver that converts serial input data into parallel output data, good clock and data recovery performance to achieve a low bit error rate is crucial. [Summary of the Invention]

[0003] Therefore, the object of the present invention is to provide a receiver and a data receiving method that have better data clock recovery performance.

[0004] According to one embodiment of the present invention, the receiver includes a phase interpolator, a decoder device, and an adaptive controller. The phase interpolator receives an input clock and applies phase interpolation to the input clock to generate N interpolated clock signals, where N ≥ 2, and each interpolated clock signal has an adjustable phase shift relative to the input clock. The decoder device includes N decoders. Each of the N decoders is connected to the phase interpolator to receive one of the corresponding N interpolated clock signals. The N decoders cooperate to receive an input data signal in pulse amplitude modulation (PAM)-M format, and cooperate to demultiplex the input data signal into N first demultiplexed data signals respectively provided by the decoders, where M ≥ 3, by referring to the N interpolated clock signals. The N decoders demultiplex the first demultiplexed data signal they provide into P second demultiplexed data signals, and decode the P second demultiplexed data signals into P decoded signals, where P ≥ 2. Each of the P decoded signals has a plurality of sequentially generated samples, each of the samples has a data portion, and each of the samples in at least one of the P decoded signals also has an error portion. The adaptive controller is electrically connected to the decoder device to receive a decoded output from the decoded signals generated by the N decoders, and is electrically connected to the phase interpolator. Based on the decoded signals, the adaptive controller generates the decoded output and applies adaptive correction to the phase interpolator to adjust the phase shift of the interpolated clock signals by referring to the data portion and error portion of a first sample of the decoded signals, the data portion of a second sample of the decoded signals generated before the first sample, and the data portion of a third sample of the decoded signals generated after the first sample. When the absolute value of a bit value of the data portion of the second sample representing the decoded signals is not equal to the absolute value of a bit value of the data portion of the third sample representing the decoded signals, the adaptive controller adjusts the phase shifts of the N interpolated clock signals to change the phase of the N interpolated clock signals.

[0005] According to another embodiment of the present invention, the data receiving method is performed by a receiver and includes the following steps: (A) decoding an input data signal into a decoded output having a plurality of sequentially generated samples based on a clock signal, each sample having a data portion, and each of at least some of the samples having an error portion; (B) adjusting the phase of the clock signal with reference to the data portion and the error portion of a first sample of the decoded output, the data portion of a second sample of the decoded output generated before the first sample was generated, and the data portion of a third sample of the decoded output generated after the first sample was generated. In step (B), the phase of the clock signal is changed when the absolute value of a bit value representing the data portion of the second sample of the decoded output is not equal to the absolute value of a bit value representing the data portion of the third sample of the decoded output.

Implementation Method

[0006] Before the present invention is described in detail, it should be noted that similar elements are represented by the same numbers in the following description.

[0007] Referring to Figures 1 and 2, one embodiment of the receiver of the present invention is suitable for converting a serial input data into a parallel input data, and includes a channel compensator 11, a voltage regulator 12, a multiphase filter 13, a current mode logic (CML) complementary metal oxide semiconductor (CMOS) converter 14, a phase interpolator 15, a decoder device 16, and an adaptive controller 17.

[0008] The channel compensator 11 is used to receive an input data signal Din in Pulse Amplitude Modulation (PAM-M) format, and to apply channel compensation to the input data signal Din to generate a feed data signal in PAM-M format, wherein M≥3 and the gain of the channel compensator 11 is adjustable. For ease of explanation, in this embodiment, the input data signal Din and the feed data signal are in PAM-4 format (i.e., M=4) and have a data rate of 112Gbps (i.e., 56 Gbaud).

[0009] In this embodiment, the channel compensator 11 includes an equalizer device 111 and a variable gain amplifier 112. The equalizer device 111 includes a continuous time linear equalizer (CTLE) 116 and a low frequency equalizer (CTLE) 117. The high-frequency components of the input data signal Din are compensated by the continuous time linear equalizer 116, and the mid-frequency and low-frequency components of the input data signal Din are compensated by the low frequency equalizer 117. The resulting signal derived from the aforementioned compensation is used to generate the feed data signal by adjusting its amplitude using the variable gain amplifier 112. The parameters of the continuous time linear equalizer 116 and the low frequency equalizer 117 can be adjusted to change the gain of the channel compensator 11.

[0010] The regulator 12 generates a reference voltage with adjustable amplitude.

[0011] The multiphase filter 13 receives a differential input clock signal pair CKin at a current-mode logic level, and splits the differential input clock signal pair CKin into two differential first clock signal pairs. These differential first clock signal pairs have the current-mode logic level and are 90 degrees out of phase. For ease of explanation, in this embodiment, the frequency of the differential input clock signal pair CKin is 14 GHz.

[0012] The current-mode logic complementary metal-oxide-semiconductor converter 14 is electrically connected to the multiphase filter 13 to receive the equal differential first clock signal pair and convert the equal differential first clock signal pair into two differential second clock signal pairs of complementary metal-oxide-semiconductor level.

[0013] The phase interpolator 15 and some components of the adaptive controller 17 cooperate to form a clock data recovery (CDR) circuit. The phase interpolator 15 is electrically connected to the current-mode logic complementary metal-oxide-semiconductor converter 14 to receive the equal differential second clock signal pairs, which together constitute a clock input. The phase interpolator 15 also performs phase interpolation on the clock input to generate N interpolated clock signals, where N≥2. A phase shift corresponding to each interpolated clock signal of the clock input is adjustable. For ease of explanation, in this embodiment, four interpolated clock signals are generated (i.e., N=4).

[0014] The decoder device 16 includes N decoders 160 (four decoders 160 in this embodiment). In this embodiment, each decoder 160 includes an offset de-counter 161, a ring counter 162, a 1 / Q divider 163, a first demultiplexer 164, a buffer 165, a second demultiplexer 166, P analog-to-digital converters 167, a phase calibration circuit 168, and a pair of Q demultiplexers 169, where P≥2 and Q≥2. For ease of explanation, in this embodiment, a 1 / 2 divider 163, four analog-to-digital converters 167, and a 1:2 demultiplexer 169 are used (i.e., P=4 and Q=2).

[0015] For each of the decoders 160, the de-offsetter 161 is electrically connected to the phase interpolator 15 to receive a corresponding one of the interpolated clock signals and delays the corresponding one of the interpolated clock signals to generate a de-offset clock signal. The delay of the de-offset clock signal relative to the corresponding one of the interpolated clock signals is adjustable. The first demultiplexer 164 is electrically connected to the de-offsetter 161 to receive the de-offset clock signal and is electrically connected to the channel compensator 11.

[0016] The first demultiplexers 164 of the decoders 160 cooperate with each other to receive the feed data signal from the channel compensator 11, and demultiplex the feed data signal into N first demultiplexed data signals (four first demultiplexed data signals in this embodiment) according to the de-offset clock signals generated by the de-offsetters 161 of the decoders 160, and output them from the first demultiplexers 164. In this embodiment, each of the first demultiplexed data signals has a data rate of 14 Gbaud.

[0017] It should be noted that, for each of these de-offset clock signals, by adjusting the delay of the de-offset clock signal, an offset between the de-offset clock signal and any other de-offset clock signal can be changed.

[0018] In this embodiment, for each decoder 160, the first demultiplexer 164 includes a sampling switch 1641. The sampling switch 1641 has a first terminal electrically connected to the channel compensator 11 to receive the feed data signal, a second terminal providing a corresponding one of the first demultiplexed data signals, and a control terminal electrically connected to the de-offsetter 161 to receive the de-offset clock signal. The sampling switch 1641 switches between on and off according to the de-offset clock signal. When the sampling switch 1641 is on, the feed data signal is transmitted through the sampling switch 1641 as one of the corresponding first demultiplexed data signals.

[0019] For each of the decoders 160, the ring counter 162 is electrically connected to the de-offsetter 161 to receive the de-offset clock signal and generates a P-bit count output (four bits in this embodiment) based on the de-offset clock signal. A predetermined logic value (e.g., logic value "1") cycles through the bits of the count output at a rate defined by the de-offset clock signal. The 1 / Q divider 163 (i.e., the 1 / 2 divider 163 in this embodiment) is electrically connected to the ring counter 162 to receive the count output and generates a third clock signal with a frequency of 1 / Q (1 / 2 in this embodiment) of the count output frequency based on the count output.

[0020] For each of the decoders 160, the buffer 165 is electrically connected to the second terminal of the sampling switch 1641 to receive the first demultiplexed data signal and buffers the first demultiplexed data signal to generate a PAM-M format (PAM-4 format in this embodiment) data signal to be decoded. The second demultiplexer 166 is electrically connected to the ring counter 162 to receive the count output and is electrically connected to the buffer 165 to receive the data signal to be decoded, and demultiplexes the data signal to be decoded into P second demultiplexed data signals (four in this embodiment) according to the count output. Each analog-to-digital converter 167 is electrically connected to the second demultiplexer 166 to receive the corresponding second demultiplexed data signal and is electrically connected to the voltage regulator 12 to receive the reference voltage. One of the analog-to-digital converters 167 is an (m+1)-bit analog-to-digital converter that performs analog-to-digital conversion on the corresponding second demultiplexing data signal according to the reference voltage to generate a first decoded signal in non-return-to-zero (NRZ) format, where m = log₂M (in this embodiment, m = 2 and one of the analog-to-digital converters 167 is a 3-bit analog-to-digital converter). The first decoded signal has an m-bit data portion (2 bits in this embodiment) and a 1-bit error portion. Each of the remaining analog-to-digital converters 167 is an m-bit analog-to-digital converter (2-bit analog-to-digital converter in this embodiment) that performs analog-to-digital conversion on the corresponding second demultiplexing data signal according to the reference voltage to generate a second decoded signal in NRZ format. The second decoded signal has an m-bit data portion (2 bits in this embodiment). In this embodiment, each of the second demultiplexed data signals has a data rate of 3.5 Gbaud.

[0021] In this embodiment, for each of the decoders 160, the second demultiplexer 166 includes P sampling switches 1661 (four sampling switches 1661 in this embodiment). Each sampling switch 1661 has a first terminal electrically connected to the buffer 165 to receive the data signal to be decoded, a second terminal providing a corresponding one of the second demultiplexed data signals, and a control terminal electrically connected to the ring counter 162 to receive a corresponding one of the bits of the count output. Each sampling switch 1661 is turned on when the corresponding bit in the count output is at the predetermined logic value (logic value "1" in this embodiment), and not turned on otherwise. For each sampling switch 1661, when the sampling switch 1661 is turned on, the feed data signal is transmitted through the sampling switch 1661 as the corresponding second demultiplexed data signal. It should also be noted that each of these analog-to-digital converters 167 is a successive approximation analog-to-digital converter.

[0022] For each of the decoders 160, the phase calibration circuit 168 is electrically connected to the analog-to-digital converters 167 to receive the first decoded signals and the second decoded signals, and is electrically connected to the ring counter 162 to receive the count output, and calibrates the first decoded signals and the second decoded signals according to the count output to generate a calibration signal having a data portion and an error portion. The data portion of the calibration signal is derived from the data portions of the first decoded signals and the data portions of the second decoded signals, and the data portion of the calibration signal is m×P bits (8 bits in this embodiment). The error portion of the calibration signal is derived from the error portion of the first decoded signal, and the error portion of the calibration signal is 1 bit. The pair of Q demultiplexers 169 (1:2 demultiplexers 169 in this embodiment) is electrically connected to the phase calibration circuit 168 to receive the calibration signal, and electrically connected to the 1 / Q divider 163 (1 / 2 divider 163 in this embodiment) to receive the third clock signal. Based on the third clock signal, the calibration signal is demultiplexed into a demultiplexed signal having a data portion and an error portion. The demultiplexed signal originates from the data portions of the first and second decoded signals, and the data portion of the demultiplexed signal is m×P×Q bits (16 bits in this embodiment). The demultiplexed signal originates from the error portion of the first decoded signal, and the error portion of the demultiplexed signal is Q bits wide (2 bits in this embodiment). The demultiplexed signals generated by the pair of Q demultiplexers 169 (1:2 demultiplexers 169 in this embodiment) of the decoder 160 cooperate to form a decoded output. In this embodiment, for each of the decoders 160, the data rate of the data portion of the calibration signal is 8 × 3.5 Gbps, and the data rate of the error portion of the calibration signal is 1 × 3.5 Gbps; the data rate of the data portion of the demultiplexing signal is 16 × 1.75 Gbps, and the data rate of the error portion of the demultiplexing signal is 2 × 1.75 Gbps.

[0023] The adaptive controller 17 is electrically connected to the 1:2 demultiplexer 169 (in this embodiment, the 1:2 demultiplexer 169) to receive the decoded output, and is electrically connected to the equalizer device 111, the voltage regulator 12, the phase interpolator 15, and the de-offsetter 161 of the decoder 160. It generates the output data signal Dout based on a data portion of the decoded output, the data portion of the decoded output originating from the data portions of the first decoded signals and the data portions of the second decoded signals generated by the analog-to-digital converters 167 of the decoders 160. The adaptive controller 17 also applies adaptive calibration to the equalizer device 111, the regulator 12, the phase interpolator 15, and the de-offsetters 161 of the decoder 160 based on "an error portion of the decoded output" derived from "error portions of the first decoded signals" and based on the data portion of the decoded output. This adjusts the gain of the channel compensator 11, the magnitude of the reference voltage, the phase shift of the interpolated clock signals, and the delay of the de-offset clock signals to obtain optimal eye diagram quality, correct swing of the input data signal, and optimal sampling position of the input data signal. In this embodiment, the data rate of the output data signal Dout is 64 × 1.75 Gbps.

[0024] In this embodiment, each of the first decoded signals and the second decoded signals has a plurality of samples arranged in a time sequence. The analog-to-digital converters 167 of the decoders 160 operate cyclically at a rate defined by a time interval corresponding to a frequency to generate the samples of the first decoded signals and the samples of the second decoded signals, the frequency being N times (for example, four times) the frequency of each interpolated clock signal. Referring to Table 1, which exemplifies the generation order of samples of the first decoded signal and samples of the second decoded signal in each operation cycle, D[] represents the data portion of a sample of the first decoded signal and the second decoded signal, which is one of the logic values ​​"00" (corresponding to a bit value -3), "01" (corresponding to a bit value -1), "10" (corresponding to a bit value +1), and "11" (corresponding to a bit value +3); and E[] represents the error portion of a sample of the first decoded signal, which is one of the logic values ​​"0" (corresponding to a bit value -1) and "1" (corresponding to a bit value +1). Table 1 3-bit analog-to-digital converter 2-bit analog-to-digital converter (I) 2-bit Analog-to-Digital Converter (II) 2-bit Analog-to-Digital Converter (III) Decoder (I) D[16×r+0] E[16×r+0] D[16×r+4] - D[16×r+8] - D[16×r+12] - Decoder (II) D[16×r+1] E[16×r+1] D[16×r+5] - D[16×r+9] - D[16×r+13] - Decoder (III) D[16×r+2] E[16×r+2] D[16×r+6] - D[16×r+10] - D[16×r+14] - Decoder (IV) D[16×r+3] E[16×r+3] D[16×r+7] - D[16×r+11] - D[16×r+15] - r: a non-negative integer

[0025] In this embodiment, as shown in Tables 2 and 3, the adaptive controller 17 applies adaptive calibration to the phase interpolator 15 to adjust the phase shift of the interpolated clock signals. It references a data portion D[a] and an error portion E[a] of a sample of the first decoded signals, a data portion D[a-1] of a sample of the first decoded signals and the second decoded signals, and a data portion D[a+1] of another sample of the first decoded signals and the second decoded signals. The sample of the first decoded signals and the second decoded signals is generated earlier by the time interval than the sample of the first decoded signals, and the other sample of the first decoded signals and the second decoded signals is generated later by the time interval than the sample of the first decoded signals. Table 2 condition D[a-1] D[a] D[a+1] E[a] phase (a) +3 +3 -3 +1 Delay (a) +3 +1 -3 +1 Delay (a) +1 +1 -1 +1 Delay (a) +3 -1 -3 +1 Delay (a) +1 -1 -1 +1 Delay (a) +3 -3 -3 +1 Delay (b) -3 +3 +3 -1 Delay (b) -1 +1 +1 -1 Delay (b) -3 +1 +3 -1 Delay (b) -1 -1 +1 -1 Delay (b) -3 -1 +3 -1 Delay (b) -3 -3 +3 -1 Delay (c) +1 +1 -3 +1 Delay (c) +1 -1 -3 +1 Delay (c) +1 -3 -3 +1 Delay (c) -1 -3 -3 +1 Delay (d) +1 +3 +3 -1 Delay (d) -1 +3 +3 -1 Delay (d) -1 +1 +3 -1 Delay (d) -1 -1 +3 -1 Delay Table 3 condition D[a-1] D[a] D[a+1] E[a] phase (i) +3 +3 -3 -1 in advance (i) +3 +1 -3 -1 in advance (i) +1 +1 -1 -1 in advance (i) +3 -1 -3 -1 in advance (i) +1 -1 -1 -1 in advance (i) +3 -3 -3 -1 in advance (ii) -3 +3 +3 +1 in advance (ii) -1 +1 +1 +1 in advance (ii) -3 +1 +3 +1 in advance (ii) -1 -1 +1 +1 in advance (ii) -3 -1 +3 +1 in advance (ii) -3 -3 +3 +1 in advance (iii) +3 +3 +1 -1 in advance (iii) +3 +3 -1 -1 in advance (iii) +3 +1 -1 -1 in advance (iii) +3 -1 -1 -1 in advance (iv) -3 +1 +1 +1 in advance (iv) -3 -1 +1 +1 in advance (iv) -3 -3 +1 +1 in advance (iv) -3 -3 -1 +1 in advance

[0026] As shown in Table 2, the adaptive controller 17 adjusts the phase shift of the interpolated clock signals to delay the phase of the interpolated clock signals when any of the following conditions are met: (a) "a bit value representing the data portion D[a-1] of a sample of the first decoded signal and the second decoded signal" and "a bit value representing the data portion D[a+1] of another sample of the first decoded signal and the second decoded signal" have the same numerical magnitude and opposite numerical signs (i.e., D[a-1] ≠ D[a+1] and |D[a-1]| = |D [a+1]|), "a bit value representing the data portion D[a] of a sample of the first decoded signal" is not greater than "the bit value representing the data portion D[a-1] of a sample of the first decoded signal and the second decoded signal" and not less than "the bit value representing the data portion D[a+1] of the other sample of the first decoded signal and the second decoded signal" (i.e., D[a-1]≧D[a]≧D[a+1]), and "a bit value representing the error portion E[a] of a sample of the first decoded signal" is positive (i.e., E[a]>0); (b) "The bit value representing the data portion D[a-1] of a sample of the first decoded signal and the second decoded signal" and "the bit value representing the data portion D[a+1] of another sample of the first decoded signal and the second decoded signal" have the same numerical magnitude and opposite numerical signs (i.e., D[a-1] ≠ D[a+1] and |D[a-1]| = |D[a+1]|), and "the bit value representing the data portion D[a] of a sample of the first decoded signal" The bit value is not less than the bit value representing the data portion D[a-1] of the sample of the first decoded signal and the second decoded signal and is not greater than the bit value representing the data portion D[a+1] of the other sample of the first decoded signal and the second decoded signal (i.e., D[a-1]≦D[a]≦D[a+1]), and the bit value representing the error portion E[a] of the sample of the first decoded signal is negative (i.e., E[a]<0).(c) The absolute value of "the bit value representing the data portion D[a-1] of a sample of the first decoded signal and the second decoded signal" is less than the absolute value of "the bit value representing the data portion D[a+1] of another sample of the first decoded signal and the second decoded signal" (i.e., |D[a-1]| < |D[a+1]|), and "the bit value representing the data portion D[a] of a sample of the first decoded signal" is not greater than "the bit value representing the data portion D[a-1] of a sample of the first decoded signal and the second decoded signal" and is not less than "the bit value representing the data portion D[a+1] of another sample of the first decoded signal and the second decoded signal" (i.e., D[a-1]). ≧D[a]≧D[a+1]), and "the bit value of the error portion E[a] of the sample of the first decoded signal" is positive (i.e., E[a]>0), excluding "the bit value of the data portion D[a-1] of the sample of the first decoded signal and the second decoded signal" and "the bit value of the data portion D[a+1] of the other sample of the first decoded signal and the second decoded signal" which have the same numerical sign (i.e., D[a-1]×D[a+1]>0) and "the bit value of the data portion D[a] of the sample of the first decoded signal" is equal to "the bit value of the data portion D[a-1] of the sample of the first decoded signal and the second decoded signal" (i.e., D[a]=D[a-1]);And (d) the absolute value of "the bit value representing the data portion D[a-1] of a sample of the first decoded signal and the second decoded signal" is less than the absolute value of "the bit value representing the data portion D[a+1] of another sample of the first decoded signal and the second decoded signal" (i.e., |D[a-1]| < |D[a+1]|), the absolute value of "the bit value representing the data portion D[a] of a sample of the first decoded signal" is not less than "the bit value representing the data portion D[a-1] of a sample of the first decoded signal and the second decoded signal" and is not greater than "the bit value representing the data portion D[a+1] of another sample of the first decoded signal and the second decoded signal" (i.e., D[a-1] ≦ D[a] ≦ D[a+1]). The statement states that "the bit value representing the error portion E[a] of the sample of the first decoded signal" is negative (i.e., E[a] < 0), excluding the fact that "the bit value representing the data portion D[a-1] of the sample of the first decoded signal and the second decoded signal" has the same numerical sign as "the bit value representing the data portion D[a+1] of the other sample of the first decoded signal and the second decoded signal" (i.e., D[a-1] × D[a+1] > 0) and "the bit value representing the data portion D[a] of the sample of the first decoded signal" is equal to "the bit value representing the data portion D[a-1] of the sample of the first decoded signal and the second decoded signal" (i.e., D[a] = D[a-1]).

[0027] As shown in Table 2, the adaptive controller 17 adjusts the phase shift of the interpolated clock signals to advance the phase of the interpolated clock signals when any of the following conditions are met: (i) The bit value of "the data portion D[a-1] representing a sample of the first decoded signal and the second decoded signal" and "the bit value of "the data portion D[a+1] representing another sample of the first decoded signal and the second decoded signal" have the same numerical magnitude and opposite numerical signs (i.e., D[a-1] ≠ D[a+1] and |D[a-1]| = |D[a+1]|), and the bit value of "the data portion D[a] representing a sample of the first decoded signal" has the same numerical magnitude and opposite numerical signs (i.e., D[a-1] ≠ D[a+1] and |D[a-1]| = |D[a+1]|), and the bit value of "the data portion D[a] representing a sample of the first decoded signal" has the same numerical magnitude and opposite numerical signs (i.e., D[a-1] ≠ D[a+1] and |D[a-1]| = |D[a+1]|). The bit value is not greater than the bit value representing the data portion D[a-1] of the sample of the first decoded signal and the second decoded signal and is not less than the bit value representing the data portion D[a+1] of the other sample of the first decoded signal and the second decoded signal (i.e., D[a-1] ≥ D[a] ≥ D[a+1]), and the bit value representing the error portion E[a] of the sample of the first decoded signal is negative (i.e., E[a] < 0); (ii) "The bit value representing the data portion D[a-1] of a sample of the first decoded signal and the second decoded signal" and "the bit value representing the data portion D[a+1] of another sample of the first decoded signal and the second decoded signal" have the same numerical magnitude and opposite numerical signs (i.e., D[a-1] ≠ D[a+1] and |D[a-1]| = |D[a+1]|), and "the bit value representing the data portion D[a] of a sample of the first decoded signal" have the same numerical magnitude and opposite numerical signs (i.e., D[a-1] ≠ D[a+1] and |D[a-1]| = |D[a+1]|). The bit value of "is not less than the bit value of the data portion D[a-1] of the sample representing the first decoded signal and the second decoded signal" and is not greater than the bit value of the data portion D[a+1] of the other sample representing the first decoded signal and the second decoded signal (i.e., D[a-1]≦D[a]≦D[a+1]), and the bit value of "the error portion E[a] of the sample representing the first decoded signal" is positive (i.e., E[a]>0);(iii) The absolute value of "the bit value representing the data portion D[a-1] of a sample of the first decoded signal and the second decoded signal" is greater than the absolute value of "the bit value representing the data portion D[a+1] of another sample of the first decoded signal and the second decoded signal" (i.e., |D[a-1]| > |D[a+1]|), and the absolute value of "the bit value representing the data portion D[a] of a sample of the first decoded signal" is not greater than the absolute value of "the bit value representing the data portion D[a-1] of a sample of the first decoded signal and the second decoded signal" and is not less than the absolute value of "the bit value representing the data portion D[a+1] of another sample of the first decoded signal and the second decoded signal" (i.e., D[a-1]). ≧D[a]≧D[a+1]), and "the bit value of the error portion E[a] of the sample of the first decoded signal" is negative (i.e., E[a] < 0), excluding "the bit value of the data portion D[a-1] of the sample of the first decoded signal and the second decoded signal" and "the bit value of the data portion D[a+1] of the other sample of the first decoded signal and the second decoded signal" which have the same numerical sign (i.e., D[a-1] × D[a+1] > 0) and "the bit value of the data portion D[a] of the sample of the first decoded signal" is equal to "the bit value of the data portion D[a+1] of the other sample of the first decoded signal and the second decoded signal" (i.e., D[a] = D[a+1]);And (iv) the absolute value of "the bit value representing the data portion D[a-1] of a sample of the first decoded signal and the second decoded signal" is greater than the absolute value of "the bit value representing the data portion D[a+1] of another sample of the first decoded signal and the second decoded signal" (i.e., |D[a-1]|>|D[a+1]|), the absolute value of "the bit value representing the data portion D[a] of a sample of the first decoded signal" is not less than "the bit value representing the data portion D[a-1] of a sample of the first decoded signal and the second decoded signal" and is not greater than "the bit value representing the data portion D[a+1] of the other sample of the first decoded signal and the second decoded signal" (i.e., D[a-1]≦D[a]≦D[a+1]). ), and "the bit value representing the error portion E[a] of the sample of the first decoded signal" is positive (i.e., E[a] > 0), excluding "the bit value representing the data portion D[a-1] of the sample of the first decoded signal and the second decoded signal" and "the bit value representing the data portion D[a+1] of the other sample of the first decoded signal and the second decoded signal" having the same numerical sign (i.e., D[a-1] × D[a+1] > 0) and "the bit value representing the data portion D[a] of the sample of the first decoded signal" is equal to "the bit value representing the data portion D[a+1] of the other sample of the first decoded signal and the second decoded signal" (i.e., D[a] = D[a+1]).

[0028] Otherwise, if the above conditions (a) to (d) and conditions (i) to (iv) are not met, the adaptive controller 17 will not adjust the phase displacement.

[0029] Referring to Figures 1, 3 and 4, in a single view 200 of the receiver described in this embodiment, a block 21 represents the data portion D[a] with a value of +3. As shown in Figure 4, taking the data portions D[a-1], D[a], and D[a+1] as -3, +3 and +3 respectively as shown by curve 211 as an example: when the value of the error portion E[a] is negative, the phase of the interpolated clock signals is relatively ahead of a locking point of the clock data recovery circuit, and the adaptive controller 17 delays the phase of the interpolated clock signals according to Table 2; when the value of the error portion E[a] is positive, the phase of the interpolated clock signals is relatively behind the locking point of the clock data recovery circuit, and the adaptive controller 17 advances the phase of the interpolated clock signals according to Table 3. Taking the data portions D[a-1], D[a], and D[a+1] as +3, +3, and -3 respectively, as shown in curve 212, as an example: when the value of the data portion E[a] is negative, the phase of the interpolated clock signals is relatively ahead of the locking point of the clock data recovery circuit, and the adaptive controller 17 delays the phase of the interpolated clock signals according to Table 2; when the value of the data portion E[a] is positive, the phase of the interpolated clock signals is relatively behind the locking point of the clock data recovery circuit, and the adaptive controller 17 advances the phase of the interpolated clock signals according to Table 3. Taking the data portions D[a-1], D[a], and D[a+1] as -1, +3, and +3 respectively (as shown in curve 213), and the data portions D[a-1], D[a], and D[a+1] as +1, +3, and +3 respectively (as shown in curve 214) as examples: When the value of the bit representing the error portion E[a] is negative, the phase of the interpolated clock signals is relatively ahead of the locking point of the clock data recovery circuit, and the adaptive controller 17 will delay the phase of the interpolated clock signals according to Table 2; when the value of the bit representing the error portion E[a] is positive, the phase of the interpolated clock signals may be relatively ahead or behind the locking point of the clock data recovery circuit, and the adaptive controller 17 will maintain the phase of the interpolated clock signals unchanged.Taking the data portions D[a-1], D[a], and D[a+1] as +3, +3, and -1 respectively (as shown in curve 215), and the data portions D[a-1], D[a], and D[a+1] as +3, +3, and +1 respectively (as shown in curve 216) as examples: When the value of the bit representing the error portion E[a] is positive, the phase of the interpolated clock signals may be relatively ahead or behind the locking point of the clock data recovery circuit, and the adaptive controller 17 will maintain the phase of the interpolated clock signals unchanged; when the value of the bit representing the error portion E[a] is negative, the phase of the interpolated clock signals is relatively behind the locking point of the clock data recovery circuit, and the adaptive controller 17 will advance the phase of the interpolated clock signals according to Table 3.

[0030] Referring to Figures 1, 3 and 5, in a block 22 of the eye diagram 200 of the receiver described in this embodiment, the bit value of the data portion D[a] is +1. As shown in Figure 5, taking the data portions D[a-1], D[a], and D[a+1] as -3, +1, and +3 respectively (as shown by curve 221), and the data portions D[a-1], D[a], and D[a+1] as -1, +1, and +1 respectively (as shown by curve 222) as examples: When the value of the bit representing the error portion E[a] is negative, the phase of the interpolated clock signals is relatively ahead of the locking point of the clock data recovery circuit, and the adaptive controller 17 delays the phase of the interpolated clock signals according to Table 2; when the value of the bit representing the error portion E[a] is positive, the phase of the interpolated clock signals is relatively behind the locking point of the clock data recovery circuit, and the adaptive controller 17 advances the phase of the interpolated clock signals according to Table 3. Taking the data portions D[a-1], D[a], and D[a+1] as +3, +1, and -3 respectively (as shown in curve 223), and the data portions D[a-1], D[a], and D[a+1] as +1, +1, and -1 respectively (as shown in curve 224) as examples: When the value of the bit representing the error portion E[a] is positive, the phase of the interpolated clock signals is relatively ahead of the locking point of the clock data recovery circuit, and the adaptive controller 17 delays the phase of the interpolated clock signals according to Table 2; when the value of the bit representing the error portion E[a] is negative, the phase of the interpolated clock signals is relatively behind the locking point of the clock data recovery circuit, and the adaptive controller 17 advances the phase of the interpolated clock signals according to Table 3. Taking the data portions D[a-1], D[a], and D[a+1] as an example, where the bit values ​​are -1, +1, and +3 respectively (as shown in curve 226): When the bit value representing the error portion E[a] is negative, the phase of the interpolated clock signals is relatively ahead of the locking point of the clock data recovery circuit, and the adaptive controller 17 will delay the phase of the interpolated clock signals according to Table 2; when the bit value representing the error portion E[a] is positive, the phase of the interpolated clock signals may be relatively ahead or behind the locking point of the clock data recovery circuit, and the adaptive controller 17 will maintain the phase of the interpolated clock signals unchanged.Taking the data portions D[a-1], D[a], and D[a+1] as +1, +1, and -3 respectively, as shown in curve 227, as an example: when the value of the bit representing the error portion E[a] is positive, the phase of the interpolated clock signals is relatively ahead of the locking point of the clock data recovery circuit, and the adaptive controller 17 will delay the phase of the interpolated clock signals according to Table 2; when the value of the bit representing the error portion E[a] is negative, the phase of the interpolated clock signals may be relatively ahead or behind the locking point of the clock data recovery circuit, and the adaptive controller 17 will maintain the phase of the interpolated clock signals unchanged. Taking the data portions D[a-1], D[a], and D[a+1] as +3, +1, and -1 respectively, as shown in curve 228, as an example: when the value of the bit representing the error portion E[a] is positive, the phase of the interpolated clock signals may be relatively ahead or behind the locking point of the clock data recovery circuit, and the adaptive controller 17 will maintain the phase of the interpolated clock signals unchanged; when the value of the bit representing the error portion E[a] is negative, the phase of the interpolated clock signals is relatively behind the locking point of the clock data recovery circuit, and the adaptive controller 17 will advance the phase of the interpolated clock signals according to Table 3.

[0031] In this eye diagram 200, the block representing the bit value of data portion D[a] as -1 and the block representing the bit value of data portion D[a] as -1 can be inferred from the above description of the region 21 and the block 22, so they will not be described again hereafter.

[0032] In summary, by means of the adaptive controller 17, when "the bit value of the data portion D[a-1] representing the sample of the first decoded signal and the second decoded signal" and "the bit value of the data portion D[a+1] representing the other sample of the first decoded signal and the second decoded signal" have the same numerical magnitude and opposite numerical sign (e.g., conditions (a), (b), (i), and (ii)), and when "the bit value of the data portion D[a+1] representing the other sample of the first decoded signal and the second decoded signal" has the same numerical magnitude and opposite numerical sign (e.g., conditions (a), (b), (i), and (ii)), and when "the bit value of the data portion D[a+1] representing the other sample of the first decoded signal and the second decoded signal" has the same numerical magnitude and opposite numerical sign (e.g., conditions (a), (b), (i), and (ii)), When the absolute value of the bit value of the data portion D[a-1] of the sample of the second decoded signal is not equal to the absolute value of the bit value of the data portion D[a+1] of the other sample of the first decoded signal and the second decoded signal (e.g., conditions (c), (d), (iii), and (iv)), the phase of the interpolated clock signal is adjusted to change the phase, so that the clock data recovery circuit has good performance and the receiver described in this embodiment has a low bit error rate.

[0033] It should be noted that the method of the receiver in this embodiment for changing the phase of the interpolated clock signals can be applied to other receivers (where an input data signal is decoded based on a clock signal into a decoded output containing a plurality of sequentially generated samples, each of the samples containing a data portion, and each of at least some of the samples having an error portion) to change the phase of the clock signal.

[0034] However, the above description is only an embodiment of the present invention and should not be construed as limiting the scope of the present invention. Any simple equivalent changes and modifications made in accordance with the scope of the patent application and the contents of the patent specification shall still fall within the scope of the patent of the present invention. [Simplified Explanation of the Diagram]

[0035] Other features and effects of the present invention will be clearly presented with reference to the illustrated embodiments, wherein: FIG1 is a circuit block diagram illustrating an embodiment of a receiver of the present invention; FIG2 is a block diagram illustrating a channel compensator in this embodiment; FIG3 is a schematic diagram illustrating an eye diagram in this embodiment; FIG4 is a schematic diagram illustrating that the bit value of a data portion representing a sample of a plurality of first decoded signals in a block of the eye diagram in this embodiment is +3; and FIG5 is a schematic diagram illustrating that the bit value of the data portion representing the sample of the first decoded signals in the block of the eye diagram in this embodiment is +1.

Claims

1. A receiver comprising: a phase interpolator for receiving an input clock and applying phase interpolation to the input clock to generate N interpolated clock signals, wherein N ≥ 2, and each of the interpolated clock signals having an adjustable phase shift relative to the input clock; a decoder device comprising N decoders; each of the N decoders being connected to the phase interpolator to receive a corresponding one of the N interpolated clock signals; the N decoders cooperating with each other to receive an input data signal in Pulse Amplitude Modulation (PAM)-M format, and cooperating with each other to demultiplex the input data signal into N first demultiplexed data signals respectively provided by the decoders, wherein M ≥ 3, by referring to the N interpolated clock signals; The N decoders demultiplex the first demultiplexed data signal they provide into P second demultiplexed data signals, and decode the P second demultiplexed data signals into P decoded signals, where P ≥ 2. Each of the P decoded signals has a plurality of sequentially generated samples, each of the samples has a data portion, and each of the samples in at least one of the P decoded signals also has an error portion. An adaptive controller is electrically connected to the decoder device to receive a decoded output from the decoded signals generated by the N decoders, and is electrically connected to the phase interpolator. Based on the decoded signals, the adaptive controller generates the decoded output and applies adaptive correction to the phase interpolator by referencing the data portion and error portion of a first sample of the decoded signals, the data portion of a second sample of the decoded signals generated before the first sample, and the data portion of a third sample of the decoded signals generated after the first sample, thereby adjusting the phase shifts of the interpolated clock signals. When the absolute value of a bit value representing the data portion of the second sample of the decoded signals is not equal to the absolute value of a bit value representing the data portion of the third sample of the decoded signals, the adaptive controller adjusts the phase shifts of the N interpolated clock signals to change the phase of the N interpolated clock signals.

2. The receiver as described in claim 1, wherein, The adaptive controller adjusts the phase shifts of the N interpolated clock signals to delay the phase of the interpolated clock signals when the following conditions are met: the absolute value of the bit value of the data portion of the second sample representing the decoded signals is less than the absolute value of the bit value of the data portion of the third sample representing the decoded signals; a bit value of the data portion of the first sample representing the decoded signals is not greater than the bit value of the data portion of the second sample representing the decoded signals and not less than the bit value of the data portion of the third sample representing the decoded signals; and the bit value of the data portion of the first sample representing the decoded signals is positive.

3. The receiver as described in claim 1, wherein, The adaptive controller adjusts the phase shifts of the N interpolated clock signals to delay the phase of the interpolated clock signals when the following conditions are met: the absolute value of the bit value of the data portion of the second sample representing the decoded signals is less than the absolute value of the bit value of the data portion of the third sample representing the decoded signals; a bit value of the data portion of the first sample representing the decoded signals is not less than the bit value of the data portion of the second sample representing the decoded signals and not greater than the bit value of the data portion of the third sample representing the decoded signals; and the bit value of the error portion of the first sample representing the decoded signals is negative.

4. The receiver as described in claim 1, wherein, The adaptive controller adjusts the phase shifts of the N interpolated clock signals to advance the phase of the interpolated clock signals when the following conditions are met: the absolute value of the bit value of the data portion of the second sample representing the decoded signals is greater than the absolute value of the bit value of the data portion of the third sample representing the decoded signals; a bit value of the data portion of the first sample representing the decoded signals is not greater than the bit value of the data portion of the second sample representing the decoded signals and not less than the bit value of the data portion of the third sample representing the decoded signals; and the bit value of the error portion of the first sample representing the decoded signals is negative.

5. The receiver as described in claim 1, wherein, The adaptive controller adjusts the phase shifts of the N interpolated clock signals to advance the phase of the interpolated clock signals when the following conditions are met: the absolute value of the bit value of the data portion of the second sample representing the decoded signals is greater than the absolute value of the bit value of the data portion of the third sample representing the decoded signals; a bit value of the data portion of the first sample representing the decoded signals is not less than the bit value of the data portion of the second sample representing the decoded signals and not greater than the bit value of the data portion of the third sample representing the decoded signals; and the bit value of the error portion of the first sample representing the decoded signals is positive.

6. The receiver as described in claim 1, wherein, When the bit value of the data portion of the second sample representing the decoded signals has the same numerical value but opposite numerical sign as the bit value of the data portion of the third sample representing the decoded signals, the adaptive controller adjusts the phase shift of the N interpolated clock signals to change the phase of the N interpolated clock signals.

7. The receiver as described in claim 6, wherein, The adaptive controller adjusts the phase shifts of the N interpolated clock signals to delay the phase of the interpolated clock signals when the following conditions are met: the bit value of the data portion of the second sample of the decoded signals and the bit value of the data portion of the third sample of the decoded signals have the same numerical magnitude and opposite numerical signs; a bit value of the data portion of the first sample of the decoded signals is not greater than the bit value of the data portion of the second sample of the decoded signals and not less than the bit value of the data portion of the third sample of the decoded signals; and the bit value of the error portion of the first sample of the decoded signals is positive.

8. The receiver as described in claim 6, wherein, The adaptive controller adjusts the phase shifts of the N interpolated clock signals to delay the phase of the interpolated clock signals when the following conditions are met: the bit value of the data portion of the second sample representing the decoded signals and the bit value of the data portion of the third sample representing the decoded signals have the same numerical value and opposite numerical signs; a bit value of the data portion of the first sample representing the decoded signals is not less than the bit value of the data portion of the second sample representing the decoded signals and not greater than the bit value of the data portion of the third sample representing the decoded signals; and the bit value of the error portion of the first sample representing the decoded signals is negative.

9. The receiver as described in claim 6, wherein, The adaptive controller adjusts the phase shifts of the N interpolated clock signals to advance the phase of the interpolated clock signals when the following conditions are met: the bit value of the data portion of the second sample of the decoded signals and the bit value of the data portion of the third sample of the decoded signals have the same numerical value and opposite numerical signs; a bit value of the data portion of the first sample of the decoded signals is not greater than the bit value of the data portion of the second sample of the decoded signals and not less than the bit value of the data portion of the third sample of the decoded signals; and the bit value of the error portion of the first sample of the decoded signals is negative.

10. The receiver as described in claim 6, wherein, The adaptive controller adjusts the phase shifts of the N interpolated clock signals to advance the phase of the interpolated clock signals when the following conditions are met: the bit value of the data portion of the second sample representing the decoded signals and the bit value of the data portion of the third sample representing the decoded signals have the same numerical value and opposite numerical signs; a bit value of the data portion of the first sample representing the decoded signals is not less than the bit value of the data portion of the second sample representing the decoded signals and not greater than the bit value of the data portion of the third sample representing the decoded signals; and the bit value of the error portion of the first sample representing the decoded signals is positive.

11. A data receiving method, performed by a receiver, comprising the steps of: (A) decoding an input data signal into a decoded output having a plurality of sequentially generated samples based on a clock signal, each sample having a data portion and each of at least some of the samples having an error portion; and (B) adjusting the phase of the clock signal with reference to the data portion and the error portion of a first sample of the decoded output, the data portion of a second sample of the decoded output generated before the first sample was generated, and the data portion of a third sample of the decoded output generated after the first sample was generated; wherein, In step (B), when the absolute value of a bit value representing the data portion of the second sample of the decoded output is not equal to the absolute value of a bit value representing the data portion of the third sample of the decoded output, the phase of the clock signal is changed.

12. The data receiving method as described in claim 11, wherein, In step (B), the phase of the clock signal will be delayed when the following conditions are met: the absolute value of the bit value of the data portion of the second sample of the decoded output is less than the absolute value of the bit value of the data portion of the third sample of the decoded output; a bit value of the data portion of the first sample of the decoded output is not greater than the bit value of the data portion of the second sample of the decoded output and not less than the bit value of the data portion of the third sample of the decoded output; and the bit value of the error portion of the first sample of the decoded output is positive.

13. The data receiving method as described in claim 11, wherein, In step (B), the phase of the clock signal will be delayed when the following conditions are met: the absolute value of the bit value of the data portion of the second sample of the decoded output is less than the absolute value of the bit value of the data portion of the third sample of the decoded output; a bit value of the data portion of the first sample of the decoded output is not less than the bit value of the data portion of the second sample of the decoded output and not greater than the bit value of the data portion of the third sample of the decoded output; and the bit value of the error portion of the first sample of the decoded output is negative.

14. The data receiving method as described in claim 11, wherein, In step (B), the phase of the clock signal will be advanced when the following conditions are met: the absolute value of the bit value of the data portion of the second sample of the decoded output is greater than the absolute value of the bit value of the data portion of the third sample of the decoded output; a bit value of the data portion of the first sample of the decoded output is not greater than the bit value of the data portion of the second sample of the decoded output and not less than the bit value of the data portion of the third sample of the decoded output; and the bit value of the error portion of the first sample of the decoded output is negative.

15. The data receiving method as described in claim 11, wherein, In step (B), the phase of the clock signal will be advanced when the following conditions are met: the absolute value of the bit value of the data portion of the second sample of the decoded output is greater than the absolute value of the bit value of the data portion of the third sample of the decoded output; a bit value of the data portion of the first sample of the decoded output is not less than the bit value of the data portion of the second sample of the decoded output and not greater than the bit value of the data portion of the third sample of the decoded output; and the bit value of the error portion of the first sample of the decoded output is positive.

16. The data receiving method as described in claim 11, wherein, In step (B), when the bit value of the data portion representing the second sample of the decoded output has the same numerical value and opposite numerical sign as the bit value of the data portion representing the third sample of the decoded output, the phase of the clock signal is also changed.

17. The data receiving method as described in claim 16, wherein, In step (B), the phase of the clock signal will be delayed when the following conditions are met: the bit value representing the data portion of the second sample of the decoded output and the bit value representing the data portion of the third sample of the decoded output have the same numerical magnitude and opposite numerical signs; a bit value representing the data portion of the first sample of the decoded output is not greater than the bit value representing the data portion of the second sample of the decoded output and not less than the bit value representing the data portion of the third sample of the decoded output; and a bit value representing the error portion of the first sample of the decoded output is positive.

18. The data receiving method as described in claim 16, wherein, In step (B), the phase of the clock signal will be delayed when the following conditions are met: the bit value representing the data portion of the second sample of the decoded output and the bit value representing the data portion of the third sample of the decoded output have the same numerical magnitude and opposite numerical signs; a bit value representing the data portion of the first sample of the decoded output is not less than the bit value representing the data portion of the second sample of the decoded output and not greater than the bit value representing the data portion of the third sample of the decoded output; and a bit value representing the error portion of the first sample of the decoded output is negative.

19. The data receiving method as described in claim 16, wherein, In step (B), the phase of the clock signal will be advanced when the following conditions are met: the bit value representing the data portion of the second sample of the decoded output and the bit value representing the data portion of the third sample of the decoded output have the same numerical magnitude and opposite numerical signs; a bit value representing the data portion of the first sample of the decoded output is not greater than the bit value representing the data portion of the second sample of the decoded output and not less than the bit value representing the data portion of the third sample of the decoded output; and a bit value representing the error portion of the first sample of the decoded output is negative.

20. The data receiving method as described in claim 16, wherein, In step (B), the phase of the clock signal will be advanced when the following conditions are met: the bit value of the data portion of the second sample of the decoded output and the bit value of the data portion of the third sample of the decoded output have the same numerical magnitude and opposite numerical signs; a bit value of the data portion of the first sample of the decoded output is not less than the bit value of the data portion of the second sample of the decoded output and not greater than the bit value of the data portion of the third sample of the decoded output; and a bit value of the error portion of the first sample of the decoded output is positive.

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