Semiconductor structure and method for forming the same

Abstract

A semiconductor structure and the method for forming the same are provided. The semiconductor structure includes a substrate, word line structures disposed on the substrate, and an insulating layer surrounding each word line structure. Each word line structure includes a conductive layer disposed on a lower portion of the word line structure, filling layer disposed on an upper layer of the word line structure, and a block layer surrounding the filling layer. The block layer is a hydrogen-rich dielectric layer.

Description

Technical Field

[0001] This invention relates to semiconductor structures, and more particularly to semiconductor structures and methods for forming the same, which reduce leakage current in word line structures. Prior Technology

[0002] Dynamic Random Access Memory (DRAM) devices are widely used in consumer electronics. To increase the component density within DRAM devices and improve their overall performance, current DRAM manufacturing technologies continue to strive towards miniaturization of component size.

[0003] However, as device dimensions continue to shrink, many challenges arise. For example, during the etching process in semiconductor manufacturing, defects and dangling bonds can easily form in the silicon lattice, leading to leakage current. Therefore, the industry still needs to improve the manufacturing methods of dynamic random access memory devices to overcome the problems caused by the shrinking device size. Summary of the Invention

[0004] Some embodiments disclosed herein provide a semiconductor structure comprising: a substrate, a plurality of word line structures disposed on the substrate, and an insulating layer covering each word line structure. Each word line structure includes a conductive layer disposed at the lower part of the word line structure, a filling layer disposed at the upper part of the word line, and a barrier layer surrounding the filling layer. The barrier layer is a hydrogen-rich dielectric layer.

[0005] Some embodiments disclosed herein provide a method for forming a semiconductor structure, comprising: providing a substrate; and forming a word line structure in the substrate. Forming the word line structure includes: forming a conductive layer at the bottom of the word line structure; and forming a barrier layer and a fill layer on the conductive layer. The barrier layer is a hydrogen-rich dielectric layer. Simple Explanation of the Diagram

[0006] Figures 1-6 are cross-sectional views showing the formation of semiconductor structures at different stages according to some embodiments of the present invention. Figure 7 is a partially enlarged cross-sectional view of the semiconductor structure in Figure 6, according to some embodiments of the present invention. Implementation

[0007] The present disclosure is described more fully below with reference to the accompanying drawings of embodiments of the invention. However, the present disclosure may be implemented in various different ways and should not be limited to the embodiments described herein. The thickness of layers and regions in the drawings may be enlarged for clarity, and the same or similar reference numerals in the drawings denote the same or similar elements.

[0008] During the etching of character lines, defects can easily form in the silicon lattice, resulting in dangling bonds and leakage current. This invention addresses these defects by forming a hydrogen-rich film, thereby reducing leakage current.

[0009] According to some embodiments of the present invention, Figures 1-6 are cross-sectional views showing the formation of a semiconductor structure at different stages. Figure 7 is a partially enlarged cross-sectional view of the semiconductor structure in Figure 6, according to some embodiments of the present invention. In some embodiments, the semiconductor structure is part of a dynamic random access memory array.

[0010] First, as shown in Figure 1, a substrate 100 is provided. In some embodiments, the substrate 100 may be an elemental semiconductor substrate, such as a silicon substrate or a germanium substrate; or a compound semiconductor substrate, such as a silicon carbide substrate or a gallium arsenide substrate. In some embodiments, the substrate 100 may be a semiconductor-on-insulator substrate.

[0011] As shown in Figure 1, a first capping layer 112 is formed on the substrate 100. In some embodiments, the first capping layer 112 may comprise a dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, or a dielectric material with a high dielectric constant. In this embodiment, the first capping layer 112 is silicon oxide to facilitate subsequent selective etching. In some embodiments, the formation of the first capping layer 112 may include a deposition process, such as chemical vapor deposition, molecular beam epitaxy, etc.

[0012] As shown in Figure 1, the substrate 100 includes a first region 100A and a second region 100B. An insulating layer 102 is formed in the second region 100B, and an insulating layer 103 is formed in the first region 100A. In some embodiments, the insulating layers 102 and 103 can be used to reduce interference between subsequently formed character line structures, and can be, for example, a single-layer film. In some embodiments, the insulating layer 103 can be an isolation structure formed of multiple films, such as a shallow trench isolation structure, but is not limited thereto.

[0013] In some embodiments, insulating layers 102 and 103 may comprise nitrides or oxides, such as silicon oxide, silicon nitride, silicon oxynitride, and / or combinations thereof. In some embodiments, insulating layers 102 and 103 may also be in-situ vapor-generated oxide layers, but the invention is not limited thereto. In some embodiments, the formation of insulating layers 102 and 103 may include patterning processes (e.g., lithography and etching processes), deposition processes, and planarization processes (e.g., chemical mechanical polishing). Etching processes may include dry etching processes, wet etching processes, or other suitable etching processes. For example, plasma etching, ion polishing reactive ion etching, neutral particle beam etching, and inductively coupled plasma etching. Etching processes may also be purely chemical etching, purely physical etching, or any combination thereof.

[0014] As shown in Figure 1, a conductive layer C is formed on insulating layer 102 and / or insulating layer 103. In some embodiments, conductive layer C serves as a gate and sequentially includes a first barrier layer 104, a metal layer 106, a second barrier layer 108, and a semiconductor layer 110 from substrate 100.

[0015] In some embodiments, a first barrier material and a metal material are first compliantly deposited, and then the first barrier material and the metal material are etched back to a predetermined depth to obtain a first barrier layer 104 and a metal layer 106. Next, a second barrier material is deposited on the metal layer 106, and then the second barrier material is etched back to obtain a second barrier layer 108. Next, a semiconductor material is deposited on the second barrier layer 108, and then the semiconductor material is etched back to obtain a semiconductor layer 110. The deposition process and etching process are similar to those described above and will not be repeated here.

[0016] In some embodiments, the first barrier layer 104 and the second barrier layer 108 may comprise tungsten nitride, titanium nitride, or tantalum nitride, etc. In some embodiments, the metal layer 106 may comprise a metal material or a metal alloy, such as tungsten or tungsten nitride, etc. In some embodiments, the semiconductor layer 110 may comprise a semiconductor material, such as polysilicon.

[0017] As shown in Figures 2-4, a barrier layer 114 and a filler layer 116 are formed on the conductive layer C. In this embodiment, the barrier layer 114 is a hydrogen-rich material to repair lattice defects with hydrogen atoms and prevent leakage current. In some embodiments, the barrier layer 114 can be a hydrogen-rich dielectric material, such as hydrogen-rich silicon oxide, hydrogen-rich silicon nitride, hydrogen-rich silicon oxynitride, or a hydrogen-rich dielectric material with a high dielectric constant. In this embodiment, the barrier layer 114 is hydrogen-rich silicon nitride.

[0018] In some embodiments, the filler layer 116 may be a dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, or a dielectric material with a high dielectric constant. In this embodiment, the filler layer 116 is silicon nitride. In some embodiments, the filler layer 116 may be a hydrogen-containing or hydrogen-free material. In this embodiment, the filler layer 116 and the barrier layer 114 are silicon nitrides with different hydrogen ratios. For example, the barrier layer 114 has a higher hydrogen ratio than the filler layer 116. In other embodiments, the filler layer 116 is a hydrogen-free material.

[0019] In some embodiments, after the conductive layer C is compliantly deposited with a barrier material (Figure 2), a filler material is compliantly deposited on the barrier material (Figure 3). Then, the filler material and the barrier material are etched back to form a barrier layer 114 and a filler layer 116 (Figure 4). The deposition and etch-back processes are similar to those described above and will not be repeated here.

[0020] It should be noted that the first capping layer 112 illustrated in this embodiment is silicon oxide, and therefore can serve as an etch stop layer in the etch-back process. Furthermore, the barrier layer 114 and the fill layer 116 are silicon nitrides with different hydrogen ratios, and therefore have different etch rates, resulting in a depression O on the formed barrier layer 114. That is, in Figure 4, the top surface of the barrier layer 114 is lower than the top surface of the fill layer 116. The barrier layer 114 is disposed on a portion of the sidewalls and bottom of the fill layer 116.

[0021] As shown in Figure 5, a second capping layer 118 is formed on the barrier layer 114 and the first capping layer 112. In some embodiments, the second capping layer 118 includes a main body portion 118b extending on the first capping layer 112 and an extension portion 118e extending from the bottom surface of the main body portion 118b into the aforementioned recess O. In some embodiments, the extension portion 118e is located on a portion of the sidewall of the filler layer 116 and contacts the barrier layer 114. In some embodiments, the bottom surface of the extension portion 118e is lower than the top surface of the filler layer 116. In some embodiments, the second capping layer 118 covers the top surface of the filler layer 116 and a portion of the sidewall. That is, the second capping layer 118, together with the barrier layer 114, covers the entire filler layer 116.

[0022] In some embodiments, depending on the aspect ratio of the recess O, the extension 118e may or may not form an air gap 118o therein. For example, in the enlarged schematic diagram of Figure 7, the extension 118e may form an air gap 118o therein.

[0023] In this embodiment, the second capping layer 118 is a hydrogen-rich material to repair lattice defects on the substrate surface with hydrogen atoms, thereby further preventing leakage current. In some embodiments, the second capping layer 118 can be a hydrogen-rich dielectric layer, which may be the same as or different from the barrier layer 114, such as hydrogen-rich silicon oxide, hydrogen-rich silicon nitride, hydrogen-rich silicon oxynitride, or a hydrogen-rich dielectric material with a high dielectric constant. In this embodiment, the second capping layer 118 is hydrogen-rich silicon nitride.

[0024] In some embodiments, the second capping layer 118 and the barrier layer 114 can be silicon nitride with the same or different hydrogen ratios. When the hydrogen ratios are the same, there will be no boundary between the second capping layer 118 and the barrier layer 114; that is, the second capping layer 118 and the barrier layer 114 can be considered to cover all side, top, and bottom surfaces of the filling layer 116. When the hydrogen ratios are different, the second capping layer 118 can have a higher or lower hydrogen ratio than the barrier layer 114. In some embodiments, the formation of the second capping layer 118 includes a deposition process similar to that described above, which will not be repeated here.

[0025] As shown in Figure 6, a third capping layer 120 is formed on the second capping layer 118. In this embodiment, the third capping layer 120 can serve as a diffusion barrier layer, preventing hydrogen atoms from diffusing to the outside, which is beneficial for hydrogen atom capture and further prevents leakage current. In some embodiments, the third capping layer 120 can be a dielectric layer, such as silicon oxide, silicon nitride, silicon oxynitride, or a dielectric material with a high dielectric constant. In some embodiments, the formation of the third capping layer 120 includes a deposition process similar to that described above, which will not be repeated here.

[0026] Figure 7 is a partially enlarged schematic diagram of Figure 6. As shown in Figure 7, the filler layer 116 has an air gap 116 therein. In a typical character line structure, the filler layer 116 has a large aspect ratio, thus easily creating an air gap 116o therein. Furthermore, in different embodiments, the extension 118e in the second cover layer 118 may or may not have an air gap 118o therein, depending on its aspect ratio.

[0027] Continuing from the above, embodiments of the present invention improve defects in the silicon lattice and further reduce leakage current by forming a film with a hydrogen-rich dielectric layer in the character line structure.

[0028] Specifically, the semiconductor structure provided in this embodiment of the invention includes a substrate, a word line structure disposed in the substrate, and an insulating layer covering the word line. The word line structure includes a conductive layer at the bottom and a filling layer at the top. The word line structure also includes a barrier layer extending from the sidewalls and bottom of the filling layer, and the barrier layer is a hydrogen-rich dielectric layer.

[0029] It is understandable that additional components, such as contacts, capacitors, metal layers, etc., can be formed after the character line structure is formed to complete the fabrication of memory elements (such as dynamic random access memory).

[0030] In summary, the embodiments of the present invention repair lattice defects and prevent leakage current by using a barrier layer with a hydrogen-rich dielectric layer. Furthermore, the embodiments of the present invention prevent hydrogen atom diffusion by using a capping layer with a hydrogen-rich dielectric layer, further capturing hydrogen atoms to repair lattice defects and preventing leakage current even more. Therefore, reliability and manufacturing yield are improved.

[0031] While the present invention has been disclosed above with reference to the foregoing embodiments, it is not intended to limit the invention. Those skilled in the art can make modifications and refinements without departing from the spirit and scope of the invention. Therefore, the scope of protection of this invention shall be determined by the appended claims.

[0032] 100:Substrate 100A: Zone 1 100B: Second Zone 102: Insulation layer 103: Insulation layer 104: First Barrier Layer 106: Metal layer 108: Second Barrier Layer 110: Semiconductor layer 112: First cap layer 114: Barrier Layer 116: Fill layer 116o: air gap 118: Second cap layer 118b: Main body 118e: Extension 118o: air gap 120: Third cap layer C: Conductive layer O: Depression

Claims

1. A semiconductor structure, comprising: One substrate; Multiple character line structures are disposed in the substrate. Each character line structure includes: a conductive layer disposed at the lower part of the character line structure; a filling layer disposed at the upper part of the character line structure; a barrier layer surrounding the filling layer, wherein the barrier layer is a hydrogen-rich dielectric layer; and an insulating layer covering each of the character line structures.

2. The semiconductor structure as claimed in claim 1, wherein the barrier layer is disposed on the sidewalls and bottom of a portion of the fill layer.

3. The semiconductor structure as claimed in claim 1, wherein the top surface of the barrier layer is lower than the top surface of the fill layer.

4. The semiconductor structure as described in claim 1, further comprising: A first cover layer is disposed on the substrate; And a second cover layer disposed on the first cover layer.

5. The semiconductor structure as described in claim 4, wherein the second capping layer is another hydrogen-rich dielectric layer.

6. The semiconductor structure as claimed in claim 4, wherein the second capping layer and the barrier layer have different hydrogen ratios.

7. The semiconductor structure as described in claim 4, wherein the second capping layer is the hydrogen-rich dielectric layer.

8. The semiconductor structure as described in claim 4, wherein the second capping layer and the barrier layer have the same hydrogen ratio.

9. The semiconductor structure as described in claim 4, wherein the second capping layer comprises: A main body is disposed on the first cover layer; an extension extends from the bottom surface of the main body onto a portion of the sidewall of the filler layer and contacts the barrier layer.

10. The semiconductor structure as claimed in claim 9, wherein the bottom surface of the extension is lower than the top surface of the filling layer.

11. The semiconductor structure as claimed in claim 9, wherein the extension has an air gap therein.

12. The semiconductor structure as described in claim 4, further comprising: A third cover layer is disposed on the second cover layer.

13. The semiconductor structure as described in claim 12, wherein the third capping layer is another hydrogen-rich dielectric layer.

14. The semiconductor structure as claimed in claim 12, wherein the third capping layer has a different hydrogen ratio than the second capping layer.

15. The semiconductor structure as claimed in claim 12, wherein the third capping layer and the barrier layer have the same hydrogen ratio as the second capping layer.

16. The semiconductor structure as described in claim 1, wherein the conductive layer comprises: A metal layer is disposed at the bottom of the conductive layer; And a semiconductor layer disposed on the metal layer.

17. The semiconductor structure as described in claim 16, wherein the conductive layer further comprises: A first barrier layer surrounds the metal layer; And a second barrier layer is disposed between the metal layer and the semiconductor layer.

18. A method for forming a semiconductor structure, comprising: Provide a substrate; And forming a character line structure in the substrate, wherein forming the character line structure includes: forming a conductive layer in the lower part of the character line structure; And forming a filling layer and a barrier layer surrounding the filling layer on the conductive layer, wherein the barrier layer is a hydrogen-rich dielectric layer.

19. A method for forming a semiconductor structure as described in claim 18, wherein forming the barrier layer and the fill layer comprises: A barrier material layer is compliantly deposited on the conductive layer and the substrate; A filler material layer is compliantly deposited on the barrier material layer; Remove excess of the barrier material layer and the filler material layer to create a recess in the barrier layer.

20. The method for forming a semiconductor structure as described in claim 18 further includes: Before forming the character line structure, an insulating layer is formed in the substrate; A first capping layer is formed on the top surface of the insulating layer and the top surface of the substrate; and after forming the character line structure, a second capping layer and a third capping layer are sequentially formed on the barrier layer and the filler layer.

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