Memory structure and manufacturing method thereof

Abstract

A memory structure including a substrate, a lower barrier layer, a bit line contact window and a bit line structure. The substrate includes a plurality of active regions. The lower barrier layer is disposed on the substrate, and overlaps with one of the plurality of active regions in a top view direction of the substrate. The bit line contact window is disposed on the lower barrier layer, and is electrically connected to one of the plurality of active regions. The bit line structure is formed above the substrate and disposed on the bit line contact window, and includes an upper barrier layer, a bit line layer, a capping layer and a first liner layer. The bit line layer is disposed on the upper barrier layer. The capping layer is disposed on the bit line layer. The first liner layer is disposed on the upper barrier layer, the bit line layer and sidewalls of the capping layer. A material of the bit line contact window includes tungsten, and a material of the first liner layer includes oxide. A manufacturing method of a memory structure is also provided.

Description

[Technical Field]

[0001] This invention relates to a memory structure and a method for manufacturing the same, and more particularly to a dynamic random access memory and a method for manufacturing the same. [Previous Technology]

[0002] As the size of dynamic random-access memory (DRAM) gradually shrinks, the corresponding increase in capacitive load and / or impedance poses challenges to DRAM operation. Specifically, the increase in capacitive load and / or impedance increases the resistor-capacitor delay (RC-delay), which reduces the operating speed and / or performance of DRAM. [Summary of the Invention]

[0003] One embodiment of this disclosure provides a memory structure including a substrate, a lower barrier layer, a bitline contact window, and a bitline structure. The substrate includes a plurality of active regions. The lower barrier layer is disposed on the substrate and overlaps with one of the plurality of active regions in the top view of the substrate. The bitline contact window is formed above the substrate and disposed on the lower barrier layer, and is electrically connected to one of the plurality of active regions. The bitline structure is disposed on the bitline contact window and includes an upper barrier layer, a bitline layer, a top cover layer, and a first liner. The bitline layer is disposed on the upper barrier layer. The top cover layer is disposed on the bitline layer. The first liner is disposed on the sidewalls of the upper barrier layer, the bitline layer, and the top cover layer. The material of the bitline contact window includes tungsten, and the material of the first liner includes oxide.

[0004] One embodiment of this disclosure provides a method for manufacturing a memory structure, which includes the following steps: Forming a stacked material layer on a substrate, wherein the stacked material layer includes a lower barrier material layer, a bit line contact window material layer, an upper barrier material layer, a bit line material layer, and a top cover material layer stacked in this order. Performing a patterning process and an oxide layer growth process on the stacked material layer to form a plurality of bit line structures, bit line contact windows, and a lower barrier layer, wherein one of the plurality of bit line structures includes an upper barrier layer, a bit line layer, and a top cover layer stacked in this order, and includes a first liner layer disposed on the sidewalls of the upper barrier layer, the bit line layer, and the top cover layer. Forming a plurality of contact window openings.

Implementation Method

[0005] The following description provides detailed examples in conjunction with the accompanying drawings, but these examples are not intended to limit the scope of the invention. Furthermore, the drawings are for illustrative purposes only and are not drawn to scale. For ease of understanding, the same elements will be designated with the same symbols in the following description.

[0006] Figures 1A to 1C illustrate a cross-sectional schematic diagram of a method for manufacturing a memory structure according to an embodiment of the present disclosure, and Figures 2A to 2C illustrate a cross-sectional schematic diagram of a method for manufacturing a bit line structure according to an embodiment of Figure 1B.

[0007] Referring to FIG1A, firstly, a stacked material layer 100a is formed on a substrate SB. The substrate SB is, for example, a semiconductor substrate. In one embodiment, the material of the substrate SB may include silicon, doped silicon, germanium, silicon-germanium, semiconductor compounds, other suitable semiconductor materials, or combinations thereof. For example, the substrate SB may be a silicon substrate.

[0008] The substrate SB may include multiple isolation structures IS, multiple active regions AA, and multiple embedded word lines WL. The multiple isolation structures IS are, for example, shallow trench isolation structures. The material of the multiple isolation structures IS is, for example, undoped silicon oxide, silicon nitride, or a combination thereof. One of the multiple active regions AA is located, for example, between adjacent isolation structures IS. In other words, multiple active regions AA can be defined by the arrangement of multiple isolation structures IS. The multiple embedded word lines WL may extend, for example, along the X direction and may be arranged along the Y direction.

[0009] The stacked material layer 100a includes a lower barrier material layer 110a, a bit line contact window material layer 120a, an upper barrier material layer 130a, a bit line material layer 140a, and a top cover material layer 150a stacked in this order, but this disclosure is not limited thereto. The bit line contact window material layer 120a may include a plurality of bit line contact window patterns 122a and a plurality of oxide patterns 124a, wherein one of the plurality of oxide patterns 124a is disposed between adjacent bit line contact window patterns 122a. In this embodiment, the bit line contact window material layer 120a can be formed by performing the following steps.

[0010] First, a bitline contact window pattern material layer (not shown) is formed using a suitable deposition process. Next, a plurality of bitline contact window patterns 122a are formed by etching the bitline contact window pattern material layer. Then, an oxide pattern material layer (not shown) is formed using a suitable deposition process, wherein the oxide pattern material layer at least fills the spaces between adjacent bitline contact window patterns 122a. Finally, a plurality of oxide patterns 124a are formed by planarizing the oxide pattern material layer.

[0011] In this embodiment, the materials of the lower barrier material layer 110a and the upper barrier material layer 130a may include metals, such as titanium, titanium nitride, tantalum, tantalum nitride, or combinations thereof, and can be formed by a suitable deposition process. The materials of the plurality of bit line contact window patterns 122a and the bit line material layer 140a may include metals, such as tungsten, aluminum, copper, titanium, tantalum, tungsten, niobium, molybdenum, or combinations thereof. The materials of the plurality of oxide patterns 124a include, for example, oxides, such as silicon oxide. The material of the top cover material layer 150a includes, for example, an insulating material, such as silicon nitride, and can be formed by a suitable deposition process.

[0012] Referring to FIG1B, the stacked material layer 100a is then patterned and an oxide layer is grown to form a plurality of bit line structures BL. In this embodiment, the plurality of bit line structures BL can be formed by performing the steps shown in FIG2A to FIG2C, but this disclosure is not limited thereto.

[0013] Referring to FIG2A, an etching process is performed to remove a portion of the top cap material layer 150a, a portion of the bit line material layer 140a, and a portion of the upper barrier material layer 130a, to form a top cap layer 150, a bit line layer 140, and an upper barrier layer 130. The bit line contact window material layer 120a can serve as an etching termination layer. In other words, after this etching process, a portion of the bit line contact window material layer 120a can be exposed. In this embodiment, the above-described etching process can simultaneously remove a portion of the bit line contact window material layer 120a.

[0014] Referring to FIG2B, a plasma process is performed to form the substrate L1. In this embodiment, the substrate L1 is formed on the sidewalls of the upper barrier layer 130, the bit line layer 140, and the top cover layer 150, and on the surface of the exposed bit line contact window material layer 120a. The material of the substrate L1 may include oxides, such as silicon oxide. In one embodiment, the above-described plasma process includes an in-situ plasma process, but this disclosure is not limited thereto.

[0015] Referring to FIG2C, an etching process is performed to remove a portion of the liner L1, a portion of the bitline contact window material layer 120a, and a portion of the lower barrier material layer 110a to form a bitline structure BL, a bitline contact window 122, and a lower barrier layer 110, wherein the substrate SB can serve as an etching termination layer. As shown in FIG2C, each bitline structure BL includes, for example, an upper barrier layer 130, a bitline layer 140, and a top cover layer 150 sequentially stacked on the substrate SB, and includes a liner L1 disposed on the sidewalls of the upper barrier layer 130, the bitline layer 140, and the top cover layer 150. In this embodiment, the liner L1 can protect the upper barrier layer 130, the bitline layer 140, and the top cover layer 150 during this etching process, and after this etching process, a trench Tr is formed that exposes a portion of the substrate SB. Additionally, this embodiment may include a lateral etching process to adjust the width of the bitline contact window 122 to be substantially the same as the width of the bitline layer 140. Furthermore, in one embodiment, this lateral etching process also removes a portion of the oxide pattern 124a, forming an oxide layer 124.

[0016] After the bit line contact window 122 and the lower barrier layer 110 are formed, a liner L2, a liner L3, a liner L4, and a sacrificial layer SAC can be formed sequentially on the substrate SB to form the structure shown in FIG1B. Referring to FIG1B, the liner L2 and the liner L3 can be formed sequentially and conformally on the substrate SB through a suitable deposition process. Specifically, the liner L2 can cover the liner L1, the bit line contact window 122, the oxide 124, the lower barrier layer 110, and the substrate SB. The liner L3 can cover the liner L2. The material of the liner L3 includes oxides or nitrides, and in this embodiment, for example, silicon oxycarbide (SiCO). The material of the liner L3 includes oxides or nitrides, and in this embodiment, for example, silicon oxide. Subsequently, a removal process can be performed to remove portions of the liner L2 and the liner L3 located at the top of the multiple bit line structures BL and the bottom of the trenches Tr. Next, a liner L4 can be formed using a suitable deposition process. The liner L4 can be conformally formed on the substrate SB. Specifically, the liner L4 can cover the bitline structure BL, the liner L3, and the substrate SB. The material of the liner L4 includes nitrides or oxides, and in this embodiment, for example, silicon nitride. Next, a sacrificial layer SAC can be formed using a deposition process, spin coating process, or a suitable process. The sacrificial layer SAC is formed on the substrate SB and filled into the trench Tr. The material of the sacrificial layer SAC can include oxides or carbides, and in this embodiment, for example, silicon oxide.

[0017] Referring to FIG1C, a plurality of contact window openings NC are then formed. In this embodiment, an etching process is performed to remove the sacrificial layer SAC filled in the trench Tr. Then, an etching process is continued to remove the liner L4 located at the top of the plurality of bit line structures BL and the bottom of the trench Tr to expose a portion of the substrate SB. Next, an etching process is continued to remove the exposed portion of the substrate SB, forming a plurality of contact window openings NC. In one embodiment, a portion of the isolation structure IS in the substrate SB is also removed in this etching process.

[0018] It is worth noting that after forming multiple contact window openings NC, capacitor contact windows (not shown) may be subsequently formed therein, but this disclosure is not limited thereto.

[0019] Thus, the manufacturing method of the memory structure 10 of this embodiment is completed. In this embodiment, the bit line contact window 122 is formed above the substrate SB and is not embedded in the substrate SB. The sidewalls of the bit line contact window 122 are covered by the liner L2, liner L3, and liner L4. Therefore, after removing the liner L4 located at the bottom of the trench Tr, when the portion of the substrate SB exposed by the trench Tr is then removed to form the contact window opening NC, the contact window opening NC will not expose the sidewalls of the bit line contact window 122, which can reduce the risk of short circuit between the subsequently formed capacitor contact window (not shown) and the bit line contact window 122. Furthermore, the contact window opening NC can have more space for expansion, more substrate SB can be removed to increase the surface area exposed by the substrate SB, increase the contact area between the substrate SB and the subsequently formed capacitor contact window (not shown), and improve the electrical performance of the memory structure 10.

[0020] The construction of the memory structure 10 of this embodiment will be briefly described below with reference to FIG1C, but the present disclosure is not limited thereto. Referring to FIG1C, the memory structure 10 of this embodiment includes a substrate SB, a lower barrier layer 110, a bit line contact window 122, an upper barrier layer 130, a bit line layer 140, a top cover layer 150, and a liner L1, wherein the lower barrier layer 110, the bit line contact window 122, the upper barrier layer 130, the bit line layer 140, and the top cover layer 150 are stacked sequentially in the top view direction Z of the substrate SB. In this embodiment, the upper barrier layer 130, the bit line layer 140, the top cover layer 150, and the liner L1 form a bit line structure BL, but the present disclosure is not limited thereto.

[0021] The substrate SB includes, for example, multiple isolation structures IS and multiple embedded character lines WL. Adjacent isolation structures IS define the active area AA of the substrate SB. The multiple embedded character lines WL extend, for example, along the X direction and are arranged along the Y direction.

[0022] The lower barrier layer 110 is disposed, for example, on the substrate SB. In this embodiment, the lower barrier layer 110 overlaps with the active region AA of the substrate SB in the top view direction Z, but this disclosure is not limited thereto. The lower barrier layer 110 and the embedded character line WL in the substrate SB have, for example, a distance D in the top view direction Z of the substrate SB. In this embodiment, the distance D is approximately 60 nanometers, but this disclosure is not limited thereto. Further description of the lower barrier layer 110 can be found in the above embodiment and will not be repeated here.

[0023] A bit line contact window 122 is formed above the substrate SB and, for example, disposed on the lower barrier layer 110, and is electrically connected to, for example, the active region AA of the substrate SB. In this embodiment, the material of the bit line contact window 122 is selected from metallic materials, such as tungsten, aluminum, copper, titanium, tantalum, niobium, molybdenum, etc. Compared with conventional bit line contact windows using non-metallic materials (such as polycrystalline silicon), it has a lower sheet resistance, thus significantly reducing the impedance value of the memory structure 10. In addition, in this embodiment, since the bit line contact window 122 is not embedded in the substrate SB, the distance between the bit line contact window 122 and the embedded word line WL in the substrate SB (or the distance D between the lower barrier layer 110 and the embedded word line WL) can be relatively increased. This can increase the signal integrity of the memory structure 10, reduce crosstalk in the memory structure 10, and reduce the capacitive load of the memory structure 10.

[0024] The bit line structure BL is disposed on the bit line contact window 122. In this embodiment, the bit line structure BL includes an upper barrier layer 130, a bit line layer 140, a top cover layer 150, and a liner L1. The upper barrier layer 130 is disposed on the bit line contact window 122. The bit line layer 140 is disposed on the upper barrier layer 130. The top cover layer 150 is disposed on the bit line layer 140. The liner L1 is disposed on the sidewalls of the upper barrier layer 130, the bit line layer 140, and the top cover layer 150.

[0025] The memory structure 10 also includes a liner L2, a liner L3, and a liner L4. Liner L2 is conformally disposed on the sidewalls of liner L1, the bit line contact window 122, and the lower barrier layer 110. Liner L3 is conformally disposed on the sidewall of liner L2. Liner L4 is conformally disposed on the sidewall of liner L3. In this embodiment, the sidewall of the bit line contact window 122 is covered by liner L2, liner L3, and liner L4.

[0026] The memory structure 10 also includes a plurality of contact window openings NC. One of the plurality of contact window openings NC is disposed, for example, between adjacent bit line contact windows 122, and exposes a portion of the substrate SB. In one embodiment, a capacitor contact window (not shown) is disposed among the plurality of contact window openings NC. In this embodiment, the bit line contact window 122 is formed above the substrate SB, and the sidewalls of the bit line contact window 122 are covered by the substrate L2, substrate L3, and substrate L4. Since the bit line contact window 122 is not embedded in the substrate SB, more of the substrate SB can be removed when forming the contact window opening NC, so that the contact window opening NC has a larger expansion space in the part of the substrate SB. As a result, the capacitor contact window (not shown) formed subsequently can have a larger contact area with the substrate SB, thereby improving the electrical performance of the memory structure 10.

[0027] Figures 3A to 3C illustrate cross-sectional schematic diagrams of a method for manufacturing a bitline structure according to another embodiment of Figure 1B. In this embodiment, multiple bitline structures BL' can be formed by performing the steps shown in Figures 3A to 3C, but this disclosure is not limited thereto. The main difference between this embodiment and the embodiments shown in Figures 2A to 2C lies in the formation method of the liner L1 (Figure 2C) and the liner L1' (Figure 3C). Other relevant descriptions of this embodiment can be referred to the embodiments shown in Figures 2A to 2C above, and will not be repeated here.

[0028] Please refer to Figure 3A. The structure shown in Figure 2A is provided. The detailed formation method can be referred to the embodiment shown in Figure 2A above, and will not be repeated here.

[0029] Referring to FIG3B, a deposition process is performed to form the liner L1'. In this embodiment, the liner L1' is formed on the sidewalls of the upper barrier layer 130, the bit line layer 140, and the capping layer 150, and on the surface of the capping layer 150 and the exposed bit line contact window material layer 120a. The material of the liner L1' may include oxides and nitrides, and in this embodiment, for example, silicon carbide. In one embodiment, the above deposition process includes a chemical vapor deposition plasma process, but this disclosure is not limited thereto.

[0030] Referring to FIG3C, an etching process is performed to remove a portion of the substrate L1, a portion of the bit line contact window material layer 120a, and a portion of the lower barrier material layer 110a to form a bit line structure BL', a bit line contact window 122, and a lower barrier layer 110. As shown in FIG3C, each bit line structure BL' includes an upper barrier layer 130, a bit line layer 140, and a top cover layer 150 sequentially stacked on the substrate SB, and includes a substrate L1' disposed on the sidewalls of the upper barrier layer 130, the bit line layer 140, and the top cover layer 150.

[0031] Next, the plurality of contact window openings NC and capacitor contact windows (not shown) can be formed as described in Figures 1B and 1C.

[0032] In summary, in the memory structure and manufacturing method of the present disclosure embodiment, by forming the bit line contact window above the substrate without embedding it in the substrate, and by covering the sidewall of the bit line contact window with at least one liner, when one of the at least one liner located at the bottom of the trench and a portion of the substrate are sequentially removed to form the contact window opening, the sidewall of the bit line contact window will not be exposed. Based on this, the risk of short circuit between the subsequently formed capacitor contact window and the bit line contact window can be reduced. Furthermore, the contact window opening can have more space for expansion, and more substrate can be removed to increase its exposed surface area, thereby increasing the contact area between the substrate and the subsequently formed capacitor contact window, thereby improving the electrical performance of the memory structure provided in the present disclosure embodiment.

[0033] Furthermore, since the bit line contact window is formed above the substrate and not embedded in the substrate, the distance between the bit line contact window and the embedded word line in the substrate (or the distance between the lower barrier layer and the embedded word line) can be relatively increased, which can increase the signal integrity of the memory structure, reduce the crosstalk phenomenon generated by the memory structure, and reduce the capacitive load of the memory structure. [Simplified Explanation of the Diagram]

[0034] Figures 1A to 1C illustrate cross-sectional schematic diagrams of a method for manufacturing a memory structure according to an embodiment of the present disclosure. Figures 2A to 2C illustrate cross-sectional schematic diagrams of a method for manufacturing a bit line structure according to an embodiment of Figure 1B. Figures 3A to 3C illustrate cross-sectional schematic diagrams of a method for manufacturing a bit line structure according to another embodiment of Figure 1B.

Claims

1. A memory structure, comprising: The substrate includes multiple active regions; A lower barrier layer is disposed on the substrate and overlaps with one of the plurality of active regions in the top view of the substrate; a bit line contact window is formed above the substrate and disposed on the lower barrier layer, and is electrically connected to one of the plurality of active regions. A bitline structure is disposed on the bitline contact window and includes: an upper barrier layer; a bitline layer disposed on the upper barrier layer; a top cover layer disposed on the bitline layer; a first liner disposed on the sidewalls of the upper barrier layer, the bitline layer, and the top cover layer; a second liner disposed on the sidewalls of the first liner, the bitline contact window, and the lower barrier layer; a third liner disposed on the sidewalls of the second liner; and a fourth liner disposed on the substrate and covering the third liner, the bitline structure, and the substrate, wherein the sidewalls of the bitline contact window are covered by the second liner, the third liner, and the fourth liner, wherein the material of the bitline contact window includes tungsten, and the material of the first liner includes oxide.

2. The memory structure as claimed in claim 1, wherein the bit line contact window has a rectangular shape in a direction perpendicular to the top view direction of the substrate.

3. The memory structure as claimed in claim 1, wherein the material of the first liner comprises silicon oxide or silicon carbide.

4. The memory structure as claimed in claim 1, further comprising a plurality of contact window openings, wherein one of the plurality of contact window openings is disposed between adjacent bit line contact windows.

5. A method for manufacturing a memory structure, comprising: A stacked material layer is formed on a substrate, wherein the stacked material layer includes a lower barrier material layer, a bit line contact window material layer, an upper barrier material layer, a bit line material layer, and a top cover material layer stacked in this order; the stacked material layer is subjected to a patterning process and an oxide layer growth process to form a plurality of bit line structures, bit line contact windows, and a lower barrier layer, wherein one of the plurality of bit line structures includes an upper barrier layer, a bit line layer, and a top cover layer stacked in this order, and includes a first liner layer disposed on the sidewalls of the upper barrier layer, the bit line layer, and the top cover layer. And to form multiple contact window openings.

6. A method for manufacturing a memory structure as claimed in claim 5, wherein the step of performing the patterning process on the stacked material layers includes: A first etching process is performed to remove a portion of the top cover material layer, a portion of the bit line material layer, and a portion of the upper barrier material layer to expose a portion of the bit line contact window material layer, thereby forming the upper barrier layer, the bit line layer, and the top cover layer, respectively. The bit line contact window material layer and the lower barrier material layer are removed in a second etching process to form the bit line contact window and the lower barrier layer, respectively.

7. The method of manufacturing a memory structure as claimed in claim 6, wherein the oxide layer growth process is performed between the first etching process and the second etching process.

8. A method for manufacturing a memory structure as claimed in claim 5, wherein the first substrate is formed by performing the oxide layer growth process, and the oxide layer growth process includes an in-situ plasma process or a chemical vapor deposition process.

9. A method of manufacturing a memory structure as claimed in claim 5, wherein after forming the bit line contact window and the lower barrier layer, a second liner, a third liner, and a fourth liner are sequentially formed on the substrate, wherein the sidewalls of the bit line contact window are covered by the second liner, the third liner, and the fourth liner.

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