Semiconductor structure

Abstract

A semiconductor structure including a carrier wafer and chips is provided. The chips are stacked on the carrier wafer. Two adjacent wafers are bonded to each other. Each of the chips includes memory arrays and input / output (I / O) circuits. The I / O circuits are located aside the memory arrays. Two adjacent I / O circuits are mirror symmetrical.

Description

Technical Field

[0001] This invention relates to a semiconductor structure, and more particularly to a semiconductor structure comprising multiple memory arrays and multiple input / output circuits. Prior Technology

[0002] Integrated circuits can be fabricated on semiconductor wafers. Semiconductor wafers and / or chips can be stacked or bonded to form three-dimensional integrated circuits (3DICs). However, improving the process efficiency of 3D integrated circuits and reducing bonding defects and bonding time are ongoing goals. Summary of the Invention

[0003] This invention provides a semiconductor structure that can improve the process efficiency of three-dimensional integrated circuits and reduce bonding defects and bonding time.

[0004] This invention proposes a semiconductor structure comprising a carrier wafer and multiple wafers. The multiple wafers are stacked on the carrier wafer. Adjacent wafers are bonded to each other. Each wafer includes multiple memory arrays and multiple input / output (I / O) circuits. The multiple I / O circuits are located adjacent to the multiple memory arrays. Adjacent I / O circuits are mirror-symmetrical.

[0005] According to one embodiment of the present invention, in the above semiconductor structure, the carrier wafer may be a controller wafer.

[0006] According to an embodiment of the present invention, in the above semiconductor structure, the multiple memory arrays can be multiple dynamic random access memory (DRAM) arrays.

[0007] According to one embodiment of the present invention, in the above semiconductor structure, multiple input / output circuits may be located between multiple memory arrays.

[0008] According to one embodiment of the present invention, in the above semiconductor structure, each chip may further include multiple decoders. Each decoder is located between the corresponding input / output circuit and the corresponding memory array.

[0009] According to one embodiment of the present invention, in the above semiconductor structure, each chip may further include multiple multiplexers. Each multiplexer is located between the corresponding input / output circuit and the corresponding decoder.

[0010] According to one embodiment of the present invention, in the above-described semiconductor structure, the wafer closest to the carrier wafer can be bonded to the carrier wafer.

[0011] According to one embodiment of the present invention, in the above-described semiconductor structure, the front side of the wafer closest to the carrier wafer can be bonded to the front side of the carrier wafer.

[0012] According to one embodiment of the present invention, in the above semiconductor structure, the interface between the wafer closest to the carrier wafer and the carrier wafer can be a hybrid bonding interface.

[0013] According to one embodiment of the present invention, in the above semiconductor structure, the interface between the wafer closest to the carrier wafer and the carrier wafer can be a bump bonding interface.

[0014] According to an embodiment of the present invention, in the above-described semiconductor structure, the back side of one of two adjacent wafers may be bonded to the back side of the other of two adjacent wafers.

[0015] According to one embodiment of the present invention, in the above-described semiconductor structure, the front side of one of two adjacent wafers can be bonded to the front side of the other of two adjacent wafers.

[0016] According to one embodiment of the present invention, in the above-described semiconductor structure, the front side of one of two adjacent wafers can be bonded to the back side of the other of the two adjacent wafers.

[0017] According to one embodiment of the present invention, in the above-described semiconductor structure, the interface between two adjacent wafers can be a hybrid bonding interface.

[0018] According to one embodiment of the present invention, in the above-described semiconductor structure, the interface between two adjacent wafers can be a bump bonding interface.

[0019] According to an embodiment of the present invention, in the above-described semiconductor structure, the stacked structure of the wafer closest to the carrier wafer and the carrier wafer can be a wafer-on-wafer (WoW) stacked structure.

[0020] According to an embodiment of the present invention, in the above-described semiconductor structure, the stacked structure of the wafer closest to the carrier wafer and the carrier wafer can be a chip-on-wafer (CoW) stacked structure.

[0021] According to one embodiment of the present invention, in the above semiconductor structure, the stacked structure of multiple wafers can be a wafer-on-wafer (WoW) stacked structure.

[0022] According to one embodiment of the present invention, in the above semiconductor structure, the stacked structure of multiple wafers can be a chip-on-chip (CoC) stacked structure.

[0023] According to an embodiment of the present invention, in the above-described semiconductor structure, the stacked structure of multiple wafers and the carrier wafer can be a wafer-on-wafer (WoW) stacked structure.

[0024] Based on the above, in the semiconductor structure proposed in this invention, since two adjacent input / output circuits are mirror-symmetrical, the chip design can be simplified by using mirror-symmetrical input / output circuits. Furthermore, mirror-symmetrical input / output circuits are applicable to various bonding methods (e.g., face-to-face (F2F) bonding, back-to-back (B2B) bonding, and face-to-back (F2B) bonding) and stacking methods (e.g., wafer-on-wafer stacking). In this way, the semiconductor structure proposed in this invention can improve the process efficiency of three-dimensional integrated circuits (3DIC) and reduce bonding defects and bonding time.

[0025] To make the above features and advantages of the present invention more apparent and understandable, specific embodiments are described below in conjunction with the accompanying drawings for detailed explanation. Simple Explanation of the Diagram

[0026] Figure 1 is a schematic diagram of a semiconductor structure according to some embodiments of the present invention. Figure 2 is a top view of a wafer according to some embodiments of the present invention. Figure 3 is a top view of a wafer according to some other embodiments of the present invention. Figure 4 is a schematic diagram of a semiconductor structure according to some other embodiments of the present invention. Implementation

[0027] The following description provides detailed examples and accompanying drawings, but these examples are not intended to limit the scope of the invention. For ease of understanding, the same components will be designated with the same symbols in the following description. Furthermore, the drawings are for illustrative purposes only and are not drawn to their original dimensions. In fact, the dimensions of various features may be arbitrarily increased or decreased for clarity of explanation.

[0028] Figure 1 is a schematic diagram of a semiconductor structure according to some embodiments of the present invention. Figure 2 is a top view of a wafer according to some embodiments of the present invention. Figure 3 is a top view of a wafer according to other embodiments of the present invention. Figure 4 is a schematic diagram of a semiconductor structure according to other embodiments of the present invention.

[0029] Referring to Figures 1 and 2, the semiconductor structure 10 includes a carrier wafer 100 and a plurality of wafers 102. The carrier wafer 100 may include a front side FS1 and a back side BS1 opposite to each other. In some embodiments, the front side FS1 may be defined as the side on which semiconductor elements (e.g., controllers, etc.) are disposed. In some embodiments, the carrier wafer 100 may be a controller wafer. That is, a controller (not shown) in the semiconductor structure 10 may be disposed in the carrier wafer 100. In some embodiments, the controller may be located on the front side FS1 of the carrier wafer 100. In Figure 1, components (e.g., controllers, etc.) located on the carrier wafer 100 are omitted to simplify the diagram.

[0030] Multiple wafers 102 are stacked on a carrier wafer 100. Adjacent wafers 102 are bonded to each other. Each wafer 102 includes multiple memory arrays 104 and multiple input / output circuits 106. Each wafer 102 may include a front face FS2 and a back face BS2 opposite to each other. In some embodiments, the front face FS2 may be defined as the face on which semiconductor elements (e.g., memory arrays 104 and input / output circuits 106) are disposed. In some embodiments, the multiple memory arrays 104 may be multiple dynamic random access memory arrays. The multiple input / output circuits 106 are located beside the multiple memory arrays 104. In some embodiments, the multiple input / output circuits 106 may be located between the multiple memory arrays 104. Adjacent input / output circuits 106 are mirror-symmetrical. Therefore, the design of the chip 102 can be simplified by using the mirror-symmetric input / output circuit 106, and the mirror-symmetric input / output circuit 106 is applicable to various bonding methods (e.g., face-to-face (F2F) bonding, back-to-back (B2B) bonding, and face-to-back (F2B) bonding) and stacking methods (e.g., wafer-on-wafer (WoW) stacking). Furthermore, the number of chips 102 is not limited to the number shown in the figure. Any number of chips 102 falls within the scope of this invention.

[0031] In some embodiments, each chip 102 may further include multiple decoders 108A. Each decoder 108A is located between a corresponding input / output circuit 106 and a corresponding memory array 104. In some embodiments, each chip 102 may further include a decoder 108B. Decoders 108A and decoders 108B may be located on different sides of the memory array 104. In some embodiments, decoder 108B is not located between the input / output circuit 106 and the memory array 104. Each chip 102 may further include multiple multiplexers 110. Each multiplexer 110 is located between a corresponding input / output circuit 106 and a corresponding decoder 108A. Furthermore, the number of memory arrays 104, the number of input / output circuits 106, the number of decoders 108A, the number of decoders 108B, and the number of multiplexers 110 are not limited to the numbers shown in FIG. 2. As long as there are multiple memory arrays 104, the number of input / output circuits 106, the number of decoders 108A, the number of decoders 108B, and the number of multiplexers 110, they are within the scope of this invention. In other embodiments, the number of memory arrays 104, the number of input / output circuits 106, the number of decoders 108A, the number of decoders 108B, and the number of multiplexers 110 may be as shown in FIG3. Furthermore, in FIG2 and FIG3, the same or similar components are represented by the same symbols, and their descriptions are omitted.

[0032] In some embodiments, the wafer 102 closest to the carrier wafer 100 may be bonded to the carrier wafer 100. In some embodiments, the method of bonding the wafer 102A closest to the carrier wafer 100 to the carrier wafer 100 may be a face-to-face (F2F) bonding method. That is, the front side FS2 of the wafer 102A closest to the carrier wafer 100 may be bonded to the front side FS1 of the carrier wafer 100.

[0033] In some embodiments, the method by which the wafer 102A closest to the carrier wafer 100 is bonded to the carrier wafer 100 may be a hybrid bonding method or a bump bonding method. That is, the interface between the wafer 102A closest to the carrier wafer 100 and the carrier wafer 100 may be a hybrid bonding interface or a bump bonding interface.

[0034] In some embodiments, the bonding method for adjacent two wafers 102 may be a back-to-back (B2B) bonding method. For example, as shown in FIG1, the back side BS2 of one of the two adjacent wafers 102 (e.g., wafer 102B) may be bonded to the back side BS2 of the other of the two adjacent wafers 102 (e.g., wafer 102A). In some embodiments, the bonding method for adjacent two wafers 102 may be a face-to-face (F2F) bonding method. For example, as shown in FIG1, the front side FS2 of one of the two adjacent wafers 102 (e.g., wafer 102C) may be bonded to the front side FS2 of the other of the two adjacent wafers 102 (e.g., wafer 102B). In other embodiments, the bonding method for adjacent two wafers 102 may be a face-to-back (F2B) bonding method. For example, as shown in FIG4, the front side FS2 of one of the two adjacent wafers 102 (e.g., wafer 102D) may be bonded to the back side BS2 of the other of the two adjacent wafers 102 (e.g., wafer 102C). Furthermore, in Figures 1 and 4, identical or similar components are represented by the same symbols, and their descriptions are omitted.

[0035] In some embodiments, the bonding method for two adjacent wafers 102 may be a hybrid bonding method or a bump bonding method. That is, the interface between two adjacent wafers 102 may be a hybrid bonding interface or a bump bonding interface.

[0036] In some embodiments, wafer 102 may be a wafer on a wafer (i.e., a wafer not yet diced from a wafer) or a wafer already diced from a wafer. In some embodiments, the stacked structure of wafer 102A closest to the carrier wafer 100 and the carrier wafer 100 may be a wafer-on-wafer (WoW) stacked structure. In other embodiments, the stacked structure of wafer 102A closest to the carrier wafer 100 and the carrier wafer 100 may be a wafer-on-wafer (CoW) stacked structure. In some embodiments, the stacked structure of multiple wafers 102 may be a wafer-on-wafer (WoW) stacked structure. In other embodiments, the stacked structure of multiple wafers 102 may be a wafer-on-wafer (CoC) stacked structure. When the stacking structure of the chip 102A closest to the carrier wafer 100 and the carrier wafer 100 is a wafer-on-wafer (WoW) stacking structure, and the stacking structure of the multiple chips 102 is a wafer-on-wafer (WoW) stacking structure, the stacking structure of the multiple chips 102 and the carrier wafer 100 can be a wafer-on-wafer (WoW) stacking structure.

[0037] As can be seen from the above embodiments, in the semiconductor structure 10, since two adjacent input / output circuits 106 are mirror-symmetrical, the design of the chip 102 can be simplified by using mirror-symmetrical input / output circuits 106. Furthermore, the mirror-symmetrical input / output circuits 106 are applicable to various bonding methods (e.g., face-to-face (F2F) bonding, back-to-back (B2B) bonding, and face-to-back (F2B) bonding) and stacking methods (e.g., wafer-on-wafer (WoW) stacking). In this way, the semiconductor structure 10 proposed in this invention can improve the process efficiency of three-dimensional integrated circuits (3DIC) and reduce bonding defects and bonding time.

[0038] In summary, the semiconductor structure of the above embodiments includes a carrier wafer and multiple wafers. Multiple wafers are stacked on the carrier wafer. Adjacent wafers are bonded to each other. Each wafer includes multiple memory arrays and multiple input / output (I / O) circuits. The multiple I / O circuits are located next to the multiple memory arrays. Adjacent I / O circuits are mirror-symmetrical. Therefore, the mirror-symmetrical I / O circuits can simplify wafer design and are suitable for various bonding and stacking methods. In this way, the semiconductor structure proposed in this invention can improve the process efficiency of three-dimensional integrated circuits (3DIC) and reduce bonding defects and bonding time.

[0039] Although the present invention has been disclosed above by way of embodiments, it is not intended to limit the present invention. Anyone skilled in the art can make some modifications and refinements without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be determined by the appended claims.

[0040] 10: Semiconductor Structure 100: Carrier wafer 102, 102A, 102B, 102C, 102D: Chips 104: Memory Array 106: Input / Output Circuit 108A, 108B: Decoders 110: Multiplexer FS1, FS2: front BS1, BS2: Back side

Claims

1. A semiconductor structure, comprising: Carrying wafer; And multiple chips, stacked on the carrier wafer, wherein two adjacent chips are bonded to each other, each chip includes multiple memory arrays and multiple input / output circuits, the multiple input / output circuits are located next to the multiple memory arrays, and two adjacent input / output circuits are mirror symmetrical.

2. The semiconductor structure as claimed in claim 1, wherein the carrier wafer includes a controller wafer.

3. The semiconductor structure as claimed in claim 1, wherein the plurality of memory arrays include a plurality of dynamic random access memory arrays.

4. The semiconductor structure as claimed in claim 1, wherein the plurality of said input / output circuits are located between the plurality of said memory arrays.

5. The semiconductor structure as claimed in claim 1, wherein each of the wafers further comprises: Multiple decoders, wherein each decoder is located between the corresponding input / output circuit and the corresponding memory array.

6. The semiconductor structure as claimed in claim 5, wherein each of the wafers further comprises: Multiple multiplexers, wherein each multiplexer is located between the corresponding input / output circuit and the corresponding decoder.

7. The semiconductor structure as claimed in claim 1, wherein the wafer closest to the carrier wafer is bonded to the carrier wafer.

8. The semiconductor structure as claimed in claim 1, wherein the front side of the wafer most adjacent to the carrier wafer is bonded to the front side of the carrier wafer.

9. The semiconductor structure of claim 1, wherein the interface between the wafer and the carrier wafer closest to the carrier wafer includes a hybrid bonding interface.

10. The semiconductor structure of claim 1, wherein the interface between the wafer and the carrier wafer most adjacent to the carrier wafer includes a bump bonding interface.

11. The semiconductor structure of claim 1, wherein the back side of one of two adjacent wafers is bonded to the back side of the other of two adjacent wafers.

12. The semiconductor structure of claim 1, wherein the front side of one of two adjacent wafers is bonded to the front side of the other of two adjacent wafers.

13. The semiconductor structure of claim 1, wherein the front side of one of two adjacent wafers is bonded to the back side of the other of two adjacent wafers.

14. The semiconductor structure as claimed in claim 1, wherein the interface between two adjacent wafers includes a hybrid bonding interface.

15. The semiconductor structure as claimed in claim 1, wherein the interface between two adjacent wafers includes a bump bonding interface.

16. The semiconductor structure of claim 1, wherein the stacking structure of the wafer and the carrier wafer most adjacent to the carrier wafer includes a wafer-on-wafer stacking structure.

17. The semiconductor structure of claim 1, wherein the stacking structure of the wafer and the carrier wafer most adjacent to the carrier wafer includes a wafer-on-wafer stacking structure.

18. The semiconductor structure of claim 1, wherein the stacked structure of the plurality of said wafers includes a wafer-on-wafer stacked structure.

19. The semiconductor structure as claimed in claim 1, wherein the stacked structure of the plurality of said wafers includes a wafer-on-wafer stack.

20. The semiconductor structure of claim 1, wherein the stacking structure of the plurality of said wafers and the carrier wafer includes a wafer-on-wafer stacking structure.

Images