Memory device and its manufacturing method

Abstract

This disclosure provides a highly stackable memory device. The memory device of one embodiment includes a plurality of memory cells MC, bit lines BL, and word lines WL. The plurality of memory cells include a plurality of transistors CT stacked along the Z direction on a substrate 20, and a plurality of capacitors CC stacked along the Z direction on the substrate and connected to the plurality of transistors. The plurality of transistors include a semiconductor layer 21 extending in the Y direction parallel to the substrate, and a gate electrode layer 23 disposed opposite to the semiconductor layer 21. The bit lines BL are connected to the semiconductor layer of the plurality of transistors CT and extend in the Z direction. The word lines WL include the gate electrodes of the plurality of transistors CT and extend in the X direction parallel to the substrate and intersecting the Y direction. The semiconductor layer 21 and the bit lines BL comprise conductive oxide.

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