Read-only memory arrays and their read-only memory that reduce capacitor layout area

Abstract

A read-only memory array and its read-only memory are disclosed. The read-only memory array includes multiple common-source lines, multiple word lines, multiple bit lines, and multiple read-only memory cells. Each read-only memory cell includes an N-channel field-effect transistor (FET), an electronic switch, and a capacitor. The source of the N-channel FET is coupled to the common-source line. The electronic switch is coupled between the drain of the N-channel FET and the bit line. The capacitor is coupled between the gate of the N-channel FET and the word line. The N-channel FET and the capacitor are disposed in a P-type semiconductor region. The capacitor includes a first N-type heavily doped region, a first dielectric block, and an electrode block. The electrode block has a strip-shaped portion and multiple finger-shaped portions disposed perpendicular to it. One end of each finger-shaped portion is connected to the strip-shaped portion, and the other end extends into the first N-type heavily doped region.

Description

[Technical Field]

[0001] This invention relates to a memory device, and more particularly to a read-only memory array and its read-only memory. [Previous Technology]

[0002] Note that Complementary Metal Oxide Semiconductor (CMOS) process technology has become a common manufacturing method for application-specific integrated circuits (ASICs). In today's world of advanced computer information products, Electrically Erasable Programmable Read Only Memory (EEPROM) is widely used in electronic products because it possesses the non-volatile memory function of electrically writing and erasing data, and the data is not lost after the power is turned off.

[0003] Non-volatile memory systems are programmable, used to store charge to change the gate voltage of the memory's transistors, or to leave no charge stored, thus retaining the original gate voltage of the memory's transistors. The erase operation removes all charge stored in the non-volatile memory, returning all non-volatile memory to the original gate voltage of the memory's transistors. During programming, the internal switching elements of non-volatile memory are either turned off or on. To program the non-volatile memory array, a certain voltage and current need to be applied to turn the corresponding switching elements on or off. To improve the stability, reliability, power efficiency, storage density, and read speed of read-only memory, the gate capacitor area is usually large. However, the larger the gate capacitor area, the larger the overall resistance and the smaller the capacitance.

[0004] Therefore, the present invention addresses the above-mentioned problems by proposing a read-only memory array and its read-only memory to solve the problems caused by conventional methods. [Summary of the Invention]

[0005] The present invention provides a read-only memory array and the read-only memory thereof, which significantly reduces the layout area and overall resistance of capacitors and increases the capacitance value.

[0006] In one embodiment of the present invention, a read-only memory array is provided, comprising multiple parallel common-source lines, multiple parallel word lines, multiple parallel bit lines, and multiple read-only memory cells. The common-source line includes a first common-source line, and the word lines are perpendicular to the common-source line, each word line including a first word line. The bit lines are perpendicular to the word lines, each bit line including a first bit line. Each read-only memory cell is coupled to one common-source line, one word line, and one bit line. Each read-only memory cell includes an N-channel field-effect transistor, an electronic switch, and a capacitor. The source of the N-channel field-effect transistor is coupled to the first common-source line, and the electronic switch is coupled between the drain of the N-channel field-effect transistor and the first bit line. One end of the capacitor is coupled to the gate of the N-channel field-effect transistor, and the other end is coupled to the first word line, wherein the N-channel field-effect transistor and the capacitor are disposed in a P-type semiconductor region. The capacitor includes a first N-type heavily doped region, a first dielectric block, and an electrode block. A first N-type heavily doped region is disposed in the P-type semiconductor region and coupled to the first word line. An electrode block is disposed on the P-type semiconductor region through the first dielectric block and coupled to the gate of the N-channel field-effect transistor. The electrode block has a strip-shaped portion and a plurality of finger-shaped portions disposed perpendicular to it, one end of each finger-shaped portion being connected to the strip-shaped portion and the other end extending into the first N-type heavily doped region.

[0007] In one embodiment of the present invention, the capacitor further includes a first N-type well region disposed in the P-type semiconductor region, and the first N-type heavily doped region is disposed in the first N-type well region.

[0008] In one embodiment of the present invention, an N-channel field-effect transistor includes a second dielectric block, a conductive gate, a second heavily doped N-type region, and a third heavily doped N-type region. The second dielectric block is disposed on a P-type semiconductor region, and the conductive gate is disposed on the second dielectric block, coupled to an electrode block. The second and third heavily doped N-type regions are disposed in the P-type semiconductor region, located on opposite sides of the P-type semiconductor region directly below the conductive gate. The second heavily doped N-type region is coupled to a first common source line, and the third heavily doped N-type region is coupled to a first element line via an electronic switch.

[0009] In one embodiment of the present invention, the N-channel field-effect transistor further includes a second N-type well region disposed in the P-type semiconductor region, and the second N-type heavily doped region is disposed in the second N-type well region.

[0010] In one embodiment of the present invention, when the N-channel field-effect transistor and capacitor are selected to perform programming operation, the P-type semiconductor region is coupled to ground voltage, the first word line is coupled to high voltage, the first common source line is coupled to ground voltage, the first word line is electrically floating, and the high voltage is greater than the ground voltage.

[0011] In one embodiment of the present invention, when the N-channel field-effect transistor and capacitor are not selected for programming, the P-type semiconductor region is coupled to ground voltage, the first word line is coupled to ground voltage, the first common source line is coupled to ground voltage, and the first word line is electrically floating.

[0012] In one embodiment of the present invention, when the N-channel field-effect transistor and capacitor are selected to perform an erase operation, the P-type semiconductor region is coupled with the ground voltage, the first word line is coupled with the ground voltage, the first common source line is coupled with the high voltage, the first word line is electrically floating, and the high voltage is greater than the ground voltage.

[0013] In one embodiment of the present invention, when the N-channel field-effect transistor and capacitor are not selected for the erase operation, the P-type semiconductor region is coupled with the ground voltage, the first word line is coupled with the medium voltage, the first common source line is coupled with the high voltage, the first word line is electrically floating, the high voltage is greater than the medium voltage, and the medium voltage is greater than the ground voltage.

[0014] In one embodiment of the present invention, the strip portion is coupled between the gate and the finger portion of the N-channel field-effect transistor.

[0015] In one embodiment of the present invention, the P-type semiconductor region is a semiconductor substrate or an epitaxial layer disposed on a semiconductor substrate.

[0016] In one embodiment of the present invention, a read-only memory is provided, comprising an N-channel field-effect transistor, an electronic switch, and a capacitor. The source of the N-channel field-effect transistor is coupled to a common source line, and the electronic switch is coupled between the drain of the N-channel field-effect transistor and a bit line. One end of the capacitor is coupled to the gate of the N-channel field-effect transistor, and the other end is coupled to a word line, wherein the N-channel field-effect transistor and the capacitor are disposed in a P-type semiconductor region. The capacitor comprises a first heavily doped N-type region, a first dielectric block, and an electrode block. The first heavily doped N-type region is disposed in the P-type semiconductor region and coupled to the word line. The electrode block is disposed on the P-type semiconductor region through the first dielectric block and coupled to the gate of the N-channel field-effect transistor. The electrode block has a strip-shaped portion and a plurality of finger-shaped portions disposed perpendicularly thereto, one end of each finger-shaped portion being connected to the strip-shaped portion, and the other end extending into the first heavily doped N-type region.

[0017] In one embodiment of the present invention, the capacitor further includes a first N-type well region disposed in the P-type semiconductor region, and the first N-type heavily doped region is disposed in the first N-type well region.

[0018] In one embodiment of the present invention, an N-channel field-effect transistor includes a second dielectric block, a conductive gate, a second heavily doped N-type region, and a third heavily doped N-type region. The second dielectric block is disposed on a P-type semiconductor region, and the conductive gate is disposed on the second dielectric block, wherein the conductive gate is coupled to an electrode block. The second and third heavily doped N-type regions are disposed in the P-type semiconductor region, and are located on opposite sides of the P-type semiconductor region directly below the conductive gate. The second heavily doped N-type region is coupled to a common source line, and the third heavily doped N-type region is coupled to a bit line through an electronic switch.

[0019] In one embodiment of the present invention, the N-channel field-effect transistor further includes a second N-type well region disposed in the P-type semiconductor region, and the second N-type heavily doped region is disposed in the second N-type well region.

[0020] In one embodiment of the present invention, when the N-channel field-effect transistor and capacitor are selected to perform programming operation, the P-type semiconductor region is coupled to ground voltage, the word line is coupled to high voltage, the common source line is coupled to ground voltage, the bit line is electrically floating, and the high voltage is greater than the ground voltage.

[0021] In one embodiment of the present invention, when the N-channel field-effect transistor and capacitor are not selected for programming, the P-type semiconductor region is coupled to ground voltage, the word line is coupled to ground voltage, the common source line is coupled to ground voltage, and the bit line is electrically floating.

[0022] In one embodiment of the present invention, when the N-channel field-effect transistor and capacitor are selected to perform an erase operation, the P-type semiconductor region is coupled to ground voltage, the word line is coupled to ground voltage, the common source line is coupled to high voltage, the bit line is electrically floating, and the high voltage is greater than the ground voltage.

[0023] In one embodiment of the present invention, when the N-channel field-effect transistor and capacitor are not selected for the erase operation, the P-type semiconductor region is coupled to ground voltage, the word line is coupled to medium voltage, the common source line is coupled to high voltage, the bit line is electrically floating, the high voltage is greater than the medium voltage, and the medium voltage is greater than the ground voltage.

[0024] In one embodiment of the present invention, the strip portion is coupled between the gate and the finger portion of the N-channel field-effect transistor.

[0025] In one embodiment of the present invention, the P-type semiconductor region is a semiconductor substrate or an epitaxial layer disposed on a semiconductor substrate.

[0026] Based on the above, the read-only memory array and its read-only memory overlap the electrode block with the finger-shaped part of the capacitor with the first dielectric block, so as to obtain the maximum capacitance value with the smallest area of ​​the electrode block, thereby greatly reducing the layout area of ​​the capacitor and the overall resistance value, and optimizing the characteristics of the memory.

[0027] To enable your review committee to have a better understanding of the structural features and effects achieved by the present invention, the following preferred embodiment diagrams and detailed descriptions are provided:

Implementation Method

[0028] Embodiments of the present invention will be further explained below with reference to the accompanying drawings. Wherever possible, the same reference numerals in the drawings and description represent the same or similar components. In the drawings, shapes and thicknesses may be exaggerated for simplification and convenience. It is understood that elements not specifically shown in the drawings or described in the description are forms known to those skilled in the art. Those skilled in the art can make various changes and modifications based on the content of this invention.

[0029] Unless otherwise specified, certain conditional clauses or words, such as "can," "could," "might," or "may," are generally intended to express features, elements, or steps that are present in the embodiments of this invention, but may also be interpreted as features, elements, or steps that may not be required. In other embodiments, these features, elements, or steps may be unnecessary.

[0030] The description of “one embodiment” or “an embodiment” in the following text refers to a specific element, structure, or feature associated with at least one embodiment. Therefore, the multiple descriptions of “one embodiment” or “an embodiment” appearing in various places below are not directed to the same embodiment. Furthermore, specific components, structures, and features in one or more embodiments may be combined in a suitable manner.

[0031] Certain terms are used in the specification and claims to refer to specific elements. However, those skilled in the art will understand that the same element may be referred to by different names. The specification and claims do not distinguish elements by differences in name, but by differences in function. The term "comprising" as used in the specification and claims is an open-ended term and should be interpreted as "comprising but not limited to". In addition, "coupled" here includes any direct and indirect means of connection. Therefore, if the text describes a first element coupled to a second element, it means that the first element can be directly connected to the second element by electrical connection or signal connection such as wireless transmission or optical transmission, or indirectly electrically or signal connected to the second element by other elements or connection means.

[0032] The disclosure is specifically described by the following examples, which are merely illustrative. Various modifications and refinements can be made by those skilled in the art without departing from the spirit and scope of this disclosure. Therefore, the scope of protection of this disclosure shall be determined by the appended claims. Throughout the specification and claims, unless explicitly stated otherwise, the words “a” and “the” include statements containing “a or at least one” of the element or component. Furthermore, as used in this disclosure, the singular article also includes statements of multiple elements or components unless clearly excluded from the specific context. Moreover, when applied in this description and throughout the claims below, unless explicitly stated otherwise, “in which” may include both “in which” and “on which”. The terms used throughout the specification and claims, unless otherwise specified, generally have their ordinary meaning in the context of this disclosure and in specific contexts. Certain terms used to describe this disclosure will be discussed below or elsewhere in this specification to provide additional guidance to practitioners in describing this disclosure. Examples throughout this specification, including examples of any terms discussed herein, are for illustrative purposes only and do not limit the scope or meaning of this disclosure or any illustrative terms. Similarly, this disclosure is not limited to the various embodiments set forth in this specification.

[0033] In the following description, a read-only memory array and a read-only memory thereof will be provided, which overlaps the electrode blocks with finger-shaped portions of capacitors with a first dielectric block, so as to obtain the maximum capacitance value with the smallest area of ​​electrode blocks, thereby significantly reducing the layout area and overall resistance of capacitors and optimizing the characteristics of memory.

[0034] Figure 1 is a circuit diagram of a read-only memory array according to an embodiment of the present invention; Figure 2 is a circuit layout diagram of a read-only memory according to an embodiment of the present invention; and Figure 3 is a structural cross-sectional view of a read-only memory according to a first embodiment of the present invention. Referring to Figures 1, 2, and 3, the read-only memory array 1 of the present invention is described below. The read-only memory array 1 includes multiple parallel common-source lines SL, multiple parallel word lines WL, multiple parallel bit lines BL, and multiple read-only memory cells M. The common-source line SL includes a first common-source line SL1. The word line WL is perpendicular to the common-source line SL, and the word line WL includes a first word line WL1. The bit line BL is perpendicular to the word line WL, and the bit line BL includes a first bit line BL1. Each read-only memory cell M is coupled to one common-source line SL, one word line WL, and one bit line BL. Each read-only memory cell M includes an N-channel field-effect transistor T, an electronic switch SW, and a capacitor C. The source of the N-channel MOSFET T is coupled to the first common source line SL1, and the electronic switch SW is coupled between the drain of the N-channel MOSFET T and the first word line BL1. One end of the capacitor C is coupled to the gate of the N-channel MOSFET T, and the other end is coupled to the first word line WL1. The N-channel MOSFET T and the capacitor C are disposed in a P-type semiconductor region 100. In this embodiment, the P-type semiconductor region 100 is exemplified by a semiconductor substrate. The capacitor C includes a first N-type heavily doped region 101, a first dielectric block 102, and an electrode block 103. The first dielectric block 102 is part of a dielectric layer, and the electrode block 103 is part of an electrode layer E. The dielectric layer, the electrode layer E, and a conductive metal layer are all disposed on the P-type semiconductor region 100 and arranged sequentially from bottom to top. The first N-type heavily doped region 101 is disposed in the P-type semiconductor region 100 and coupled to the first word line WL1. Specifically, the first conductive via H1 overlaps with the first conductive block BK1, and the first conductive via H1 penetrates the first dielectric block 102, so that the first conductive block BK1 is coupled to the first heavily doped N-type region 101. Because the first conductive block BK1 is part of the conductive metal layer, the first heavily doped N-type region 101 is coupled to the first word line WL1 through the first conductive block BK1. The electrode block 103 is disposed on the P-type semiconductor region 100 through the first dielectric block 102 and coupled to the gate of the N-channel field-effect transistor T. The electrode block 103 has a strip-shaped portion 1030 and a plurality of finger-shaped portions 1031 disposed perpendicularly thereto. One end of each finger-shaped portion 1031 is connected to the strip-shaped portion 1030, and the other end extends into the first heavily doped N-type region 101. In some embodiments of the present invention, the strip-shaped portion 1030 is coupled between the gate of the N-channel field-effect transistor T and the finger-shaped portion 1031.When the read-only memory M operates using Fowler-Nordheim tunneling, the overlapping edge of the electrode block 103 and the first dielectric block 102 will generate a capacitance effect. The edges of the strip portion 1030 and the finger portion 1031 can be combined with the electrode block 103 with the smallest area to obtain the maximum capacitance value, thereby greatly reducing the layout area of ​​the capacitor and the overall resistance, and optimizing the characteristics of the memory.

[0035] In some embodiments of the present invention, the capacitor C may further include a first N-type well region 104 disposed in the P-type semiconductor region 100, and a first N-type heavily doped region 101 disposed in the first N-type well region 104. The first N-type well region 104 is used to improve the voltage withstand characteristics of the capacitor C. The N-channel field-effect transistor T may include a second dielectric block 105, a conductive gate 106, a second N-type heavily doped region 107, and a third N-type heavily doped region 108. The second dielectric block 105 is part of the dielectric layer, and the conductive gate 106 is part of the electrode layer E. The second dielectric block 105 is disposed on the P-type semiconductor region 100, and the conductive gate 106 is disposed on the second dielectric block 105, wherein the conductive gate 106 is coupled to the electrode block 103. The second N-type heavily doped region 107 and the third N-type heavily doped region 108 are disposed in the P-type semiconductor region 100. The second N-type heavily doped region 107 and the third N-type heavily doped region 108 are located on opposite sides of the P-type semiconductor region 100 directly below the conductive gate 106. The second N-type heavily doped region 107 is coupled to the first common source line SL1, and the third N-type heavily doped region 108 is coupled to the first bit line BL1 through the electronic switch SW. Specifically, the second conductive via H2 overlaps with the second conductive block BK2 and penetrates the second dielectric block 105, so that the second conductive block BK2 is coupled to the second N-type heavily doped region 107. Because the second conductive block BK2 is part of the conductive metal layer, the second N-type heavily doped region 107 is coupled to the first common source line SL1 through the second conductive block BK2. The third conductive via H3 overlaps with the third conductive block BK3, and the third conductive via H3 penetrates the second dielectric block 105, so that the third conductive block BK3 is coupled to the third N-type heavily doped region 108. Because the third conductive block BK3 is part of the conductive metal layer, the third N-type heavily doped region 108 is coupled to the first bit line BL1 through the third conductive block BK3 and the electronic switch SW. In some embodiments of the present invention, the N-channel field-effect transistor T may further include a second N-type well region 109, which is disposed in the P-type semiconductor region 100, and the second N-type heavily doped region 107 is disposed in the second N-type well region 109. The second N-type well region 109 is used to improve the breakdown voltage characteristics of the N-channel field-effect transistor T.

[0036] The third N-type heavily doped region 108 serves as the drain, and the second N-type heavily doped region 107 serves as the source. Two first sidewall spacers 110 are respectively provided on the two sidewalls of the conductive gate 106. The two first sidewall spacers 110 extend to the sidewall of the second dielectric block 105. Two first N-type lightly doped drain (LDD) regions 111 are respectively provided directly below the two first sidewall spacers 110, one of which is located in the second N-type well region 109. When the N-channel field-effect transistor T is turned on, a channel region CH is formed between the first lightly doped drain regions 111.

[0037] To meet process requirements, capacitor C may further include a fourth N-type heavily doped region 112, which is located on opposite sides of the first N-type well region 104 directly below electrode block 103, as opposed to the first N-type heavily doped region 101. Two second sidewall spacers 113 are provided on each sidewall of electrode block 103, extending to the sidewall of the first dielectric block 102. Two second N-type lightly doped drain (LDD) regions 114 with a second conductivity type are provided directly below the two second sidewall spacers 113.

[0038] The following describes the operation process of the read-only memory M, which includes programming and erasing operations. Common-source lines, word lines, or bit lines are electrically floated or coupled to high, medium, or ground voltages according to process characteristics. When the electronic switch SW of the read-only memory M is turned on, the data stored in the read-only memory M can be read. When the electronic switch SW of the read-only memory M is turned off, the data stored in the read-only memory M cannot be read.

[0039] When the N-channel MOSFET T and capacitor C are selected for programming, the P-type semiconductor region 100 is coupled with ground voltage, the first word line WL1 is coupled with high voltage, the first common source line SL1 is coupled with ground voltage, and the first bit line BL1 is electrically floating. When the N-channel MOSFET T and capacitor C are not selected for programming, the P-type semiconductor region 100 is coupled with ground voltage, the first word line WL1 is coupled with ground voltage, the first common source line SL1 is coupled with ground voltage, and the first bit line BL1 is electrically floating. When the N-channel MOSFET T and capacitor C are selected for erasure, the P-type semiconductor region 100 is coupled with ground voltage, the first word line WL1 is coupled with ground voltage, the first common source line SL1 is coupled with high voltage, and the first bit line BL1 is electrically floating. When the N-channel MOSFET T and capacitor C are not selected for erase operation, the P-type semiconductor region 100 is coupled to ground voltage, the first word line WL1 is coupled to medium voltage, the first common-source line SL1 is coupled to high voltage, and the first word line BL1 is electrically floating. In the above operation, the high voltage is greater than the medium voltage, and the medium voltage is greater than the ground voltage. When the read-only memory M operates using Fowler-Nordheim tunneling, the high voltage is equal to the breakdown voltage of the interface between the second N-type well region 109 and the semiconductor region 100, and the medium voltage is equal to the breakdown voltage of the drain of the N-channel MOSFET T against the source of the N-channel MOSFET T minus the critical voltage of the N-channel MOSFET T. The ground voltage is zero.

[0040] Figure 4 is a cross-sectional view of the read-only memory according to the second embodiment of the present invention. Please refer to Figure 4 and Figure 1. In the embodiment of Figure 4, the N-channel field-effect transistor T and the capacitor C can be disposed in the epitaxial layer 100 on the semiconductor substrate 2, and the epitaxial layer is used as the P-type semiconductor region 100. The remaining structure has been described above and will not be repeated here.

[0041] According to the above embodiments, the read-only memory array and its read-only memory overlap the electrode block with the finger-shaped part of the capacitor with the first dielectric block, so as to obtain the maximum capacitance value with the smallest area of ​​the electrode block, thereby greatly reducing the layout area and overall resistance of the capacitor, and optimizing the characteristics of the memory.

[0042] The above description is only a preferred embodiment of the present invention and is not intended to limit the scope of the present invention. Therefore, all equivalent changes and modifications made in accordance with the shape, structure, features and spirit described in the claims of the present invention should be included in the scope of the claims of the present invention. [Simplified Explanation of the Diagram]

[0043] Figure 1 is a circuit diagram of a read-only memory array according to an embodiment of the present invention. Figure 2 is a circuit layout diagram of a read-only memory according to an embodiment of the present invention. Figure 3 is a structural cross-sectional view of a read-only memory according to a first embodiment of the present invention. Figure 4 is a structural cross-sectional view of a read-only memory according to a second embodiment of the present invention.

Claims

1. A read-only memory array, comprising: a plurality of parallel common-source lines, including a first common-source line; a plurality of parallel word lines perpendicular to the plurality of parallel common-source lines, the plurality of parallel word lines including a first word line; a plurality of parallel bit lines perpendicular to the plurality of parallel word lines, the plurality of parallel bit lines including a first bit line; and a plurality of read-only memory cells, each read-only memory cell being coupled to one common-source line, one word line, and one bit line, wherein each read-only memory cell comprises: an N-channel field-effect transistor, the source of which is coupled to the first common-source line; an electronic switch coupled between the drain of the N-channel field-effect transistor and the first bit line; and a capacitor, one end of which is coupled to the gate of the N-channel field-effect transistor and the other end of which is coupled to the first word line, wherein the N-channel field-effect transistor and the capacitor are disposed in a P-type semiconductor region; wherein the capacitor comprises: A first N-type heavily doped region is disposed in the P-type semiconductor region and coupled to the first word line; a first dielectric block; and an electrode block is disposed on the P-type semiconductor region through the first dielectric block and coupled to the gate of the N-channel field-effect transistor, wherein the electrode block has a strip-shaped portion and a plurality of finger-shaped portions disposed perpendicularly thereto, one end of each finger-shaped portion is connected to the strip-shaped portion, and the other end extends into the first N-type heavily doped region.

2. The read-only memory array as claimed in claim 1, wherein the capacitor further includes a first N-type well region disposed in the P-type semiconductor region, and the first N-type heavily doped region is disposed in the first N-type well region.

3. The read-only memory array as described in claim 2, wherein the N-channel field-effect transistor comprises: a second dielectric block disposed on the P-type semiconductor region; a conductive gate disposed on the second dielectric block, wherein the conductive gate is coupled to the electrode block; and a second heavily doped N-type region and a third heavily doped N-type region disposed on the P-type semiconductor region, the second heavily doped N-type region and the third heavily doped N-type region being located on opposite sides of the P-type semiconductor region directly below the conductive gate, the second heavily doped N-type region being coupled to the first common source line, and the third heavily doped N-type region being coupled to the first bit line through the electronic switch.

4. The read-only memory array as described in claim 3, wherein the N-channel field-effect transistor further includes a second N-type well region disposed in the P-type semiconductor region, and the second N-type heavily doped region is disposed in the second N-type well region.

5. The read-only memory array as described in claim 1, wherein when the N-channel field-effect transistor and the capacitor are selected for programming, the P-type semiconductor region is coupled to ground voltage, the first word line is coupled to high voltage, the first common-source line is coupled to ground voltage, the first word line is electrically floating, and the high voltage is greater than the ground voltage.

6. The read-only memory array as described in claim 1, wherein when the N-channel field-effect transistor and the capacitor are not selected for programming, the P-type semiconductor region is coupled to ground voltage, the first word line is coupled to ground voltage, the first common-source line is coupled to ground voltage, and the first word line is electrically floating.

7. The read-only memory array as described in claim 1, wherein when the N-channel field-effect transistor and the capacitor are selected for an erase operation, the P-type semiconductor region is coupled to a ground voltage, the first word line is coupled to the ground voltage, the first common-source line is coupled to a high voltage, the first word line is electrically floating, and the high voltage is greater than the ground voltage.

8. The read-only memory array as described in claim 1, wherein when the N-channel field-effect transistor and the capacitor are not selected for an erase operation, the P-type semiconductor region is coupled to ground voltage, the first word line is coupled to intermediate voltage, the first common source line is coupled to high voltage, the first word line is electrically floating, the high voltage is greater than the intermediate voltage, and the intermediate voltage is greater than the ground voltage.

9. The read-only memory array as claimed in claim 1, wherein the strip is coupled between the gate and the finger of the N-channel field-effect transistor.

10. The read-only memory array as described in claim 1, wherein the P-type semiconductor region is a semiconductor substrate or an epitaxial layer disposed on a semiconductor substrate.

11. A read-only memory, comprising: an N-channel field-effect transistor (FET) having its source coupled to a common source line; an electronic switch coupled between the drain of the N-channel FET and a bit line; and a capacitor having one end coupled to the gate of the N-channel FET and the other end coupled to a word line, the word line perpendicularly intersecting the bit line and the common source line, wherein the N-channel FET and the capacitor are disposed in a P-type semiconductor region; wherein the capacitor comprises: a first heavily doped N-type region disposed in the P-type semiconductor region and coupled to the word line; a first dielectric block; and an electrode block disposed through the first dielectric block on the P-type semiconductor region and coupled to the gate of the N-channel FET, wherein the electrode block has a strip-shaped portion and a plurality of finger-shaped portions disposed perpendicularly thereto, one end of each finger-shaped portion being connected to the strip-shaped portion and the other end extending into the first heavily doped N-type region.

12. The read-only memory as claimed in claim 11, wherein the capacitor further includes a first N-type well region disposed in the P-type semiconductor region, and the first N-type heavily doped region is disposed in the first N-type well region.

13. The read-only memory as claimed in claim 12, wherein the N-channel field-effect transistor comprises: a second dielectric block disposed on the P-type semiconductor region; a conductive gate disposed on the second dielectric block, wherein the conductive gate is coupled to the electrode block; and a second heavily doped N-type region and a third heavily doped N-type region disposed on the P-type semiconductor region, the second heavily doped N-type region and the third heavily doped N-type region being located on opposite sides of the P-type semiconductor region directly below the conductive gate, the second heavily doped N-type region being coupled to the common source line, and the third heavily doped N-type region being coupled to the bit line through the electronic switch.

14. The read-only memory as claimed in claim 13, wherein the N-channel field-effect transistor further includes a second N-type well region disposed in the P-type semiconductor region, and the second N-type heavily doped region is disposed in the second N-type well region.

15. The read-only memory as described in claim 11, wherein when the N-channel field-effect transistor and the capacitor are selected for programming operation, the P-type semiconductor region is coupled to ground voltage, the word line is coupled to a high voltage, the common-source line is coupled to ground voltage, the bit line is electrically floating, and the high voltage is greater than the ground voltage.

16. The read-only memory as described in claim 11, wherein when the N-channel field-effect transistor and the capacitor are not selected for programming, the P-type semiconductor region is coupled to ground voltage, the word line is coupled to ground voltage, the common-source line is coupled to ground voltage, and the bit line is electrically floating.

17. The read-only memory as described in claim 11, wherein when the N-channel field-effect transistor and the capacitor are selected for an erase operation, the P-type semiconductor region is coupled to ground voltage, the word line is coupled to ground voltage, the common-source line is coupled to a high voltage, the bit line is electrically floating, and the high voltage is greater than the ground voltage.

18. The read-only memory as described in claim 11, wherein when the N-channel field-effect transistor and the capacitor are not selected for an erase operation, the P-type semiconductor region is coupled to ground voltage, the word line is coupled to a medium voltage, the common-source line is coupled to a high voltage, the bit line is electrically floating, the high voltage is greater than the medium voltage, and the medium voltage is greater than the ground voltage.

19. The read-only memory as described in claim 11, wherein the strip is coupled between the gate and the finger of the N-channel field-effect transistor.

20. The read-only memory as described in claim 11, wherein the P-type semiconductor region is a semiconductor substrate or an epitaxial layer disposed on a semiconductor substrate.

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