Semiconductor device with neck layer and method for fabricating the same

Abstract

The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a substrate with an active region; a gate structure disposed in a gate trench in the active region; an impurity region disposed adjacent to the gate structure; at least two bit line structures positioned on the substrate; a contact layer positioned on the substrate and between the at least two bit line structures; and a conductive neck layer positioned on the contact layer and between the at least two bit line structures. The impurity region has an upper portion defining a top surface of the impurity region and a lower portion defining a bottom surface of the impurity region. A width of the top surface of the impurity region is greater than a width of the bottom surface of the impurity region.

Description

Technical Field

[0001] This application claims priority to U.S. Patent Application No. 19 / 055,762 (i.e., priority date "February 18, 2025"), the contents of which are incorporated herein by reference in their entirety.

[0002] This disclosure relates to a semiconductor device and a method for manufacturing a semiconductor device. In particular, it relates to a semiconductor device having a neck layer and a method for manufacturing a semiconductor device having a neck layer. Prior Technology

[0003] Semiconductor components are used in a wide range of electronic applications, including personal computers, mobile phones, digital cameras, and other electronic devices. To meet the ever-increasing demands for computing power, the size of semiconductor components continues to shrink. However, this shrinkage also brings increasingly frequent and impactful challenges. Therefore, improving quality, yield, performance, and reliability while reducing complexity remains a challenge.

[0004] The above description of "prior art" is merely to provide background information and does not constitute an admission that the above description of "prior art" discloses the subject matter of this disclosure. It does not constitute prior art to this disclosure, and no description of the above "prior art" should be considered part of the "prior art" in this case. Summary of the Invention

[0005] One aspect of this disclosure provides a semiconductor device. The semiconductor device includes a substrate having an active region; a gate structure disposed within a gate trench in the active region; a duplication region disposed adjacent to the gate structure; at least two bit line structures located on the substrate; a contact layer located on the substrate and between the at least two bit line structures; and a conductive neck layer located on the contact layer and between the at least two bit line structures. The duplication region has an upper portion and a lower portion, the upper portion defining a top surface of the duplication region, and the lower portion defining a bottom surface of the duplication region. The width of the top surface of the duplication region is greater than the width of the bottom surface of the duplication region.

[0006] Another aspect of this disclosure provides a semiconductor device. The semiconductor device includes a substrate having a first top surface; a first gate electrode and a second gate electrode disposed within the substrate, wherein the second gate electrode is located above the first gate electrode; a first barrier layer and a second barrier layer disposed within the substrate, wherein the second barrier layer is located on the first barrier layer and the first gate electrode; a gate cap layer disposed on the second gate electrode; at least two bit line structures located on the substrate; a contact layer located on the substrate and between the at least two bit line structures; and a conductive neck layer located on the contact layer and between the at least two bit line structures. The first gate electrode includes a first component and a second component, the first component being surrounded by the first barrier layer, the second component extending from the first component toward the first top surface, and the second component protruding from the first barrier layer. The second gate electrode is located on the second barrier layer and surrounds the second component of the second barrier layer and the first gate electrode. The width of the top surface of one of the conductive neck layers is greater than the width of the bottom surface of one of the conductive neck layers.

[0007] Another aspect of this disclosure provides a method for manufacturing a semiconductor device. The method includes providing a substrate having an isolation region defining an active region; forming a gate structure within the substrate; forming at least two bit line structures on the substrate; forming at least two separator layers on the substrate; forming a contact layer on the substrate; and forming a conductive neck layer on the contact layer. The width of a top surface of one of the conductive neck layers is greater than the width of a bottom surface of one of the conductive neck layers.

[0008] Another aspect of this disclosure provides a method for manufacturing a semiconductor device. The method includes providing a substrate having a first top surface, wherein the substrate includes an isolation region surrounding an active region; forming a gate structure within the active region of the substrate; forming a first recess and a second recess adjacent to the gate structure within the substrate; forming an impurity region within the first recess and the second recess; forming at least two bit line structures on the substrate; forming at least two separator layers on the substrate; forming a contact opening on the substrate; forming a contact layer on the substrate and within the contact opening; and forming a conductive neck layer on the contact layer. The contact opening is surrounded by the at least two separator layers and the at least two bit line structures. The impurity region has an upper portion and a lower portion, the upper portion defining a top surface of the impurity region, and the lower portion defining a bottom surface of the impurity region. The width of the top surface of the impurity region is greater than the width of the bottom surface of the impurity region.

[0009] The semiconductor device design disclosed herein increases the overlap area between the conductive neck layer and the landing pad by using a conductive neck layer with a wider top surface. This reduces defects and complexity associated with manufacturing the semiconductor device.

[0010] The foregoing has provided a fairly broad overview of the technical features and advantages of this disclosure, so as to provide a better understanding of the detailed description of this disclosure that follows. Other technical features and advantages constituting the subject matter of this disclosure will be described below. Those skilled in the art to which this disclosure pertains will understand that the concepts and specific embodiments disclosed below can be readily used to modify or design other structures or processes to achieve the same purpose as this disclosure. Those skilled in the art to which this disclosure pertains will also understand that such equivalent constructions cannot depart from the spirit and scope of this disclosure as defined in the appended claims. Simple Explanation of the Diagram

[0011] For a better understanding of all aspects of this disclosure, please refer to the following detailed description and diagrams. It should be noted that, in accordance with industry standard practice, the features are not drawn to scale. In fact, the dimensions of the features may be arbitrarily enlarged or reduced for clarity of discussion. Figure 1 shows a method for manufacturing a semiconductor device according to an embodiment of the present disclosure in the form of a flowchart. Figure 2 shows a top view of an intermediate semiconductor element according to an embodiment of the present disclosure. Figure 3 shows a schematic cross-sectional view along lines A-A', B-B', and C-C' in Figure 2. Figure 4 shows a top view of an intermediate semiconductor element according to an embodiment of the present disclosure. Figure 5 shows a schematic cross-sectional view along lines A-A', B-B', and C-C' in Figure 4. Figure 6 shows a top view of an intermediate semiconductor element according to an embodiment of the present disclosure. Figure 7 shows a schematic cross-sectional view along lines A-A', B-B', and C-C' in Figure 6. Figure 8 shows a top view of an intermediate semiconductor element according to an embodiment of the present disclosure. Figure 9 shows a schematic cross-sectional view along lines A-A', B-B', and C-C' in Figure 8, illustrating a portion of the manufacturing process of a semiconductor device according to an embodiment of the present disclosure. Figure 10 shows a schematic cross-sectional view along lines A-A', B-B', and C-C' in Figure 8, illustrating a portion of the manufacturing process of a semiconductor device according to an embodiment of the present disclosure. Figure 11 shows a top view of an intermediate semiconductor element according to an embodiment of the present disclosure. Figure 12 shows a schematic cross-sectional view along lines A-A', B-B', and C-C' in Figure 11. Figure 13 shows a top view of an intermediate semiconductor element according to an embodiment of the present disclosure. Figure 14 shows a schematic cross-sectional view along lines A-A', B-B', and C-C' in Figure 13, illustrating a portion of the manufacturing process of a semiconductor device according to an embodiment of the present disclosure. Figure 15 shows a schematic cross-sectional view along lines A-A', B-B', and C-C' in Figure 13, illustrating a portion of the manufacturing process of a semiconductor device according to an embodiment of the present disclosure. Figure 16 shows a top view of an intermediate semiconductor element according to an embodiment of the present disclosure. Figure 17 shows a schematic cross-sectional view along lines A-A', B-B', and C-C' in Figure 16. Figure 18 shows a top view of an intermediate semiconductor element according to an embodiment of the present disclosure. Figure 19 shows a schematic cross-sectional view along lines A-A', B-B', and C-C' in Figure 18, illustrating a portion of the manufacturing process of a semiconductor device according to an embodiment of the present disclosure. Figure 20 shows a schematic cross-sectional view along lines A-A', B-B', and C-C' in Figure 18, illustrating a portion of the manufacturing process of a semiconductor device according to an embodiment of the present disclosure. Figure 21 shows a schematic cross-sectional view along lines A-A', B-B', and C-C' in Figure 18, illustrating a portion of the manufacturing process of a semiconductor device according to an embodiment of the present disclosure. Figure 22 shows a top view of an intermediate semiconductor element according to an embodiment of the present disclosure. Figure 23 shows a schematic cross-sectional view along lines A-A', B-B', and C-C' in Figure 22, illustrating a portion of the manufacturing process of a semiconductor device according to an embodiment of the present disclosure. Figure 24 shows a schematic cross-sectional view along lines A-A', B-B', and C-C' in Figure 22, illustrating a portion of the manufacturing process of a semiconductor device according to an embodiment of the present disclosure. Figure 25 shows a top view of an intermediate semiconductor element according to an embodiment of the present disclosure. Figure 26 shows a schematic cross-sectional view along lines A-A', B-B', and C-C' in Figure 25. Figure 27 shows a top view of an intermediate semiconductor element according to an embodiment of the present disclosure. Figure 28 shows a schematic cross-sectional view along lines A-A', B-B', and C-C' in Figure 27. Figures 29 to 30 show schematic cross-sectional views of semiconductor devices according to some embodiments of the present disclosure. Figure 31 shows a schematic cross-sectional view along lines A-A', B-B', and C-C' in Figure 27. Figures 32 to 42 are schematic cross-sectional views along line B-B' in Figure 27, illustrating a portion of the manufacturing process of a semiconductor device according to some embodiments of this disclosure. Implementation

[0012] The following disclosure provides many different embodiments or examples to implement different features of the invention. Specific examples of components and configurations are described below to simplify this disclosure. Of course, these are merely examples and should not be construed as limiting the scope of this disclosure. For example, when the description refers to a first feature being formed on or above a second feature, it may include embodiments where the first and second features are in direct contact, or embodiments where other features are formed between the first and second features, such that the first and second features are not in direct contact. Furthermore, reference numerals and / or designations may be repeated in various examples in this disclosure. These repetitions are for simplification and clarity and are not intended to limit the relationship between the different embodiments and / or configurations discussed.

[0013] Furthermore, the spatially related terms used herein, such as "below," "under," "down," "above," "up," and similar terms, are for the convenience of describing the relationship between one element or feature shown in the diagram and one or more other elements or features. These spatially related terms are used to cover different orientations of the device in use or operation, in addition to the orientation depicted in the diagram. The instrument may be turned to different orientations (rotated 90 degrees or other orientations), and the spatially related terms used therein can be interpreted accordingly.

[0014] It should be understood that when a component or layer is referred to as being "connected to" or "coupled to" another component or layer, it can be directly connected to or coupled to another component or layer, or there may be a component or layer in between.

[0015] It should be understood that although terms such as "first," "second," etc., are used herein to describe various elements, these elements are not limited by these terms. Unless otherwise stated, these terms are used only to distinguish one element from other elements. Thus, for example, the first element, first component, or first segment discussed below may be referred to as the second element, second component, or second segment, without departing from the teachings of this disclosure.

[0016] Unless the context otherwise requires, the terms used here, such as “same,” “equal,” “plane,” or “coplanar,” when referring to orientation, layout, location, shape, size, quantity, or other measure, do not necessarily mean exactly the same orientation, layout, location, shape, size, quantity, or other measure. Rather, they mean that these orientations, layouts, locations, shapes, sizes, quantities, or other measures are substantially the same within acceptable variations, for example, variations that may arise during the manufacturing process. The term “substantially” may be used here to express this meaning. For example, items described as “substantially the same,” “substantially equal,” or “substantially plane” may be exactly the same, equal, or plane, or the same, equal, or plane within acceptable variations that may arise during the manufacturing process.

[0017] In this disclosure, semiconductor devices generally refer to devices that can operate using semiconductor properties, and optoelectronic devices, light-emitting display devices, semiconductor circuits and electronic devices all fall under the category of semiconductor devices.

[0018] It should be noted that in the description disclosed herein, "above" (or "up") corresponds to the direction of the arrow in the Z direction, while "below" (or "down") corresponds to the opposite direction of the arrow in the Z direction.

[0019] Figure 1 shows a method 10 for manufacturing a semiconductor element 1A according to an embodiment of the present disclosure, in the form of a flowchart. Figure 2 shows a top view of an intermediate semiconductor element according to an embodiment of the present disclosure. Figure 3 shows a cross-sectional view along lines A-A', B-B', and C-C' in Figure 2. Figure 4 shows a top view of an intermediate semiconductor element according to an embodiment of the present disclosure. Figure 5 shows a cross-sectional view along lines A-A', B-B', and C-C' in Figure 4.

[0020] Referring to Figures 1 to 5, in step S11, a substrate 101 is provided, an isolation layer 103 is formed in the substrate 101 to define a plurality of active regions AA, and a plurality of character line structures 200 intersecting with the plurality of active regions AA are formed in the substrate 101.

[0021] Referring to Figures 2 and 3, substrate 101 may comprise a bulk semiconductor substrate. The bulk semiconductor substrate may be formed, for example, of elemental semiconductors, such as silicon or germanium; it may be formed of compound semiconductors, such as silicon germanium, silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, indium antimonide, or other group III-V or group II-VI compound semiconductors; or it may be formed of a combination of the foregoing.

[0022] In some embodiments, substrate 101 may include a semiconductor-on-insulator structure comprising, from bottom to top, a disposal substrate, an insulating layer, and a topmost semiconductor material layer. The disposal substrate and the topmost semiconductor material layer may be formed of the same material as the bulk semiconductor substrate described above. The insulating layer may be a crystalline or amorphous dielectric material, such as oxides and / or nitrides. For example, the insulating layer may be a dielectric oxide, such as silicon oxide. In another example, the insulating layer may be a dielectric nitride, such as silicon nitride or boron nitride. In yet another example, the insulating layer may comprise a stack of dielectric oxides and dielectric nitrides, such as silicon oxide, silicon nitride, and / or boron nitride stacked in any order. The insulating layer may have a thickness between about 10 nm and about 200 nm. The insulating layer can reduce leakage current between adjacent elements in substrate 101 and reduce parasitic capacitance associated with the source / drain.

[0023] It should be noted that the term "about," when used to modify the amount of ingredients, components, or reactants used in this disclosure, refers to possible numerical variations, such as those caused by typical measurement and liquid handling procedures used in the preparation of concentrates or solutions. Furthermore, variations may arise from unexpected errors in measurement procedures, differences in the manufacture, source, or purity of the ingredients used to prepare the composition or implement the method, or other factors. On one hand, "about" refers to within 10% of the reported value. On the other hand, "about" refers to within 5% of the reported value. Yet another aspect refers to within 10%, 9%, 8%, 7%, 6%, 5%, 4%, 3%, 2%, or 1% of the reported value.

[0024] Referring to Figures 2 and 3, an isolation layer 103 can be formed within the substrate 101. A series of deposition processes can be performed to deposit a pad oxide layer and a pad nitride layer on the substrate 101. Optical lithography processes and subsequent etching processes, such as anisotropic dry etching processes, can be performed to form trenches that penetrate the pad oxide layer and the pad nitride layer and extend into the substrate 101. An insulating material can be deposited within the trenches, followed by a planarization process such as chemical mechanical polishing (CMP) until the top surface of the substrate 101 is exposed to remove excess deposited material, providing a generally flat surface for subsequent process steps, and simultaneously forming the isolation layer 103. The insulating material can be, for example, silicon oxide or other suitable insulating materials. The isolation layer 103 can define a plurality of active regions AA within the substrate 101.

[0025] It should be noted that, in the description disclosed herein, the surface of the element (or feature) at its highest vertical height along the Z-axis is referred to as the top surface of the aforementioned element (or feature). The surface of the element (or feature) at its lowest vertical height along the Z-axis is referred to as the bottom surface of the aforementioned element (or feature).

[0026] It should be noted that each of the plurality of active regions AA may include a portion of the substrate 101 and the space above the aforementioned portion of the substrate 101. Describing an element as disposed on the active region AA means that the element is disposed on the top surface of the aforementioned portion of the substrate 101. Describing an element as disposed within the active region AA means that the element is disposed within the aforementioned portion of the substrate 101; however, the top surface of the element may be flush with the top surface of the aforementioned portion of the substrate 101. Describing an element as disposed above the active region AA means that the element is disposed above the top surface of the aforementioned portion of the substrate 101.

[0027] Referring to Figures 2 and 3, a plurality of impurity regions 105 can be formed within a plurality of active regions AA. In some embodiments, a planting process can be used to form the plurality of impurity regions 105. In other words, a plurality of impurity regions 105 are formed by converting a portion of the active regions AA into impurity regions 105. The dopants in the planting process can include P-type impurities (dopants) or N-type impurities (dopants). P-type impurities can be added to intrinsic semiconductors to create valence electron vacancies. Examples of P-type impurities in silicon-containing substrates include, but are not limited to, boron, aluminum, gallium, and indium. N-type impurities can be added to intrinsic semiconductors to contribute free electrons to the intrinsic semiconductor. Examples of N-type impurities in silicon-containing substrates include, but are not limited to, antimony, arsenic, and phosphorus. In some embodiments, the dopant concentration of the plurality of impurity regions 105 can be between approximately 1E19 atoms / cm³ and approximately 1E21 atoms / cm³. After the implantation process is implemented, the multiple impurity regions 105 may have electrical types such as N-type or P-type.

[0028] Referring to Figures 4 and 5, a plurality of character line trenches TR can be formed within the substrate 101 to define the locations of a plurality of character line structures 200. The plurality of character line trenches TR can be formed using an optical lithography process and subsequent etching process. In some embodiments, in a top view, the character line trenches TR may have a linear profile and extend along the X direction, spanning (or intersecting) a plurality of impurity regions 105. For example, each impurity region 105 may intersect with two character line trenches TR. The plurality of character line trenches TR can divide each of the plurality of impurity regions 105 into a plurality of common source regions 105-1 and a plurality of drain regions 105-3. For an impurity region 105, a common source region 105-1 may be formed between the two word line trenches TR, and two drain regions 105-3 may be formed between the isolation layer 103 and the two word line trenches TR, respectively.

[0029] Referring to Figures 4 and 5, multiple character line structures 200 (e.g., the two character line trenches TR mentioned above) can be formed within multiple character line trenches TR (e.g., the two character line trenches TR mentioned above). For simplicity, clarity, and ease of description, only one character line structure 200 is described. The character line structure 200 may include a character line dielectric layer 201, a character line barrier layer 203, a character line conductive layer 205, and a character line capping layer 207.

[0030] Referring to Figures 4 and 5, a character line dielectric layer 201 can be conformally formed on the inner surface of the character line trench TR. The character line dielectric layer 201 may have a U-shaped cross-sectional profile. In other words, the character line dielectric layer 201 can be formed inwardly within the active region AA. In some embodiments, a thermal oxidation process can be used to form the character line dielectric layer 201. For example, the character line dielectric layer 201 can be formed on the inner surface of the character line trench TR via an oxidation process. In some embodiments, a deposition process, such as chemical vapor deposition (CVD) or atomic layer deposition (ALD), can be used to form the character line dielectric layer 201. The character line dielectric layer 201 may comprise a material with a high dielectric constant, an oxide, a nitride, an oxynitride, or a combination thereof. In some embodiments, after depositing a polycrystalline silicon substrate, the character line dielectric layer 201 can be formed on the polycrystalline silicon substrate via radical oxidation. In some embodiments, after forming the silicon nitride substrate, a word line dielectric layer 201 may be formed on the silicon nitride substrate via free radical oxidation.

[0031] In some embodiments, the high dielectric constant material may comprise a hafnium-containing material. The hafnium-containing material may be, for example, hafnium oxide, hafnium silicon oxide, hafnium silicon nitride, or a combination thereof. In some embodiments, the high dielectric constant material may be, for example, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, zirconium silicon nitride, aluminum oxide, or a combination thereof.

[0032] Referring to Figures 4 and 5, a word line barrier layer 203 can be conformally formed on the word line dielectric layer 201 and within the word line trench TR. In some embodiments, the word line barrier layer 203 may be formed, for example, of titanium nitride, titanium, or a combination thereof. In some embodiments, the word line barrier layer 203 may be formed, for example, of titanium nitride. In some embodiments, the word line barrier layer 203 may be formed, for example, using atomic layer deposition, physical vapor deposition (PVD), chemical vapor deposition, or other suitable deposition processes.

[0033] Referring to Figures 4 and 5, a character line conductive layer 205 can be formed on the character line barrier layer 203 and within the character line trench TR. In some embodiments, to form the character line conductive layer 205, a conductive layer filling the character line trench TR can be formed, followed by a recess process. The recess process can be implemented using an etch-back process or by sequentially performing a planarization process and an etch-back process. The character line conductive layer 205 may have a recessed shape that partially fills the character line trench TR. In other words, the top surface of the character line conductive layer 205 may be lower than the top surface of the substrate 101.

[0034] In some embodiments, the character line conductive layer 205 may comprise a metal, a metal nitride, or a combination thereof. For example, the character line conductive layer 205 may be formed of titanium nitride, tungsten, or titanium nitride / tungsten. After conformally depositing titanium nitride, a titanium nitride / tungsten structure may be formed, wherein tungsten is used to partially fill the character line trench TR. Alternatively, the character line conductive layer 205 may be formed using titanium nitride alone or tungsten alone. In some embodiments, the character line conductive layer 205 may be formed, for example, of a conductive material, such as doped polycrystalline silicon, doped polycrystalline silicon-germanium, or a combination thereof. In some embodiments, the character line conductive layer 205 may be formed, for example, of tungsten, aluminum, titanium, copper, similar materials, or a combination thereof.

[0035] Referring to Figures 4 and 5, a dielectric material can be deposited, for example, using chemical vapor deposition, to completely fill the word line trench TR and cover the top surface of the substrate 101. A planarization process, such as chemical mechanical polishing, can be implemented to provide a generally flat surface for subsequent process steps to form the word line capping layer 207. In some embodiments, the word line capping layer 207 can be formed, for example, from silicon nitride or other suitable dielectric materials.

[0036] Figure 6 shows a top view of an intermediate semiconductor device according to an embodiment of the present disclosure. Figure 7 shows a cross-sectional view along lines A-A', B-B', and C-C' in Figure 6. Figure 8 shows a top view of an intermediate semiconductor device according to an embodiment of the present disclosure. Figure 9 shows a cross-sectional view along lines A-A', B-B', and C-C' in Figure 8, illustrating a portion of the manufacturing process of the semiconductor device according to an embodiment of the present disclosure. Figure 10 shows a cross-sectional view along lines A-A', B-B', and C-C' in Figure 8, illustrating a portion of the manufacturing process of the semiconductor device according to an embodiment of the present disclosure.

[0037] Referring to Figures 1 and 6 to 10, in step S13, a plurality of bit line structures 300 are formed on the substrate 101, an inner spacer layer 401 is conformally formed on the substrate 101, and an outer spacer layer 403 is conformally formed on the inner spacer layer 401.

[0038] Referring to Figures 6 and 7, a bottom dielectric layer 107 may be formed on the substrate 101. In some embodiments, the bottom dielectric layer 107 may be formed of a material that is etch-selective to both the substrate 101 and the insulating layer 103. In some embodiments, the bottom dielectric layer 107 may be formed, for example, of silicon nitride, boron nitride, boron phosphide, boron carbide, or a combination thereof. In some embodiments, the bottom dielectric layer 107 may be formed, for example, of silicon nitride. In some embodiments, the bottom dielectric layer 107 may be formed using, for example, chemical vapor deposition, plasma-enhanced chemical vapor deposition, or other suitable deposition processes.

[0039] Referring to Figures 6 and 7, a plurality of bit line contacts 309 can be formed, penetrating the bottom dielectric layer 107 and extending to a plurality of common source regions 105-1. In some embodiments, the plurality of bit line contacts 309 may be formed, for example, from tungsten, cobalt, zirconium, tantalum, titanium, aluminum, ruthenium, copper, metal carbides (e.g., tantalum carbide, titanium carbide, magnesium tantalum carbide), metal nitrides (e.g., titanium nitride), transition metal aluminum nitrides, or combinations thereof. In some embodiments, the plurality of bit line contacts 309 may have a square cross-sectional profile in a top view, but this disclosure is not limited thereto. In some embodiments, the plurality of bit line contacts 309 may have a rectangular, circular, or other suitable cross-sectional profile in a top view.

[0040] Referring to Figures 8 and 9, a plurality of bitline structures 300, each electrically connected to a plurality of bitline contacts 309, can be formed on the bottom dielectric layer 107. In top view, the plurality of bitline structures 300 can extend along the Y direction and be separated from each other. In other words, in top view, the plurality of bitline structures 300 can intersect with a plurality of wordline structures 200. For simplicity, clarity, and ease of description, only one bitline structure 300 is described. In some embodiments, the bitline structure 300 may include a bitline top conductive layer 301 and a bitline capping layer 307.

[0041] A top conductive layer 301 electrically connected to the bit line contact 309 can be formed on the bit line contact 309. In some embodiments, the top conductive layer 301 can be formed, for example, of titanium nitride, tungsten, titanium, nickel, platinum, tantalum, cobalt, silver, copper, aluminum, other suitable conductive materials, or combinations thereof. A bit line capping layer 307 can be formed on the top conductive layer 301. In some embodiments, the bit line capping layer 307 can be formed, for example, of silicon nitride or other suitable insulating materials.

[0042] Referring to Figure 10, an interstitial layer 401 can be formed on the substrate 101 to cover the plurality of bit-line structures 300 and the bottom dielectric layer 107. Specifically, the interstitial layer 401 can be conformally formed on the bottom dielectric layer 107, on the sides 300S of the plurality of bit-line structures 300, and on the top surface 307TS of the plurality of bit-line structures 300. In some embodiments, the interstitial layer 401 can be formed, for example, from silicon oxide or other suitable insulating oxides. In some embodiments, the interstitial layer 401 can be formed, for example, using atomic layer deposition, chemical vapor deposition, or other suitable deposition processes.

[0043] Referring to Figure 10, an outer spacer layer 403 can be conformally formed on the inner spacer layer 401. In some embodiments, the outer spacer layer 403 may be formed of the same material as the bit line capping layer 307. In some embodiments, the outer spacer layer 403 may be formed, for example, of silicon nitride or other suitable insulating materials. In some embodiments, the outer spacer layer 403 may be formed, for example, using atomic layer deposition, chemical vapor deposition, or other suitable deposition processes.

[0044] Figure 11 shows a top view of an intermediate semiconductor element according to an embodiment of the present disclosure. Figure 12 shows a cross-sectional view along lines A-A', B-B', and C-C' in Figure 11. Figure 13 shows a top view of an intermediate semiconductor element according to an embodiment of the present disclosure. Figure 14 shows a cross-sectional view along lines A-A', B-B', and C-C' in Figure 13, illustrating a portion of the manufacturing process of semiconductor element 1A according to an embodiment of the present disclosure. Figure 15 shows a cross-sectional view along lines A-A', B-B', and C-C' in Figure 13, illustrating a portion of the manufacturing process of semiconductor element 1A according to an embodiment of the present disclosure. Figure 16 shows a top view of an intermediate semiconductor element according to an embodiment of the present disclosure. Figure 17 shows a cross-sectional view along lines A-A', B-B', and C-C' in Figure 16.

[0045] It should be noted that some elements have been omitted in the top view for clarity.

[0046] Referring to Figures 1 and 11 to 17, in step S15, a sacrificial layer 801 is formed between a plurality of bit line structures 300, a first masking layer 701 containing a line pattern P1 is formed on the sacrificial layer 801 to partially expose the sacrificial layer 801 and the outer spacer layer 403, the sacrificial layer 801 is selectively removed to form a plurality of partition openings OP1, and a plurality of partition layers 601 are formed within the plurality of partition openings OP1.

[0047] Referring to Figures 11 and 12, a sacrificial layer 801 may be formed on the bottom dielectric layer 107 to cover a plurality of bit-line structures 300, an inner spacer layer 401, and an outer spacer layer 403. In some embodiments, the sacrificial layer 801 may be formed, for example, from a material having etch selectivity for the outer spacer layer 403. In some embodiments, the sacrificial layer 801 may be formed, for example, from silicon oxynitride, silicon oxynitride, or other suitable materials. In some embodiments, the sacrificial layer 801 may be formed, for example, using chemical vapor deposition, plasma-enhanced chemical vapor deposition, or other suitable deposition processes. In some embodiments, a planarization process, such as chemical mechanical polishing, may be performed until the top surface 403TS of the outer spacer layer 403 is exposed to remove excess material and provide a generally flat surface for subsequent process steps.

[0048] It should be noted that, in this disclosure, silicon nitride refers to a substance containing silicon, nitrogen, and oxygen, wherein the proportion of oxygen is greater than the proportion of nitrogen. Silicon nitride oxide refers to a substance containing silicon, oxygen, and nitrogen, wherein the proportion of nitrogen is greater than the proportion of oxygen.

[0049] Referring to Figures 11 and 12, a first masking layer 701 may be formed on the sacrificial layer 801. In some embodiments, the first masking layer 701 may be a photoresist layer. From a top-view perspective, the line pattern P1 of the first masking layer 701 may comprise a plurality of rectangular spaces extending in the X direction and alternately arranged along the Y direction. The sacrificial layer 801 and the outer spacer layer 403 may be partially exposed through the aforementioned spaces.

[0050] Referring to Figures 13 and 14, the sacrificial layer 801 exposed by the line pattern P1 of the first masking layer 701 is selectively removed. In some embodiments, the sacrificial layer 801 can be removed by an anisotropic etching process, such as an anisotropic dry etching process. After removing the sacrificial layer 801, a plurality of separating openings OP1 can be formed at the locations where the sacrificial layer 801 is exposed by the line pattern P1 of the first masking layer 701. After forming these separating openings OP1, the first masking layer 701 can be removed.

[0051] Referring to Figure 15, a spacer material layer 803 may be formed on the sacrificial layer 801 to completely fill the plurality of spacer openings OP1. In some embodiments, the spacer material layer 803 may be a material that is etch-selective on the sacrificial layer 801. In some embodiments, the spacer material layer 803 may be the same material as the bit line capping layer 307 or the outer spacer layer 403. In some embodiments, the spacer material layer 803 may be formed, for example, from silicon nitride or other suitable insulating materials. In some embodiments, the spacer material layer 803 may be formed, for example, using chemical vapor deposition or other suitable deposition processes.

[0052] Referring to Figures 16 and 17, a planarization process, such as chemical mechanical polishing, can be performed until the top surface 403TS of the outer spacer layer 403 is exposed to remove excess material, provide a generally flat surface for subsequent process steps, and transform the spacer layer 803 into a plurality of spacer layers 601. In top view, each of the plurality of spacer layers 601 may have a linear (or rectangular) cross-sectional profile extending along the X direction. The plurality of spacer layers 601 may be arranged alternately along the X direction, with each corresponding bit line structure 300 located between two adjacent spacer layers 601. In the Y direction, the plurality of spacer layers 601 may be arranged alternately with sacrificial layers 801 inserted between the spacer layers 601. In top view, the arrangement of the plurality of spacer layers 601 and the plurality of bit line structures 300 can divide the sacrificial layer 801 into multiple segments.

[0053] Figure 18 shows a top view of an intermediate semiconductor element according to an embodiment of the present disclosure. Figures 19 to 21 each show cross-sectional views along lines A-A', B-B', and C-C' in Figure 18, illustrating a portion of the manufacturing process of semiconductor element 1A according to an embodiment of the present disclosure. Figure 22 shows a top view of an intermediate semiconductor element according to an embodiment of the present disclosure. Figures 23 and 24 show cross-sectional views along lines A-A', B-B', and C-C' in Figure 22, respectively, illustrating a portion of the manufacturing process of semiconductor element 1A according to an embodiment of the present disclosure. Figure 25 shows a top view of an intermediate semiconductor element according to an embodiment of the present disclosure. Figure 26 shows a cross-sectional view along lines A-A', B-B', and C-C' in Figure 25. Figure 27 shows a top view of an intermediate semiconductor element according to an embodiment of the present disclosure. Figure 28 shows a cross-sectional view along lines A-A', B-B', and C-C' in Figure 27.

[0054] Referring to Figures 1 and 18 to 28, in step S17, the sacrificial layer 801 is selectively removed to form a plurality of contact openings OP2, a plurality of contact layers 501 are formed within the plurality of contact openings OP2, a plurality of conductive neck layers 503 are formed on the plurality of contact layers 501, and a plurality of landing pads 505 are formed on the plurality of conductive neck layers 503.

[0055] Referring to Figures 18 and 19, an etching process can be used to selectively remove the sacrificial layer 801. For example, the sacrificial layer 801 can be removed using an anisotropic etching process. After removing the sacrificial layer 801, a plurality of contact openings OP2 can be formed in the locations previously occupied by multiple segments of the sacrificial layer 801. For simplicity, clarity, and ease of description, only one contact opening OP2 is described. In a cross-sectional view, the contact opening OP2 can be disposed on the bottom dielectric layer 107. In a top view, the contact opening OP2 can be surrounded by two adjacent separator layers 601 in the Y direction and two adjacent bit line structures 300 in the X direction (with an inner spacer layer 401 and an outer spacer layer 403 disposed between the bit line structures 300).

[0056] In some embodiments, the etch selectivity of silicon oxide during anisotropic etching may be similar to that of silicon nitride. In some embodiments, the etch selectivity of silicon oxide may be slightly greater than that of silicon nitride. For example, during anisotropic etching, the silicon oxide to silicon nitride etch rate ratio may be between about 3.0 and about 1.1, between about 2.0 and about 1.1, or between about 1.5 and about 1.2. Because the etch rates of silicon oxide and silicon nitride are similar, the inner spacer layer 401, the outer spacer layer 403, and the bit line capping layer 307 may also be partially consumed during the removal of the sacrificial layer 801.

[0057] In some embodiments, the inner spacer layer 401, outer spacer layer 403, and bit line capping layer 307 adjacent to the sacrificial layer 801 may be consumed first. As a result, during the anisotropic etching process, the upper portions of the outer spacer layer 403, inner spacer layer 401, and bit line capping layer 307 adjacent to the plurality of contact openings OP2 become thinner, thus exhibiting a tapered profile and sloping sides 300S in these regions, as indicated by arrows CP1 and CP2.

[0058] In some embodiments, the outer spacer layer 403, inner spacer layer 401, and bit line cover layer 307 adjacent to the plurality of partition layers 601 experience less wear than those adjacent to the plurality of contact openings OP2. Therefore, the outer spacer layer 403, inner spacer layer 401, and bit line cover layer 307 adjacent to the plurality of partition layers 601 can maintain a rectangular cross-sectional profile and vertical sides 300S, as indicated by arrow CP3.

[0059] Referring to Figure 20, a punch-through etching process can be performed to remove portions of the outer spacer layer 403, the inner spacer layer 401, and the bottom dielectric layer 107 exposed by the plurality of contact openings OP2. In some embodiments, the punch-through etching process can be an anisotropic dry etching process. The punch-through etching process can extend the plurality of contact openings OP2 downward to the substrate 101. The punch-through etching process can divide the bottom dielectric layer 107, the inner spacer layer 401, and the outer spacer layer 403 into multiple portions, respectively. After the punch-through etching process, a plurality of drain regions 105-3 are exposed by the plurality of contact openings OP2.

[0060] Referring to Figure 21, a first conductive material layer 805 is conformally formed to fill a plurality of contact openings OP2. In some embodiments, the first conductive material layer 805 may be, for example, doped polycrystalline silicon, doped polycrystalline germanium, or doped polycrystalline silicon-germanium. In some embodiments, the first conductive material layer 805 may contain P-type dopants or N-type dopants. In some embodiments, the first conductive material layer 805 may be formed, for example, using atomic layer deposition, chemical vapor deposition, or other suitable deposition processes.

[0061] Referring to Figures 22 and 23, an etch-back process can be performed to remove a portion of the first conductive material 805. After the etch-back process, the remaining first conductive material 805 can be transformed into a plurality of contact layers 501 in a plurality of contact openings OP2. For simplicity, clarity, and ease of description, only one contact layer 501 is described. In some embodiments, the contact layer 501 may have a square or rectangular cross-sectional profile in a top view. The contact layer 501 is surrounded by two adjacent separator layers 601 in the Y direction and two adjacent bit line structures 300 in the X direction (with an inner spacer layer 401 and an outer spacer layer 403 disposed between the bit line structures 300). The contact layer 501 provides electrical connection to the corresponding drain regions 105-3.

[0062] Referring to Figure 24, a second conductive material layer 807 is deposited to completely fill the plurality of contact openings OP2 and cover the outer spacer layer 403, the inner spacer layer 401, the plurality of bit line structures 300, and the plurality of separator layers 601. In some embodiments, the second conductive material layer 807 may comprise, for example, tungsten, cobalt, zirconium, tantalum, titanium, aluminum, ruthenium, copper, metal carbides (e.g., tantalum carbide, titanium carbide, tantalum magnesium carbide), metal nitrides (e.g., titanium nitride), transition metal aluminum nitrides, or combinations thereof. In some embodiments, the second conductive material layer 807 may be, for example, titanium nitride, titanium, tungsten, or combinations thereof.

[0063] Referring to Figures 25 and 26, a planarization process, such as chemical mechanical polishing, can be performed until the top surface 307TS of the plurality of bit-line capping layers 307 is exposed to remove excess material and provide a generally flat surface for subsequent process steps. After the planarization process, the remaining second conductive material layer 807 can be transformed into a plurality of conductive neck layers 503. The plurality of conductive neck layers 503 can be formed on a plurality of contact layers 501.

[0064] For simplicity, clarity, and ease of description, only one conductive neck layer 503 is described. In some embodiments, in a top view, the conductive neck layer 503 is surrounded by two adjacent spacer layers 601 in the Y direction and two adjacent bit line structures 300 in the X direction (with an inner spacer layer 401 and an outer spacer layer 403 disposed between the bit line structures 300). In some embodiments, the width W1 of the top surface 503TS of the conductive neck layer 503 is greater than the width W2 of the bottom surface 503BS of the conductive neck layer 503. In some embodiments, the ratio of the width W1 of the top surface 503TS of the conductive neck layer 503 to the width W2 of the bottom surface 503BS of the conductive neck layer 503 may be between about 2.0 and about 1.3, between about 1.8 and about 1.3, and between about 1.7 and about 1.4.

[0065] In some embodiments, the conductive neck layer 503 may include two first sides FS. The two first sides FS may contact the sides 300S of a corresponding adjacent pair of bit line structures 300, with an inner spacer layer 401 and an outer spacer layer 403 disposed between them. Specifically, the inner spacer layer 401 may be disposed between the bit line structure 300 and the conductive neck layer 503, while the outer spacer layer 403 may be disposed between the inner spacer layer 401 and the conductive neck layer 503. In some embodiments, the two first sides FS may be inclined due to conformal contour to the outer spacer layer 403. The inclined first sides FS may cause the conductive neck layer 503 to have a cross-sectional profile that tapers towards the contact layer 501. In some embodiments, the conductive neck layer 503 may include two second sides SS. The two second sides SS may contact a corresponding separator layer 601. In some embodiments, the two second sides SS are vertical relative to the first sides FS.

[0066] In some embodiments, the width W3 of the top surface 307TS adjacent to the bit line capping layer 307 and the conductive neck layer 503 is narrower than the width W4 of the top surface 307TS adjacent to the bit line capping layer 307 and the separator layer 601. Therefore, in a top view, the widths W3 and W4 of the top surface 307TS of the bit line structure 300 vary in the Y direction.

[0067] In some embodiments, the width W3 of the top surface 307TS of the bit line capping layer 307 adjacent to the conductive neck layer 503 is narrower than the width W5 of the bottom surface 307BS of the bit line capping layer 307.

[0068] In some embodiments, the top surface 307TS of the bit line capping layer 307, the top surface 401TS of the inner spacer layer 401, the top surface 403TS of the outer spacer layer 403, the top surface 503TS of the conductive neck layer 503, and the top surface 601TS of the separator layer 601 may be substantially coplanar.

[0069] Referring to Figures 27 and 28, a top dielectric layer 109 may be formed on substrate 101 to completely cover a plurality of spacer layers 601, a plurality of inner spacer layers 401, a plurality of outer spacer layers 403, a plurality of conductive neck layers 503, and a plurality of bit line structures 300. In some embodiments, the top dielectric layer 109 may be formed, for example, from silicon dioxide, undoped silicate glass, fluorosilicate glass, borosilicate glass, spin-coated low-dielectric-constant dielectric layer, chemical vapor deposition low-dielectric-constant dielectric layer, or a combination thereof. As used herein, "low-dielectric-constant" refers to a dielectric material having a dielectric constant lower than that of silicon dioxide. In some embodiments, the top dielectric layer 109 may comprise a self-planarizing material, such as spin-coated glass or a spin-coated low-dielectric-constant dielectric material, such as SiLK™. The use of a self-planarizing dielectric material avoids the need for subsequent planarization steps. In some embodiments, a deposition process may be used to form the top dielectric layer 109, and the deposition process may include, for example, chemical vapor deposition, plasma-enhanced chemical vapor deposition, vapor deposition, or spin coating.

[0070] Referring to Figures 27 and 28, a plurality of landing pads 505 may be formed through the top dielectric layer 109. A plurality of landing pads 505 may be formed on a plurality of conductive neck layers 503. For simplicity, clarity, and ease of description, only one landing pad 505 is described. In some embodiments, the landing pad 505 may partially overlap the conductive neck layer 503 in a top view. In some embodiments, the landing pad 505 may be formed of the same material as the conductive neck layer 503. In some embodiments, the landing pad 505 may be formed, for example, of tungsten, cobalt, zirconium, tantalum, titanium, aluminum, ruthenium, copper, metal carbides (e.g., tantalum carbide, titanium carbide, magnesium tantalum carbide), metal nitrides (e.g., titanium nitride), transition metal aluminum compounds, or combinations thereof.

[0071] By utilizing the wider top surface 503TS of the conductive neck layer 503, the overlap margin between the conductive neck layer 503 and the landing pad 505 can be increased. This improvement can reduce defects (such as overlap alignment errors) and reduce the complexity of manufacturing the semiconductor device 1A.

[0072] Figures 29 and 30 show schematic cross-sectional views of semiconductor elements 1B and 1C according to some embodiments of the present disclosure.

[0073] Referring to Figure 29, semiconductor element 1B may have a structure similar to that shown in Figure 28. Elements that are the same as or similar to those in Figure 28 in Figure 29 are labeled with similar reference numerals, and repeated descriptions are omitted.

[0074] In semiconductor device 1B, bit line structure 300 may include a bottom conductive layer 305, a middle conductive layer 303, a top conductive layer 301, and a capping layer 307.

[0075] The bottom conductive layer 305 of the bit line may be disposed on the bit line contact 309. In some embodiments, the bottom conductive layer 305 may be formed, for example, by doped polycrystalline silicon, doped polycrystalline germanium, doped polycrystalline silicon-germanium, or a combination thereof. In some embodiments, the dopant of the bottom conductive layer 305 may include boron, aluminum, gallium, indium, antimony, arsenic, or phosphorus.

[0076] The intermediate conductive layer 303 of the bit line may be disposed on the bottom conductive layer 305 of the bit line. In some embodiments, the intermediate conductive layer 303 of the bit line may be formed, for example, of titanium silicon, nickel silicon, nickel-platinum silicon, tantalum silicon, or cobalt silicon. In some embodiments, the intermediate conductive layer 303 of the bit line may have a thickness between about 2 nm and about 20 nm.

[0077] The top conductive layer 301 of the bit line may be disposed on the middle conductive layer 303 of the bit line. In some embodiments, the top conductive layer 301 of the bit line may be formed, for example, from titanium, nickel, platinum, tantalum, cobalt, silver, copper, aluminum, other suitable conductive materials, or combinations thereof.

[0078] The bit line capping layer 307 may be disposed on the top conductive layer 301 of the bit line. In some embodiments, the bit line capping layer 307 may be formed, for example, from silicon nitride or other suitable insulating materials.

[0079] Referring to Figure 30, semiconductor element 1C may have a structure similar to that shown in Figure 28. Elements in Figure 30 that are the same as or similar to those in Figure 28 are labeled with similar reference numerals, and repeated descriptions are omitted.

[0080] In semiconductor device 1C, there is no word line barrier layer 203 as shown in FIG28. The word line conductive layer 205 can be directly disposed on the word line dielectric layer 201. In this embodiment, the word line conductive layer 205 can be formed of titanium nitride.

[0081] Figure 31 is a schematic cross-sectional view of a semiconductor element 1D according to another embodiment of the present disclosure along lines A-A', B-B', and C-C' in Figure 27. The semiconductor element 1D is similar to the intermediate semiconductor structure in Figure 28, except that the semiconductor element 1D includes a buried gate electrode 180 and impurity regions 105-1 / 105-3 in the active region AA.

[0082] It should be noted that the cross-sectional view of semiconductor element 1D along lines A-A' and C-C' is the same as the cross-sectional view of the intermediate semiconductor structure in Figure 27 along lines A-A' and C-C', and the repeated figures and descriptions are omitted.

[0083] Referring to Figure 31, in some embodiments, the buried gate electrode 180 may be disposed within a trench TR1 in the substrate 101. The active region AA includes a first impurity region 105-1 and a second impurity region 105-3. The first impurity region 105-1 and the second impurity region 105-3 are separated by the gate trench TR1.

[0084] As shown in Figure 31, a first gate material 140 is disposed on a portion TR1S-P of the sidewall TR1S of the gate trench TR1. The first gate material 140 includes a first component 140-1 and a second component 140-2 on the first component 140-1. The second component 140-2 is a protruding component extending from the first component 140-1 toward the top surface 101TS of the substrate 101. The first component 140-1 and the second component 140-2 have different diameters and different heights. In some embodiments, the second component 140-2 has a dome shape. In some embodiments, the first component 140-1 has a first width W31 and a first height H1, the first width W31 varying at different vertical height positions, and the second component 140-2 has a second width W32 and a second height H2, the second width W32 varying at different vertical height positions.

[0085] The first component 140-1 is surrounded by a first barrier layer 130. Furthermore, the first component 140-1 and the second component 140-2 are covered by a second barrier layer 150. Therefore, the first gate material 140 is completely surrounded by the first barrier layer 130 and the second barrier layer 150. In some embodiments, the first barrier layer 130 and the second barrier layer 150 are integrally formed. A second gate material 160 covering the first gate material 140 is provided in the middle portion of the gate trench TR1. The second barrier layer 150 is inserted between the second gate material 160 and the first gate material 140. A gate insulating material 170 covering the second gate material 160 is provided in the upper portion of the gate trench TR1.

[0086] In some embodiments, the first barrier layer 130 and the second barrier layer 150 comprise various materials, such as tantalum (Ta), titanium (Ti), tantalum nitride (TaN), titanium nitride (TiN), titanium silicon nitride (TiSiN), or other suitable materials. The gate insulating material 170 comprises silicon nitride (Si3N4) or other suitable materials. The first gate material 140 comprises various metals, such as aluminum (Al), copper (Cu), tungsten (W), titanium (Ti), or other suitable materials. The second gate material 160 comprises doped or undoped polycrystalline silicon. The first gate material 140 serves as a metallic gate electrode, and the second gate material 160 serves as a polycrystalline silicon gate electrode. In some embodiments, the first gate material 140 and the second gate material 160 together within the gate trench TR1 form the buried gate electrode 180 within the active region AA. In some embodiments, the buried gate electrode 180, the first barrier layer 130, the second barrier layer 150, and the gate insulating material 170 together form a buried gate structure.

[0087] In the buried gate electrode 180, the second component 140-2 of the first gate material 140 extends toward the second gate material 160. The buried gate electrode 180 (or buried gate structure), the first impurity region 105-1, and the second impurity region 105-3 together form the transistor of the dynamic random access memory (DRAM) element.

[0088] Figures 32 to 42 are schematic cross-sectional views along line B-B' in Figure 27, illustrating a part of the manufacturing process of a semiconductor device 1D according to another embodiment of the present disclosure. The corresponding steps are shown in step S11 of method 10 in Figure 1.

[0089] Referring to FIG32, a process for forming a gate trench is performed on a substrate 101 having an isolation layer 103. In some embodiments, the process for forming the gate trench is a process for forming a recess. First, referring to FIG32, a photoresist pattern 120 is formed on the substrate 101 to define the location of the recess. In some embodiments, the photoresist pattern 120 includes a plurality of openings exposing the top surface 101TS of the substrate 101. Specifically, the formation of the photoresist pattern 120 includes sequentially coating a photoresist layer on the active region AA and the isolation layer 103, exposing the photoresist layer to radiation using a photomask and lithography process, and developing the exposed photoresist layer.

[0090] Next, the active region AA is etched using the photoresist pattern 120 as an etching mask. The portion of the active region AA exposed by the opening is removed. Thus, a plurality of gate trenches TR1 are formed within the active region AA, and then the photoresist pattern 120 is removed using an ashing process or a wet stripping process. In some embodiments, the depth of the gate trenches TR1 is less than the depth of the isolation layer 103.

[0091] Referring to Figure 33, a first barrier layer 130a is formed on substrate 101. Specifically, the first barrier layer 130a is first deposited on the active region AA and the isolation layer 103, and the first barrier layer 130a is conformally formed within the gate trench TR1. Next, a CMP process is performed to remove a portion of the first barrier layer 130a on the top surface 101TS of substrate 101. As a result, the remaining portion of the first barrier layer 130a is lined within the inner sidewall of the gate trench TR1. In some embodiments, a CVD process is used to form the first barrier layer 130a. Preferably, an atomic layer deposition (ALD) process is used to form the first barrier layer 130a to allow for the formation of a highly conformal barrier layer with a more uniform thickness. In some embodiments, the first barrier layer 130a comprises various materials, such as tantalum (Ta), titanium (Ti), tantalum nitride (TaN), titanium nitride (TiN), titanium silicon nitride (TiSiN), or other suitable materials selected based on compatibility.

[0092] Furthermore, a first gate material 140a is formed on the substrate 101. Specifically, firstly, the first gate material 140a is deposited on the active region AA and the isolation layer 103 to completely fill the gate trench TR1. Next, a CMP process is performed to remove a portion of the first gate material 140a on the top surface 101TS of the substrate 101. As a result, the remaining portion of the first gate material 140a, surrounded by the first barrier layer 130a, completely fills the gate trench TR1 within the active region AA. In some embodiments, the formation of the first gate material 140a may utilize CVD, physical vapor deposition (PVD), or electroplating processes. In some embodiments, the first gate material 140a comprises various materials, such as aluminum (Al), copper (Cu), tungsten (W), titanium (Ti), or other suitable materials with a suitable work function. In some embodiments, before depositing the first gate material 140a on the first barrier layer 130a, a metal seed layer is conformally formed on the first barrier layer 130a to improve the adhesion between the first barrier layer 130a and the subsequently formed first gate material 140a. The material of the metal seed layer is selected based on the material selected for the first gate material 140a.

[0093] Referring to Figures 34 to 37, a recess is created within the gate trench TR1. In some embodiments, the first barrier layer 130a and the first gate material 140a are sequentially recessed and shaped into different profiles. First, referring to Figure 34, a first etching process is used to remove a portion of the first barrier layer 130a, leaving the remaining first barrier layer 130b. In some embodiments, the top surface S2 of the first barrier layer 130b is lower than the top surface 101TS of the substrate 101.

[0094] Next, referring to FIG. 35, a second etching process is used to remove a portion of the first gate material 140a, leaving the remaining first gate material 140b. In some embodiments, the second etching process uses an etchant different from that used in the first etching process. The second etching process is anisotropic etching, vertically removing approximately one-third of the height of the first gate material 140a. In some embodiments, after performing the second etching process, the top surface S3 of the first gate material 140b is substantially coplanar with the top surface S2 of the first barrier layer 130b.

[0095] Subsequently, referring to FIG36, a third etching process is used to remove a portion of the first barrier layer 130b, leaving the remaining first barrier layer 130. In some embodiments, the third etching process uses the same etchant as the first etching process. In some embodiments, after the third etching process is performed, the top surface S4 of the first barrier layer 130 is substantially lower than the top surface S3 of the first gate material 140b.

[0096] Next, referring to FIG. 37, a fourth etching process is used to remove a portion of the first gate material 140b, leaving the remaining first gate material 140. In some embodiments, the fourth etching process uses the same etchant as the third etching process. The fourth etching process primarily etches the sidewalls of the first gate material 140b at a height above the top surface S4, forming the upper arc portion of the first gate material 140b. Comparing FIG. 37 with FIG. 33, it can be seen that the first gate material 140a is etched to form a mound-shaped first gate material 140. Specifically, the first gate material 140 includes a first component 140-1 and a second component 140-2 located on the first component 140-1. The second component 140-2 extends from the first component 140-1 toward the top surface 101TS of the substrate 101. In some embodiments, the first component 140-1 has a semi-elliptical profile, and the second component 140-2 has a bell-shaped profile. In some embodiments, the first component 140-1 and the second component 140-2 have different dimensions. In some embodiments, the first component 140-1 has a first width W31 and a first height H1, the first width W31 varying at different vertical height positions. In some embodiments, the second component 140-2 has a second width W32 and a second height H2, the second width W32 varying at different vertical height positions. In some embodiments, the first component 140-1 has a generally flat top surface S5, and the top surface S5 is adjacent to and coplanar with the top surface S4 of the first barrier layer 130. In some embodiments, the second component 140-2 has a generally convex top surface S6, and the top surface S6 extends from and is surrounded by the top surface S5. The first component 140-1 is surrounded by the first barrier layer 130, while the second component 140-2 is not covered by any barrier layer.

[0097] Referring to Figure 38, a second barrier layer 150 is formed on the substrate 101. Specifically, the second barrier layer 150 covers the top surface S5 of the first component 140-1 and the top surface S6 of the second component 140-2. As a result, the first gate material 140 is completely surrounded by the first barrier layer 130 and the second barrier layer 150. In some embodiments, the second barrier layer 150 may contain the same material as the first barrier layer 130 and be formed by the same process steps as the first barrier layer 130.

[0098] Referring to Figure 39, a second gate material 160 is formed on substrate 101. Specifically, the second gate material 160 is deposited to completely cover the first gate material 140 and partially fill the gate trench TR1. In some embodiments, the top surface S7 of the second gate material 160 is substantially lower than the top surface 101TS of the substrate 101. In some embodiments, the second gate material 160 may comprise doped or undoped polycrystalline silicon formed using an LPCVD process. Preferably, the second gate material 160 is impurity-doped polycrystalline silicon to reduce the resistance of the second gate material 160. In some embodiments, the resistance of the first gate material 140 is lower than the resistance of the second gate material 160. In some embodiments, the work function of the first gate material 140 is higher than the work function of the second gate material 160. In some embodiments, the first gate material 140 is a metal gate electrode, and the second gate material 160 is a polycrystalline silicon gate electrode. The first gate material 140, serving as a metal gate electrode, and the second gate material 160, serving as a polysilicon gate electrode, can together form a buried dual gate electrode for the transistor of a DRAM device. In some embodiments, the buried gate electrode 180, comprising the first gate material 140 and the second gate material 160, is formed in a gate trench TR1 and operates as a transistor, wherein the buried gate electrode 180 has a dual work function. In the buried gate electrode 180, a second component 140-2 of the first gate material 140 extends toward the second gate material 160. A second barrier layer 150 is inserted between the second gate material 160 and the first gate material 140. The first barrier layer 130 and the second barrier layer 150 completely separate the first gate material 140 and the second gate material 160. Therefore, the formation of metal silicide between the first gate material 140 and the second gate material 160 can be avoided. In addition, the first barrier layer 130 and the second barrier layer 150 can prevent mutual ion diffusion between the buried gate electrode 180 and the impurity region.

[0099] Referring to Figure 40, a gate insulating material 170' is formed on the substrate 101. Specifically, the gate insulating material 170' is deposited to completely cover the second gate material 160 and partially fill the gate trench TR1. In some embodiments, the top surface S8 of the gate insulating material 170' is substantially coplanar with the top surface 101TS of the substrate 101. In some embodiments, a CVD process can be used to form the gate insulating material 170'. In some embodiments, the gate insulating material 170' comprises a dielectric material such as silicon nitride (Si3N4) or other suitable materials. The gate insulating material 170' protects the buried gate electrode 180 and prevents electrical short circuits.

[0100] Referring to Figure 41, a fifth etching process can be performed to remove a portion of the substrate 101 and a portion of the gate insulating material 170', while forming a plurality of first recesses 901 and gate insulating material 170. For ease of description, only one first recess 901 and one gate insulating material 170 are described. The first recess 901 may have two tapered sidewalls opposite to each other. The horizontal distance between the two tapered sidewalls may gradually decrease along the Z direction at a gradually decreasing height. In some embodiments, the fifth etching process may be an isotropic plasma dry etching process. In some embodiments, the fifth etching process may be a wet etching process. Furthermore, after performing the fifth etching process, the gate insulating material 170 may also have tapered sidewalls.

[0101] It should be noted that the selectivity of an etching process is generally expressed as a ratio of etching rates. For example, if the etching rate of one material is 25 times that of another material, the etching process can be described as having a selectivity of 25:1, or simply expressed as 25. In this respect, a higher ratio or value represents an etching process with higher selectivity.

[0102] Furthermore, a sixth etching process, such as anisotropic plasma dry etching, can be implemented to remove portions of the substrate 101 and form a plurality of second recesses 903. In some embodiments, in the sixth etching process, the etching rate of the substrate 101 may be greater than the etching rate of the gate insulating material 170'. The selectivity of the sixth etching process may be greater than or equal to about 10, greater than or equal to about 12, greater than or equal to about 15, greater than or equal to about 20, or greater than or equal to about 25.

[0103] For ease of description, only one second recess 903 is described. The second recess 903 may extend from the bottom surface of the first recess 901. In some embodiments, the bottom surface of the second recess 903 may be curved. In some embodiments, the bottom surface of the second recess 903 may be flat. In some embodiments, the second recess 903 may have a U-shaped cross-sectional profile. If the second recess 903 has a U-shaped cross-sectional profile, the corner effect can be avoided. The depth D1 of the first recess 901 may be equal to or less than one-quarter of the depth D2 of the second recess 903. In other words, the total depth D3 is equal to the sum of the depth D1 of the first recess 901 and the depth D2 of the second recess 903, and the depth D1 of the first recess 901 may be equal to or less than one-fifth of the total depth D3.

[0104] Referring to Figure 42, an epitaxial growth process can be implemented to fill a plurality of first recesses 901 and a plurality of second recesses 903, while simultaneously forming a plurality of impurity regions 105-1, 105-3. The epitaxial growth process can be chemical vapor deposition, atomic layer deposition, or molecular beam epitaxy. In some embodiments, the process temperature of the epitaxial growth process can be between about 700 °C and about 850 °C. The process pressure of the epitaxial growth process can be between about 5 Torr and about 50 Torr. In some embodiments, a planarization process such as chemical mechanical polishing can be optionally implemented to provide a generally flat surface for subsequent process steps. In some embodiments, a plurality of impurity regions 105-1, 105-3 protruding from the top surface 101TS of the substrate 101 can be formed.

[0105] The shape (or structure) of the plurality of impurity regions 105-1, 105-3 can be determined by the shape (or structure) of the plurality of first recesses 901 and the plurality of second recesses 903. Impurity region 105-1 can be located between two buried gate electrodes 180. Impurity region 105-3 can be respectively located on opposite sides of impurity region 105-1, and the two buried gate electrodes 180 are inserted between impurity regions 105-3. The plurality of impurity regions 105-1, 105-3 can include an upper portion 105U and a lower portion 105L. The upper portion 105U of the plurality of impurity regions 105-1, 105-3 can be located at the position previously occupied by the plurality of first recesses 901. The lower portion 105L can be located at the position previously occupied by the plurality of second recesses 903.

[0106] For ease of description, only an upper portion 105U and a lower portion 105L are described. The upper portion 105U may include two tapered sidewalls 105S. The horizontal distance between the two tapered sidewalls 105S (i.e., the width of the upper portion 105U) may gradually decrease along the Z direction at a position where the height gradually decreases. The upper portion 105U may have a tapered cross-sectional profile. The thickness T1 of the upper portion 105U (i.e., the vertical distance between the top surface 105TS of the upper portion 105U and the bottom surface of the upper portion 105U) may be equal to or less than one-quarter of the thickness T2 of the lower portion 105L (i.e., the vertical distance between the bottom surface 105BS of the lower portion 105L and the bottom surface of the upper portion 105U). In other words, the thickness T1 of the upper portion 105U can be equal to or less than one-fifth of the total thickness T3 of the impurity region 105-1 / 105-3 (i.e., the vertical distance between the top surface 105TS of the upper portion 105U and the bottom surface 105BS of the lower portion 105L). In some embodiments, the width W35 of the top surface 105TS of the impurity region 105-1 / 105-3 is greater than the width W36 of the bottom surface 105BS of the impurity region 105-1 / 105-3.

[0107] In some embodiments, the plurality of impurity regions 105-1 / 105-3 may be formed, for example, from silicon phosphide (SiP), phosphorus-doped silicon carbide (SiCP), silicon carbide (SiC), silicon-germanium (SiGe), silicon-germanium-tin alloy (SiGeSn), silicon-germanium-boron alloy (SiGeB), or other suitable semiconductor materials.

[0108] In some embodiments, the impurity region 105-1 / 105-3 is doped with a dopant such as phosphorus or boron. The dopant concentration in the impurity region 105-1 / 105-3 may be uniform. In some embodiments, the dopant concentration in the impurity region 105-1 / 105-3 may gradually increase at locations where the height gradually increases within the impurity region 105-1 / 105-3. In some embodiments, the dopant concentration in the upper portion 105U may be greater than the dopant concentration in the lower portion 105L. In some embodiments, the dopant concentration in the upper portion 105U gradually increases from the bottom to the top surface 105TS.

[0109] After forming the buried gate electrode 180 and impurity regions 105-1 and 105-3, the process described in steps S13 to S17 is continued to obtain the semiconductor device 1D in FIG31.

[0110] One aspect of this disclosure provides a semiconductor device. The semiconductor device includes a substrate having an active region; a gate structure disposed within a gate trench in the active region; a duplication region disposed adjacent to the gate structure; at least two bit line structures located on the substrate; a contact layer located on the substrate and between the at least two bit line structures; and a conductive neck layer located on the contact layer and between the at least two bit line structures. The duplication region has an upper portion and a lower portion, the upper portion defining a top surface of the duplication region, and the lower portion defining a bottom surface of the duplication region. The width of the top surface of the duplication region is greater than the width of the bottom surface of the duplication region.

[0111] Another aspect of this disclosure provides a semiconductor device. The semiconductor device includes a substrate having a first top surface; a first gate electrode and a second gate electrode disposed within the substrate, wherein the second gate electrode is located above the first gate electrode; a first barrier layer and a second barrier layer disposed within the substrate, wherein the second barrier layer is located on the first barrier layer and the first gate electrode; a gate cap layer disposed on the second gate electrode; at least two bit line structures located on the substrate; a contact layer located on the substrate and between the at least two bit line structures; and a conductive neck layer located on the contact layer and between the at least two bit line structures. The first gate electrode includes a first component and a second component, the first component being surrounded by the first barrier layer, the second component extending from the first component toward the first top surface, and the second component protruding from the first barrier layer. The second gate electrode is located on the second barrier layer and surrounds the second component of the second barrier layer and the first gate electrode. The width of the top surface of one of the conductive neck layers is greater than the width of the bottom surface of one of the conductive neck layers.

[0112] Another aspect of this disclosure provides a method for manufacturing a semiconductor device. The method includes providing a substrate having an isolation region defining an active region; forming a gate structure within the substrate; forming at least two bit line structures on the substrate; forming at least two separator layers on the substrate; forming a contact layer on the substrate; and forming a conductive neck layer on the contact layer. The width of a top surface of one of the conductive neck layers is greater than the width of a bottom surface of one of the conductive neck layers.

[0113] Another aspect of this disclosure provides a method for manufacturing a semiconductor device. The method includes providing a substrate having a first top surface, wherein the substrate includes an isolation region surrounding an active region; forming a gate structure within the active region of the substrate; forming a first recess and a second recess adjacent to the gate structure within the substrate; forming an impurity region within the first recess and the second recess; forming at least two bit line structures on the substrate; forming at least two separator layers on the substrate; forming a contact opening on the substrate; forming a contact layer on the substrate and within the contact opening; and forming a conductive neck layer on the contact layer. The contact opening is surrounded by the at least two separator layers and the at least two bit line structures. The impurity region has an upper portion and a lower portion, the upper portion defining a top surface of the impurity region, and the lower portion defining a bottom surface of the impurity region. The width of the top surface of the impurity region is greater than the width of the bottom surface of the impurity region.

[0114] Because of the semiconductor device design disclosed herein, by using a conductive neck layer 503 with a wider top surface 503TS, the overlap area between the conductive neck layer 503 and the landing pad 505 can be increased. As a result, defects and complexity associated with the manufacture of semiconductor devices 1A, 1B, 1C, and 1D can be reduced.

[0115] While this disclosure and its advantages have been detailed, it should be understood that various changes, substitutions, and alternatives can be made without departing from the spirit and scope of this disclosure as defined in the claims. For example, many of the processes described above can be implemented using different methods, and many of the processes described above can be replaced by other processes or combinations thereof.

[0116] Furthermore, the scope of this application is not limited to the specific embodiments of the processes, machinery, manufacturing, material composition, means, methods, and steps described in the specification. Those skilled in the art will understand from the disclosure herein that existing or future processes, machinery, manufacturing, material composition, means, methods, or steps that have the same function or achieve substantially the same results as the corresponding embodiments described herein can be used based on this disclosure. Therefore, such processes, machinery, manufacturing, material composition, means, methods, or steps are included within the scope of this application.

[0117] 1A: Semiconductor components 1B: Semiconductor components 1C: Semiconductor components 1D: Semiconductor Components 10: Method 101: Base 101TS: Top surface 103: Isolation layer 105: Impurity Zone 105-1: Source Region / Impurity Region 105-3: Drain Region / Impurity Region 105L: Lower Part 105U: Upper Part 105BS: Bottom 105S: Sidewall 105TS: Top surface 107: Bottom Dielectric Layer 109: Top Dielectric Layer 120: Photoresist pattern 130: First Barrier Layer 130a: First barrier layer 130b: First Barrier Layer 140: First gate material 140a: First gate material 140b: First gate material 140-1: First Component 140-2: Second Component 150: Second Barrier Layer 160: Second gate material 170: Gate insulation material 170': Gate insulation material 180: Embedded gate electrode 200: Character Line Structure 201: Character line dielectric layer 203: Character Line Barrier Layer 205: Character Line Conductive Layer 207: Character Line Cover Layer 300: Bitline Structure 300S: Side 301: Top conductive layer of bit line 303: Intermediate conductive layer of bit line 305: Base conductive layer of bit line 307: Bit line capping layer 307BS: Bottom surface 307TS: Top surface 309: Bitline contact 401: Inner spacer layer 401TS: Top surface 403: External spacer layer 403TS: Top surface 501: Contact Layer 503: Conductive neck layer 503BS: Bottom 503TS: Top surface 505: Landing mat 601: Separator Layer 601TS: Top surface 701: First masking layer 801: Sacrificial Layer 803: Separating material layer 805: First conductive material layer 807: Second conductive material layer 901: First Depression 903: Second Depression AA: Active Zone CP1: Arrow CP2: Arrow CP3: Arrow D1: Depth D2: Depth D3: Total Depth FS: First side H1: First Height H2: Second Altitude OP1: Separating opening OP2: Contact opening P1: Line pattern S11: Steps S13: Steps S15: Steps S17: Steps S2: Top surface S3: Top surface S4: Top surface S5: Top surface S6: Top surface S7: Top surface S8: Top surface SS: Second side T1: Thickness T2: Thickness T3: Total Thickness TR: Character line groove TR1: Trench TR1S: Sidewall TR1S-P: Partial W1: Width W2: Width W3: Width W31: First width W32: Second width W35: Width W36: Width W4: Width W5: Width X: Direction Y: direction Z: Direction

Claims

1. A semiconductor element, comprising: A single base has an active region; A gate structure is disposed in a gate trench within the active region; An impurity region is disposed adjacent to the gate structure; at least two bit line structures are located on the substrate; a contact layer is located on the substrate and between the at least two bit line structures; and a conductive neck layer is located on the contact layer and between the at least two bit line structures, wherein the impurity region has an upper portion and a lower portion, the upper portion defining a top surface of the impurity region, and the lower portion defining a bottom surface of the impurity region, wherein the width of the top surface of the impurity region is greater than the width of the bottom surface of the impurity region.

2. The semiconductor device as claimed in claim 1, wherein the gate structure comprises: A first barrier layer is disposed on a portion of one sidewall of the gate trench; a first gate material is disposed within the gate trench, wherein the first gate material includes a first component and a second component, the first component being surrounded by the first barrier layer, the second component extending from the first component toward a first top surface of the substrate, and the second component protruding from the first barrier layer; a second barrier layer is disposed on the first barrier layer and the first gate material; and a second gate material is disposed on the second barrier layer.

3. The semiconductor device as claimed in claim 1, wherein the at least two bit line structures extend along a first direction and are separated from each other in a top view, the conductive neck layer includes two first sides that contact the at least two bit line structures via an inner spacer layer and an outer spacer layer, respectively, and the two first sides taper toward the contact layer.

4. The semiconductor device as described in claim 3 further includes: At least two separator layers are located on the substrate, spaced apart from each other, and located between the at least two bit line structures, wherein the at least two separator layers and the at least two bit line structures together surround the contact layer and the conductive neck layer.

5. The semiconductor device as claimed in claim 4, wherein the conductive neck layer includes two second sides that contact the at least two separator layers and the two second sides are generally vertical.

6. The semiconductor device as described in claim 5 further includes: Multiple layers of internal spacers are conformally located on the sides of the at least two bit line structures.

7. The semiconductor device as described in claim 6 further includes: A plurality of outer spacer layers are conformally located on the plurality of inner spacer layers.

8. The semiconductor element as claimed in claim 1, wherein a width of a top surface of one of the conductive neck layers is greater than a width of a bottom surface of one of the conductive neck layers.

9. The semiconductor device as described in claim 5 further includes: A landing pad is located on the conductive neck layer.

10. The semiconductor element as claimed in claim 9, wherein the landing pad and the conductive neck layer partially overlap in the top view.

11. The semiconductor element as claimed in claim 10, wherein the conductive neck layer and the landing pad comprise the same material.

12. A semiconductor element, comprising: A base having a first top surface; A first gate electrode and a second gate electrode are disposed within the substrate, wherein the second gate electrode is located above the first gate electrode; a first barrier layer and a second barrier layer are disposed within the substrate, wherein the second barrier layer is located on the first barrier layer and the first gate electrode; a gate cap layer is disposed on the second gate electrode; at least two bit line structures are located on the substrate; a contact layer is located on the substrate and between the at least two bit line structures; and a conductive neck layer is located on the contact layer and between the at least two bit line structures, wherein the first gate electrode includes a first component and a second component, the first component being surrounded by the first barrier layer, the second component extending from the first component toward the first top surface and protruding from the first barrier layer, wherein the second gate electrode is located on the second barrier layer and surrounds the second barrier layer and the second component of the first gate electrode. The width of the top surface of one of the conductive neck layers is greater than the width of the bottom surface of one of the conductive neck layers.

13. The semiconductor device as claimed in claim 12, wherein the ratio of the width of the top surface of the conductive neck layer to the width of the bottom surface of the conductive neck layer is between about 2.0 and about 1.

3.

14. The semiconductor element as claimed in claim 12, wherein the first component has a first width and a first height, the first width varying at different vertical height positions, and the second component has a second width and a second height, the second width varying at different vertical height positions.

15. The semiconductor device as claimed in claim 12, wherein the first gate electrode is surrounded by the first barrier layer and the second barrier layer.

16. The semiconductor device as claimed in claim 12, wherein a top surface of the gate cap layer is substantially coplanar with the first top surface of the substrate.

17. The semiconductor device of claim 12, wherein the at least two bit line structures extend along a first direction and are separated from each other in a top view, the conductive neck layer includes two first sides that contact the at least two bit line structures via an inner spacer layer and an outer spacer layer, respectively, and the two first sides taper toward the contact layer.

18. The semiconductor device as described in claim 17 further comprises: At least two separator layers are located on the substrate, spaced apart from each other, and located between the at least two bit line structures, wherein the at least two separator layers and the at least two bit line structures together surround the contact layer and the conductive neck layer.

19. The semiconductor device as claimed in claim 18, wherein the conductive neck layer includes two second sides that contact the at least two separator layers and the two second sides are generally vertical.

20. The semiconductor device as described in claim 19, further comprising: A landing pad is located on the conductive neck layer.

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