Semiconductor device and method of manufacturing the same

Abstract

A method of manufacturing a semiconductor device includes forming a device isolation structure in a substrate to define an active region, wherein the active region includes edge regions and a central region located between the edge regions, and forming a well region in the active region, and forming a plurality of lightly-doped drain (LDD) regions first in the well region followed by forming a gate structure on the substrate and across the active region. Due to the LDD regions, an average doping concentration in the edge region below the gate structure is lower than an average doping concentration in the central region below the gate structure. Source / drain regions are formed in the LDD regions.

Description

Technical Field

[0001] This invention relates to a semiconductor manufacturing process, and more particularly to a semiconductor device and a method of manufacturing the same. Prior Technology

[0002] Current metal-oxide-semiconductor (MOS) devices have developed a gate-last process, using metal gates instead of polysilicon gates to solve electrical problems caused by gate size reduction.

[0003] However, the active region edge of a wide-edge device is prone to premature triggering, causing a double hump phenomenon in the subcritical region of the IV curve, which affects the properties of the semiconductor device. Summary of the Invention

[0004] This invention provides a semiconductor device and its manufacturing method, which can solve the double-peak problem and can be integrated into CMOS process.

[0005] A method for manufacturing a semiconductor device according to the present invention includes the following steps: Forming a device isolation structure within a substrate to define an active region, wherein the active region includes an edge region and a central region located between the edge regions. Forming a well region within the active region. First forming a plurality of lightly doped drain (LDD) regions within the well region, then forming a gate structure spanning the active region on the substrate, wherein the average doping concentration of the edge region of the active region below the gate structure is less than the average doping concentration of the central region below the gate structure due to the LDD regions. Forming a source / drain region within the LDD regions.

[0006] In one embodiment of the present invention, the method for forming the plurality of LDD regions includes forming a doped region having a first width in an edge region and forming a doped region having a second width in a central region, wherein the first width is smaller than the second width.

[0007] In one embodiment of the present invention, the method for forming the above-mentioned plurality of LDDs includes forming two rectangular doped regions within the well region, and performing a reverse doping process on the two rectangular doped regions within the edge region to reduce the average doping concentration of the edge region.

[0008] In one embodiment of the present invention, the method for forming the above-mentioned plurality of LDDs includes forming two rectangular doped regions in the well region, and performing another ion implantation process on the two rectangular doped regions in the central region to increase the average doping concentration in the central region.

[0009] In one embodiment of the present invention, the steps of forming the above-mentioned gate structure include sequentially forming a gate oxide layer, a high dielectric constant material layer, a barrier layer, a dummy gate layer and a hard mask layer on the surface of a substrate; patterning the hard mask layer; using the patterned hard mask layer as an etching mask to etch the dummy gate layer, the barrier layer, the high dielectric constant material layer and the gate oxide layer; and using a gate replacement process to replace the dummy gate layer with a metal gate.

[0010] In one embodiment of the present invention, the steps of forming the above-mentioned gate structure include sequentially forming a gate oxide layer, a gate layer and a hard mask layer on the surface of a substrate; patterning the hard mask layer; using the patterned hard mask layer as an etching mask to etch the gate layer and the gate oxide layer; and removing the hard mask layer.

[0011] In one embodiment of the present invention, the plurality of LDD regions are two asymmetric L-shaped doped regions.

[0012] A semiconductor device according to the present invention includes a substrate, a device isolation structure, a well region, a gate structure, a plurality of LDD regions, and a plurality of source / drain regions. The device isolation structure is formed on the substrate to define an active region, wherein the active region includes edge regions and a central region located between the edge regions. A well region is formed within the active region. A gate structure is formed on the surface of the substrate and spans the active region. A plurality of LDD regions are formed within the well region such that the average doping concentration of an edge region of the active region below the gate structure is less than the average doping concentration of the central region below the gate structure. Source / drain regions are formed within the plurality of LDD regions.

[0013] In another embodiment of the present invention, the LDD region includes a doped region having a first width in the edge region and a doped region having a second width in the central region, wherein the first width is smaller than the second width.

[0014] In another embodiment of the present invention, the gate structure includes an HKMG structure or a poly-SiON structure.

[0015] In various embodiments of the present invention, in a top view, the edge of the doped region having a first width may be aligned with the sidewall of the gate structure, the doped region having a first width may partially overlap with the gate structure, or the doped region having a first width may not overlap with the gate structure.

[0016] To make the above features of the present invention more apparent and understandable, specific embodiments are described below, and detailed descriptions are provided in conjunction with the accompanying drawings. Simple Explanation of the Diagram

[0017] Figures 1A to 1H are cross-sectional views of the manufacturing process of a semiconductor device according to a first embodiment of the present invention. Figure 2 is a top view of the structure in Figure 1A. Figure 3 is a cross-sectional view of line XX in Figure 2. Figure 4 is a top view of the semiconductor device in Figure 1H. Figure 5 is a cross-sectional view of line XX in Figure 4. Figure 6 is an IV curve diagram of a general semiconductor device and a semiconductor device of the first embodiment. Figures 7A to 7E are top views of various examples of the semiconductor device of the second embodiment. Implementation

[0018] The present invention can be understood by referring to the following detailed description and the accompanying drawings. Furthermore, the dimensions of the various regions in the drawings are for illustrative purposes only and are not intended to limit the scope of the invention.

[0019] Figures 1A to 1H are cross-sectional views of the manufacturing process of a semiconductor device according to a first embodiment of the present invention.

[0020] Referring to Figure 1A, a device isolation structure 102 is formed within the substrate 100 to define the active region AA. Then, a well region 104 is formed within the active region AA, and then multiple lightly doped drain (LDD) regions 106 are formed within the well region 104. The LDD regions 106 can be formed, for example, by first forming a patterned mask 108 on the surface 100s of the substrate 100, and then performing an ion implantation process 110.

[0021] Figure 2 is a top view of the structure of Figure 1A, wherein the active region AA includes edge regions 200 and a central region 202 located between the edge regions 200. In one embodiment, the sum of the length L1 of the upper edge region 200 and the length L2 of the lower edge region 200 accounts for approximately 5% to 40% of the total length L2 of the active region AA, for example, 5% to 30% or 5% to 20%.

[0022] Please refer to Figures 1A and 2 simultaneously. The method for forming the LDD region 106 is, for example, forming a doped region dp1 with a first width w1 in the edge region 200 and a doped region dp2 with a second width w2 in the central region 202, wherein the first width w1 is smaller than the second width w2.

[0023] Figure 3 is a cross-sectional view of line XX in Figure 2. Figure 3 shows the doped region dp1 with a first width w1 in the edge region 200, which is part of the LDD region 106 in Figure 2. Compared with the doped region dp2 with a second width w2 in Figure 1A, the average doping concentration of the edge region 200 is less than that of the central region 202 because the area occupied by the doped region dp1 is smaller. The "average doping concentration" in this text refers to the average doping concentration of all doped regions in the cross-section; taking the central region 202 in Figure 2 as an example, its cross-section is Figure 1A, and the area of ​​the doped region dp2 in Figure 1A is significantly larger than that of the doped region dp1 in Figure 3, so the average doping concentration of the central region 202 is greater than that of the edge region 200.

[0024] Referring to Figure 1B, after removing the patterned mask 108 of Figure 1A, a gate oxide layer 112, a high dielectric constant material layer 114, a barrier layer 116, a dummy gate layer 118, and a hard mask layer 120 are sequentially formed above the surface 100s of the substrate 100. The high dielectric constant material layer 114 may include a dielectric material with a high dielectric constant. For example, the dielectric material with a high dielectric constant may be a material with a dielectric constant greater than that of silicon oxide (approximately 3.9). In some embodiments, the high dielectric constant material layer 114 may be, for example, HfO₂, TiO₂, HfZrO, Ta₂O₃, HfSiO₄, ZrO₂, ZrSiO₂, LaO, AlO, ZrO, TiO, Ta₂O₅, Y₂O₃, BaZrO, HfZrO, HfLaO, HfSiO, LaSiO, AlSiO, HfTaO, HfTiO, Al₂O₃, Si₃N₄, SiON, or combinations thereof. The barrier layer 116 may include TiN or other suitable materials. The dummy gate layer 118 may include polysilicon. The hard mask layer 120 may include oxides, nitrides, or combinations thereof. Then, using lithography and etching processes, the hard mask layer 120 is patterned, exposing a portion of the dummy gate layer 118.

[0025] Referring to Figure 1C, a patterned hard mask layer 120 is used as an etching mask to etch the dummy gate layer 118, barrier layer 116, high dielectric constant material layer 114, and gate oxide layer 112 until the surface 100 of the substrate 100 is exposed. Subsequently, a gate replacement process can be used to replace the dummy gate layer 118 with a metal gate. For example, a spacer wall 122 can be formed on the sidewall s1. The spacer wall 122 may include silicon oxide, silicon nitride, or a combination thereof.

[0026] Referring to Figure 1D, a source / drain region 124 is formed in the LDD region 106 using an ion implantation process. Then, a metal silicate layer 126 can be formed on the exposed surface 100s of the substrate 100. Afterward, the hard mask layer 120 in Figure 1C is removed, along with a portion of the spacer wall 122, to obtain the spacer walls 122a located on both sides of the dummy gate layer 118.

[0027] Referring to Figure 1E, first deposit an etch stop layer 128 to cover the surface of the metal silicate layer 126, the spacer wall 122a and the dummy gate layer 118, and then form an ILD layer 130 to cover the etch stop layer 128 and the entire dummy gate layer 118.

[0028] Referring to Figure 1F, a planarization process such as CMP is performed on the ILD layer 130 and the etch stop layer 128 until the dummy gate layer 118 (in Figure 1E) below the etch stop layer 128 is exposed. Then, the dummy gate layer 118 is removed to obtain the opening 132. The opening 132 is a space formed by the spacer wall 122a and the barrier layer 116.

[0029] Referring to Figure 1G, a metal gate layer MG is formed above the substrate 100, and the metal gate layer MG fills the opening 132. The metal gate layer MG may include tantalum nitride (TaN), nickel silicon (NiSi), cobalt silicon (CoSi), molybdenum (Mo), copper (Cu), tungsten (W), aluminum (Al), cobalt (Co), zirconium (Zr), platinum (Pt), or other suitable materials.

[0030] Referring to Figure 1H, a planarization process, such as CMP, is performed on the metal gate layer MG to form the gate structure HKMG. The gate structure HKMG may include a gate oxide layer 112, a high dielectric constant material layer 114, a barrier layer 116, and the metal gate layer MG.

[0031] Besides the gate structure HKMG formed using a gate substitution process, this invention can also be used in processes where the gate structure is a poly-SiON structure. For example, in the steps of FIG1B, after forming the gate oxide layer 112, a polycrystalline silicon layer (not shown) is directly formed without forming the barrier layer 116 and the high dielectric constant material layer 114. Then, through the etching step of FIG1C, the poly-SiON structure can be formed. Subsequently, as in FIG1D, the source / drain region 124 is formed in the LDD region 106 to complete the semiconductor device of an embodiment of the present invention.

[0032] Figure 4 is a top view of the structure in Figure 1H, and for clarity, some components are omitted, such as the ILD layer 130, etch stop layer 128, spacer wall 122a, source / drain region 124, and metal silicide layer 126 in Figure 1H. Figure 5 is a cross-sectional view along line XX in Figure 4.

[0033] Please refer to Figures 4 and 5 simultaneously. The doped region dp1 with a first width w1 partially overlaps with the gate structure HKMG, and the average doping concentration of the edge region 200 below the gate structure HKMG is less than the average doping concentration of the central region 202 below the gate structure HKMG.

[0034] Figure 6 shows the IV curves of a general semiconductor device and the semiconductor device of the first embodiment. Referring to Figure 6, the IV curve of a general semiconductor device exhibits a double-hump phenomenon, while the semiconductor device of the first embodiment has a low average doping concentration at the edge of the active region, so the critical voltage (Vth) in this region is pulled up, resulting in an IV curve without double peaks, thereby avoiding premature turn-on at the edge region.

[0035] In order to make the average doping concentration of the edge region (active region) below the gate structure less than the average doping concentration of the central region (active region) below the gate structure, there are various technical means, as shown in Figures 7A to 7E.

[0036] In Figure 7A, the edge of the doped region dp1 with a first width w1' can be aligned with the sidewall s2 of the gate structure HKMG.

[0037] In Figure 7B, the doped region dp1 with a first width w1” can not overlap with the gate structure HKMG.

[0038] In Figure 7C, LDD region 106' consists of two asymmetric L-shaped doped regions. That is, the left LDD region 106' is not mirror-symmetric with the right LDD region 106'. In some embodiments, the area of ​​the left LDD region 106' is the same as the area of ​​the right LDD region 106'.

[0039] In addition, by controlling the manufacturing process, the average doping concentration of the edge region 700 below the gate structure HKMG can be made less than the average doping concentration of the central region 702 below the gate structure HKMG.

[0040] For example, the two rectangular doped regions 704 in Figure 7D are first formed in the well region 104 through an ion implantation process. The rectangular doped regions 704 cover the upper edge region 700, the lower edge region 700, and the central region 702. Next, the two rectangular doped regions 704 in the edge region 700 can be dedoped to form the dedoped region 706, thereby reducing the average doping concentration of the edge region 700.

[0041] In Figure 7E, two rectangular doped regions 704 are first formed in the well region 104 through an ion implantation process. Then, another ion implantation process is performed on the two rectangular doped regions 704 in the central region 702 to form a doped region 708, thereby increasing the average doping concentration of the central region 702.

[0042] Based on the above, the present invention adopts the method of forming the LDD region first and then forming the gate, so that the LDD region of a specific shape can be manufactured according to the requirements and the double peak phenomenon of semiconductor devices can be eliminated.

[0043] Although the present invention has been disclosed above by way of embodiments, it is not intended to limit the present invention. Anyone skilled in the art can make some modifications and refinements without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be determined by the appended claims.

[0044] 100: Base 100s: Surface 102: Component isolation structure 104: Well Area 106, 106': LDD area 108: Patterned Mirror 110: Ion Implantation Process 112: Gate oxide layer 114: High dielectric constant material layer 116: Barrier Layer 118: Virtual gate layer 120: Rigid Coverage Layer 122, 122a: Spacer wall 124: Source / Drain Region 126: Metal silicide layer 128: Etching Stop Layer 130: ILD layer 132: Opening 200, 700: Edge Zone 202, 702: Central District 704: Rectangular doped region 706: Undoped region AA: Active Zone dp1, dp2, 708: Doped regions HKMG: Gate Structure L1, L2: Length MG: Metal Gate Layer s1, s2: sidewalls w1, w1', w1”, w2: width

Claims

1. A method for manufacturing a semiconductor device, comprising: A device isolation structure is formed within a substrate to define an active region, wherein the active region includes an edge region and a central region located between the edge regions; a well region is formed within the active region; a plurality of lightly doped drain (LDD) regions are formed within the well region; a gate structure is formed on the substrate spanning the active region, and the average doping concentration of the edge region below the gate structure is less than the average doping concentration of the central region below the gate structure by means of the plurality of LDD regions, wherein the average doping concentration is the average of the doping concentrations of the plurality of LDD regions and the well region; and a source / drain region is formed within the plurality of LDD regions.

2. A method of manufacturing a semiconductor device as claimed in claim 1, wherein the method of forming the plurality of LDD regions includes forming a doped region having a first width in the edge region and forming a doped region having a second width in the central region, wherein the first width is smaller than the second width.

3. A method of manufacturing a semiconductor device as claimed in claim 2, wherein, in a top view, the edge of the doped region having the first width is aligned with the sidewall of the gate structure.

4. A method of manufacturing a semiconductor device as claimed in claim 2, wherein, in a top view, the doped region having the first width partially overlaps with the gate structure.

5. A method of manufacturing a semiconductor device as claimed in claim 2, wherein, in a top view, the doped region having the first width does not overlap with the gate structure.

6. A method of manufacturing a semiconductor device as claimed in claim 1, wherein, in a top view, the plurality of LDD regions are two asymmetric L-shaped doped regions.

7. A method for manufacturing a semiconductor device as claimed in claim 1, wherein the method for forming the plurality of LDD regions comprises: Two rectangular doped regions were formed within this well area; And perform a dedoping process on the two rectangular doped regions within the edge region to reduce the average doping concentration of the edge region.

8. A method for manufacturing a semiconductor device as claimed in claim 1, wherein the method for forming the plurality of LDD regions comprises: Two rectangular doped regions were formed within this well area; And another ion implantation process is performed on the two rectangular doped regions in the central region to increase the average doping concentration in the central region.

9. A method for manufacturing a semiconductor device as claimed in claim 1, wherein the step of forming the gate structure includes: A gate oxide layer, a high dielectric constant material layer, a barrier layer, a polysilicon layer, a dummy gate layer, and a hard mask layer are sequentially formed on the surface of the substrate; the hard mask layer is patterned; the patterned hard mask layer is used as an etching mask to etch the dummy gate layer, the barrier layer, the high dielectric constant material layer, and the gate oxide layer; and the dummy gate layer is replaced with a metal gate using a gate replacement process.

10. A method of manufacturing a semiconductor device as claimed in claim 1, wherein the step of forming the gate structure includes: A gate oxide layer, a gate layer, and a hard mask layer are sequentially formed on the surface of the substrate. Pattern the rigid mask layer; The patterned hard mask layer is used as an etching mask to etch the gate layer and the gate oxide layer; and the hard mask layer is removed.

11. A semiconductor device, comprising: Base; A device isolation structure is formed on the substrate to define an active region, wherein the active region includes an edge region and a central well region located between the edge regions, formed within the active region; a gate structure is formed on the surface of the substrate and spans the active region; a plurality of lightly doped drain (LDD) regions are formed within the well region such that the average doping concentration of the edge region below the gate structure is less than the average doping concentration of the central region below the gate structure, wherein the average doping concentration is the average of the doping concentrations of the plurality of LDD regions and the well region; and a source / drain region is formed within the plurality of LDD regions.

12. The semiconductor device of claim 11, wherein the plurality of LDD regions include a doped region having a first width in the edge region and a doped region having a second width in the central region, and the first width is smaller than the second width.

13. The semiconductor device of claim 12, wherein, in a top view, the edge of the doped region having the first width is aligned with the sidewall of the gate structure.

14. The semiconductor device of claim 12, wherein, in a top view, the doped region having the first width partially overlaps with the gate structure.

15. The semiconductor device of claim 12, wherein, in a top view, the doped region having the first width does not overlap with the gate structure.

16. The semiconductor device of claim 11, wherein the plurality of LDD regions are two asymmetric L-shaped doped regions.

17. The semiconductor device of claim 11, wherein the gate structure comprises an HKMG structure or a poly-SiON structure.

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