Semiconductor power device and manufacturing method thereof

Abstract

A semiconductor power device and a manufacturing method thereof are provided. The semiconductor power device includes a substrate, a buffer layer, a nitride channel layer, a source, a drain, a barrier layer, a first etching stop layer, a first passivation layer, a second etching stop layer, a second passivation layer, a gate structure, a spacer, and a field plate structure. The buffer layer is disposed on the substrate. The nitride channel layer is disposed on the buffer layer. The source and the drain are disposed on the nitride channel layer. The barrier layer is disposed on the nitride channel layer between the source and the drain. The first etching stop layer is disposed on the barrier layer, the source and the drain. The first passivation layer is disposed on the first etching stop layer. The second etching stop layer is disposed on the first passivation layer. The second passivation layer is disposed on the second etching stop layer. The gate structure is disposed in the second passivation layer, the second etching stop layer and the first passivation layer. The spacer is disposed between the gate structure and the second passivation layer and the second etching stop layer. The field plate structure is disposed in the second passivation layer. A two-dimensional electron gas is located in the nitride channel layer between the source and the drain, and is adjacent to an interface between the nitride channel layer and the barrier layer.

Description

[Technical Field]

[0001] This invention relates to a semiconductor element, and more particularly to a semiconductor power device. [Previous Technology]

[0002] In recent years, to meet the demands of high-frequency semiconductor devices, semiconductor power devices have evolved to include III-V group semiconductor power devices, such as GaN HEMT devices. Generally, in GaN HEMT devices, a two-dimensional electron gas (2DEG) is formed in the AlGaN layer below the interface due to spontaneous polarization and piezoelectric polarization effects at the interface between the AlGaN layer (which serves as a barrier layer) and the GaN layer (which serves as a channel layer). The high electron mobility of electrons, the high electron concentration of the 2DEG, and the low resistivity of GaN make III-V group semiconductor materials suitable for high-frequency applications. [Summary of the Invention]

[0003] The present invention provides a semiconductor power device and a method for manufacturing the same, wherein the semiconductor power device includes a power transistor and a field plate, and the gate structure of the power transistor and the field plate are formed in a stacked structure composed of multiple etch stop layers and multiple passivation layers.

[0004] The semiconductor power device of the present invention includes a substrate, a buffer layer, a nitride channel layer, a source, a drain, a barrier layer, a first etch stop layer, a first passivation layer, a second etch stop layer, a second passivation layer, a gate structure, a spacer, and a field plate structure. The buffer layer is disposed on the substrate. The nitride channel layer is disposed on the buffer layer. The source and the drain are disposed on the nitride channel layer. The barrier layer is disposed on the nitride channel layer between the source and the drain. The first etch stop layer is disposed on the barrier layer, the source, and the drain. The first passivation layer is disposed on the first etch stop layer. The second etch stop layer is disposed on the first passivation layer. The second passivation layer is disposed on the second etch stop layer. The gate structure is disposed in the second passivation layer, the second etch stop layer, and the first passivation layer. The spacer is disposed between the gate structure, the second passivation layer, and the second etch stop layer. The field plate structure is disposed in the second passivation layer. The two-dimensional electron gas is located in the nitride channel layer between the source and the drain, and is adjacent to the interface between the nitride channel layer and the barrier layer.

[0005] In one embodiment of the semiconductor power device of the present invention, the thickness of the second etch stop layer is greater than the thickness of the first etch stop layer.

[0006] In one embodiment of the semiconductor power element of the present invention, the gate structure further extends through the barrier layer.

[0007] In one embodiment of the semiconductor power element of the present invention, the two-dimensional electron gas does not exist below the gate structure.

[0008] In one embodiment of the semiconductor power element of the present invention, the field plate structure further extends through the second etch stop layer.

[0009] In one embodiment of the semiconductor power device of the present invention, a third etch stop layer is further included. The third etch stop layer is disposed on the second passivation layer, wherein the gate structure and the field plate structure further extend through the third etch stop layer.

[0010] In one embodiment of the semiconductor power device of the present invention, the thickness of the third etch stop layer is greater than the thickness of the second etch stop layer.

[0011] In one embodiment of the semiconductor power device of the present invention, the bottom of the field plate structure is located on the second etch stop layer.

[0012] In one embodiment of the semiconductor power device of the present invention, the gate structure includes a first conductive layer, a dielectric layer, and a second conductive layer. The dielectric layer is disposed on the sidewall and bottom surface of the first conductive layer. The second conductive layer is disposed between the first conductive layer and the dielectric layer.

[0013] In one embodiment of the semiconductor power device of the present invention, the field plate structure includes a first conductive layer, a dielectric layer, and a second conductive layer. The dielectric layer is disposed on the sidewall and bottom surface of the first conductive layer. The second conductive layer is disposed between the first conductive layer and the dielectric layer.

[0014] In one embodiment of the semiconductor power element of the present invention, the width of the top of the gate structure is greater than the width of the bottom of the gate structure.

[0015] The method for manufacturing a semiconductor power device according to the present invention includes the following steps. In one embodiment of the method for manufacturing a semiconductor power device according to the present invention, a buffer layer is formed on a substrate. A nitride channel layer is formed on the buffer layer. A source and a drain are formed on the nitride channel layer. A barrier layer is formed on the nitride channel layer between the source and the drain. A first etch stop layer is formed on the barrier layer, the source, and the drain. A first passivation layer is formed on the first etch stop layer. A second etch stop layer is formed on the first passivation layer. A second passivation layer is formed on the second etch stop layer. A gate structure is formed in the second passivation layer, the second etch stop layer, and the first passivation layer. A spacer is formed between the gate structure, the second passivation layer, and the second etch stop layer. A field plate structure is formed in the second passivation layer. A two-dimensional electron gas is located in the nitride channel layer between the source and the drain, and adjacent to the interface between the nitride channel layer and the barrier layer.

[0016] In one embodiment of the method for manufacturing a semiconductor power device according to the present invention, the gate structure includes a first conductive layer, a dielectric layer, and a second conductive layer. The dielectric layer is disposed on the sidewall and bottom surface of the first conductive layer. The second conductive layer is disposed between the first conductive layer and the dielectric layer.

[0017] In one embodiment of the method for manufacturing a semiconductor power device according to the present invention, the field plate structure includes a first conductive layer, a dielectric layer, and a second conductive layer. The dielectric layer is disposed on the sidewall and bottom surface of the first conductive layer. The second conductive layer is disposed between the first conductive layer and the dielectric layer.

[0018] In one embodiment of the semiconductor power device manufacturing method of the present invention, the method for forming the gate structure, the spacer wall, and the field plate structure includes the following steps. In one embodiment of the semiconductor power device manufacturing method of the present invention, after forming the second passivation layer, a third etch stop layer is formed on the second passivation layer. A first etch process is performed to form a first trench in the third etch stop layer, the second passivation layer, and the second etch stop layer. The spacer wall is formed on the sidewall of the first trench. A second etch process is performed to form a second trench in the third etch stop layer. A third etch process is performed to extend the first trench downward through the first passivation layer and to extend the second trench downward through the second passivation layer, wherein the first trench exposes the first etch stop layer, and the second trench exposes the second etch stop layer. The dielectric layer, the second conductive layer, and the first conductive layer are sequentially formed in the first trench and the second trench.

[0019] In one embodiment of the method for manufacturing a semiconductor power device of the present invention, after the third etching process and before the dielectric layer is formed, the method further includes removing the third etch stop layer, the first etch stop layer exposed by the first trench, and the second etch stop layer exposed by the second trench.

[0020] In one embodiment of the method for manufacturing a semiconductor power device of the present invention, the thickness of the third etch stop layer is greater than the thickness of the second etch stop layer, and the thickness of the second etch stop layer is greater than the thickness of the first etch stop layer.

[0021] In one embodiment of the method for manufacturing a semiconductor power device of the present invention, the method for forming the first conductive layer includes performing a chemical vapor deposition process.

[0022] In one embodiment of the method for manufacturing a semiconductor power device of the present invention, the method for forming the second conductive layer includes performing an atomic layer deposition process.

[0023] In one embodiment of the method for manufacturing a semiconductor power element of the present invention, the width of the top of the gate structure is greater than the width of the bottom of the gate structure.

[0024] Based on the above, in the semiconductor power device and its manufacturing method of the present invention, by forming an etch stop layer, first trenches and second trenches with different depths can be formed in the same etch process. Furthermore, by forming a spacer wall in the first trench, the width of the region used to accommodate the gate structure of the power transistor in the semiconductor power device is reduced, thus facilitating the formation of a gate structure with a smaller width. Additionally, the gate structure and the field plate structure can be made of the same material and can be formed in the same process step.

Implementation Method

[0025] The following description provides detailed examples in conjunction with the accompanying drawings, but these examples are not intended to limit the scope of the invention. Furthermore, the drawings are for illustrative purposes only and are not drawn to their original dimensions. For ease of understanding, the same elements will be designated with the same symbols in the following description.

[0026] The terms “include”, “including”, “have” and so on used in the text are all open-ended terms, which means “includes but is not limited to”.

[0027] When using terms such as "first" and "second" to describe elements, it is only for distinguishing these elements from each other and does not limit the order or importance of these elements. Therefore, in some cases, a first element may also be called a second element, and a second element may also be called a first element, and this does not depart from the scope of the present invention.

[0028] Furthermore, directional terms mentioned in the text, such as "up" and "down," are only used to refer to the direction of the drawings and are not intended to limit the present invention. Therefore, it should be understood that "up" and "down" can be used interchangeably, and when an element such as a layer or film is placed "up" of another element, the element can be placed directly on the other element, or there may be an intermediate element. On the other hand, when an element is said to be placed "directly" on another element, there is no intermediate element between the two.

[0029] Furthermore, in this document, the range expressed as "from one value to another" is a concise way of representing the range to avoid listing all the values ​​in the range one by one in the specification. Therefore, the description of a particular value range covers any value within the value range, as well as the smaller value range defined by any value within the value range.

[0030] Figures 1A to 1G are schematic cross-sectional views of the manufacturing process of a semiconductor power device according to the first embodiment of the present invention.

[0031] The semiconductor power element in various embodiments of the present invention includes a power transistor and a field plate electrically connected to the power transistor, and the process of fabricating the field plate structure including the field plate can be integrated with the process of fabricating the gate structure of the power transistor.

[0032] Furthermore, the semiconductor power devices of various embodiments of the present invention include multiple etch stop layers, so that additional photomasks and protective materials are not required to form trenches with different depths for accommodating gate structures and trenches for accommodating field plate structures during the manufacturing process of semiconductor power devices.

[0033] Furthermore, in the manufacturing process of the semiconductor power device according to various embodiments of the present invention, a gap wall is formed on the sidewall of the trench accommodating the gate structure. Therefore, the gate structure formed in the trench can have a smaller width, so that the semiconductor power device according to various embodiments of the present invention can be applied at low operating voltages (e.g., 5 V to 12 V).

[0034] In the following embodiments, a high-electron-mobility transistor (HEMT) is used as an example of a power transistor for description, but the present invention is not limited thereto. The semiconductor power device and its manufacturing method according to embodiments of the present invention will be described in detail below.

[0035] Figures 1A to 1G are schematic cross-sectional views of the manufacturing process of a semiconductor power device according to the first embodiment of the present invention.

[0036] First, referring to FIG1A, a substrate 100 is provided. The substrate 100 is, for example, a silicon (Si) substrate, a silicon carbide (SiC) substrate, a gallium nitride (GaN) substrate, or a sapphire substrate. Next, a buffer layer 101 is formed on the substrate 100. The material of the buffer layer 101 is, for example, AlGaN. The buffer layer 101 may have a superlattice structure. The thickness of the buffer layer 101 is, for example, between 0.5 μm and 6 μm. Furthermore, in other embodiments, a nucleation layer may be formed on the substrate 100 before forming the buffer layer 101. The material of the nucleation layer is, for example, AlN, GaN, or AlGaN. The thickness of the nucleation layer is, for example, between 5 nm and 50 nm.

[0037] After forming the buffer layer 101, a nitride channel layer 102 is formed on the buffer layer 101. The material of the nitride channel layer 102 is, for example, GaN or InGaN. The thickness of the nitride channel layer 102 is, for example, between 0.2 μm and 0.8 μm. Then, a barrier layer 104 is formed on the nitride channel layer 102. The material of the barrier layer 104 is, for example, AlGaN, InAlN, InAlGaN, or AlN. The thickness of the barrier layer 104 is, for example, between 5 nm and 35 nm. After forming the barrier layer 104, a two-dimensional electron gas 2DEG is formed in the nitride channel layer 102, and the two-dimensional electron gas 2DEG is adjacent to the interface between the nitride channel layer 102 and the barrier layer 104.

[0038] After forming the barrier layer 104, a source S and a drain D are formed in the barrier layer 104 and the nitride channel layer 102. The material of the source S and the drain D is, for example, silicon-doped GaN or silicon-doped InGaN, wherein the silicon concentration is, for example, between 10 × 10¹⁹ cm⁻³ and 10 × 10²¹ cm⁻³.

[0039] In this embodiment, the method for forming the source S and drain D may include the following steps. First, grooves corresponding to the positions of the source and drain of the power transistor in the semiconductor power device are formed in the barrier layer 104 and the nitride channel layer 102. The bottom of the grooves is located in the nitride channel layer 102. Then, an epitaxially growing process is performed to form the source S and drain D in the grooves. In this embodiment, the top surface of the source S and the top surface of the drain D are coplanar with the plane of the barrier layer 106, but the present invention is not limited thereto.

[0040] In this embodiment, since the source S and drain D are formed in the barrier layer 104 and the nitride channel layer 102, the two-dimensional electron gas 2DEG will be located between the source S and drain D, and will be continuous between the source S and drain D.

[0041] Next, referring to FIG1B, a first etch stop layer ESL1, a first passivation layer 106, a second etch stop layer ESL2, a second passivation layer 108 and a third etch stop layer ESL3 are sequentially formed on the barrier layer 104, the source S and the drain D.

[0042] In this embodiment, the thickness of the third etch stop layer ESL3 is greater than the thickness of the second etch stop layer ESL2, and the thickness of the second etch stop layer ESL2 is greater than the thickness of the first etch stop layer ESL1. The material of the first etch stop layer ESL1 is, for example, AlN or Al2O3. The thickness of the first etch stop layer ESL1 is, for example, between 1 nm and 2 nm. The material of the first passivation layer 106 is, for example, AlN, Al2O3, SiO2, or SiN. The thickness of the first passivation layer 106 is, for example, between 0.05 nm and 30 nm. The material of the second etch stop layer ESL2 is, for example, AlN or Al2O3. The thickness of the second etch stop layer ESL2 is, for example, between 2 nm and 10 nm. The material of the second passivation layer 108 is, for example, AlN, Al2O3, SiO2, or SiN. The thickness of the second passivation layer 108 is, for example, between 0.05 nm and 30 nm. The material of the third etch stop layer ESL3 is, for example, AlN or Al2O3. The thickness of the third etch stop layer ESL3 is, for example, between 5 nm and 20 nm.

[0043] Then, referring to FIG1C, a first trench TR1 is formed in the third etch stop layer ESL3, the second passivation layer 108, and the second etch stop layer ESL2. The first trench TR1 corresponds to the location of the gate structure of the power transistor in the semiconductor power device. The method for forming the first trench TR1 may include the following steps. First, a patterned photoresist layer is formed on the third etch stop layer ESL3. The patterned photoresist layer exposes the location corresponding to the gate structure of the power transistor in the semiconductor power device. Then, an etching process is performed to remove a portion of the third etch stop layer ESL3, a portion of the second passivation layer 108, and a portion of the second etch stop layer ESL2 until the first passivation layer 106 is exposed. Afterward, the patterned photoresist layer is removed.

[0044] After forming the first trench TR1, a spacer wall SP is formed on the sidewall of the first trench TR1. The material of the spacer wall SP is, for example, SiN, SiO2, or SiON. The thickness of the spacer wall SP is, for example, between 0.5 nm and 30 nm. The method for forming the spacer wall SP may include the following steps. First, a spacer wall material layer is conformally formed on the substrate 100. Then, an anisotropic etching process is performed to remove a portion of the spacer wall material layer until the top surface of the third etch stop layer ESL3 and the first passivation layer 106 are exposed.

[0045] Based on the characteristics of the anisotropic etching process, the upper sidewall of the gap wall SP can be a convex surface, and the middle and lower sidewalls of the gap wall SP can be planes that are substantially perpendicular to the substrate 100. Therefore, the width of the upper gap wall SP will be smaller than the width of the middle and lower gap wall SP.

[0046] In this embodiment, by forming a gap wall SP in the first trench TR1, the width of the region used to accommodate the gate structure of the power transistor in the semiconductor power element is reduced, and thus it is advantageous to form a gate structure with a smaller width.

[0047] Next, referring to FIG1D, a patterned mask layer 109 is formed on the third etch stop layer ESL3. The patterned mask layer 109 is located on the third etch stop layer ESL3 and fills the first trench TR1. Furthermore, the patterned mask layer 109 exposes the positions corresponding to the field plate structures of the power transistors in the semiconductor power device. In this embodiment, the material of the patterned mask layer 109 is photoresist, but the present invention is not limited thereto.

[0048] After the patterned mask layer 109 is formed, an anisotropic etching process is performed using the patterned mask layer 109 as an etch mask to remove part of the third etch stop layer ESL3 and form a second trench TR2 in the third etch stop layer ESL3. The second trench TR2 exposes the second passivation layer 108.

[0049] Next, referring to FIG1E, the patterned mask layer 109 is removed. Then, an anisotropic etching process is performed using the third etch stop layer ESL3 and the spacer SP as the etch mask. In the anisotropic etching process, the first passivation layer 106, the first etch stop layer ESL1, and the barrier layer 104 below the first trench TR1 are removed, causing the first trench TR1 to extend downward through the first passivation layer 106, the first etch stop layer ESL1, and the barrier layer 104 to expose the nitride channel layer 102. Furthermore, in the anisotropic etching process, the second passivation layer 108 below the second trench TR2 is also removed simultaneously, causing the second trench TR2 to extend downward through the second passivation layer 108 to expose the second etch stop layer ESL2.

[0050] In this embodiment, since the thickness of the third etch stop layer ESL3 is greater than the thickness of the second etch stop layer ESL2, and the thickness of the second etch stop layer ESL2 is greater than the thickness of the first etch stop layer ESL1, the third etch stop layer ESL3 and the second etch stop layer ESL2 below the second trench TR1 will not be completely removed during the aforementioned anisotropic etching process. In other words, in this embodiment, by adjusting the thickness of the first etch stop layer ESL1, the thickness of the second etch stop layer ESL2, and the thickness of the third etch stop layer ESL3, first trench TR1 and second trench TR2 with different depths can be formed in the same etching process. Furthermore, during the aforementioned anisotropic etching process, the upper part of the spacer wall SP may also be slightly removed.

[0051] Furthermore, in the steps described in FIG1E, the first trench TR1 extends downward to expose the nitride channel layer 102, so there is no two-dimensional electron gas 2DEG directly below the first trench TR1.

[0052] Next, referring to FIG1F, the third etch stop layer ESL3 on the second passivation layer 108 and the second etch stop layer ESL2 exposed by the second trench TR2 are removed. The method for removing the third etch stop layer ESL3 and the second etch stop layer ESL2 is, for example, a wet etching process. In addition, in this embodiment, during the process of removing the third etch stop layer ESL3 and the second etch stop layer ESL2 by a wet etching process, the upper part of the spacer wall SP may also be slightly removed.

[0053] Next, referring to FIG1G, a gate structure GS is formed in the first trench TR1, and a field plate structure FPS is formed in the second trench TR2. In this embodiment, the method for forming the gate structure GS and the field plate structure FPS may include the following steps. First, a dielectric layer 110 with a high dielectric constant is conformally formed on the substrate 100. In this art, a high dielectric constant generally refers to a dielectric constant greater than 4. In this embodiment, the material of the dielectric layer 110 is, for example, HfO, Al2O3, or AlN. The thickness of the dielectric layer 110 is, for example, between 0.05 nm and 30 nm. Next, a conductive layer M1 is conformally formed on the dielectric layer 110. The material of the conductive layer M1 is, for example, TiN, Ni, Ti, AlCu, Al, or AlSi. The thickness of the conductive layer M1 is, for example, between 0.05 nm and 30 nm. The method for forming the conductive layer M1 is, for example, performing an atomic layer deposition process. Then, a conductive layer M2 is formed on the conductive layer M1 to fill the first trench TR1 and the second trench TR2. The material of the conductive layer M2 is, for example, W or Cu. The conductive layer M2 is formed by, for example, a chemical vapor deposition process. Afterward, the dielectric layer 110, conductive layer M1, and conductive layer M2, excluding the first trench TR1 and the second trench TR2, are removed. The method for removing the dielectric layer 110, conductive layer M1, and conductive layer M2, excluding the first trench TR1 and the second trench TR2, is, for example, a chemical mechanical polishing (CMP) process or an etching-back process.

[0054] After removing the dielectric layer 110, conductive layer M1, and conductive layer M2 outside the first trench TR1 and the second trench TR2, the dielectric layer 110, conductive layer M1, and conductive layer M2 in the first trench TR1 constitute the gate structure GS, while the dielectric layer 110, conductive layer M1, and conductive layer M2 in the second trench TR2 constitute the field plate structure FPS. That is, in this embodiment, the gate structure GS and the field plate structure FPS can be made of the same material and can be formed in the same process step.

[0055] In the gate structure GS, the dielectric layer 110 serves as the gate dielectric layer, while the conductive layers M1 and M2 together serve as the gate. In the field plate structure FPS, the conductive layers M1 and M2 together serve as the field plate. In this way, the semiconductor power device 10 of this embodiment, including the power transistor and the field plate structure, is formed.

[0056] In the semiconductor power device 10, a buffer layer 101 and a nitride channel layer 102 are sequentially disposed on a substrate 100, a source electrode S and a drain electrode D are disposed on the nitride channel layer 102, and a barrier layer 104 is disposed on the nitride channel layer 102 between the source electrode S and the drain electrode D. In addition, a first etch stop layer ESL1, a first passivation layer 106, a second etch stop layer ESL2 and a second passivation layer 108 are sequentially disposed on the barrier layer 104, the source electrode S and the drain electrode D.

[0057] The gate structure GS is disposed in the second passivation layer 108, the second etch stop layer ESL2, the first passivation layer 106, the first etch stop layer ESL1, and the barrier layer 104, such that the two-dimensional electron gas 2DEG is located in the nitride channel layer 102 between the source electrode S and the drain electrode D, adjacent to the interface between the nitride channel layer 102 and the barrier layer 104, and is not located below the gate structure GS. Therefore, the power transistor in the semiconductor power device 10 is an enhancement-mode (E-mode) power transistor.

[0058] The spacer wall SP is disposed between the gate structure GS, the second passivation layer 108, and the second etch stop layer ESL2. In this embodiment, since the upper width of the spacer wall SP is smaller than the middle and lower widths of the spacer wall SP, the top width of the gate structure GS is greater than the bottom width of the gate structure GS.

[0059] The field plate structure FPS is disposed on the second passivation layer 108 and the second etch stop layer ESL2, and can be electrically connected to the gate structure GS through conductive elements formed in subsequent processes.

[0060] Figure 2 is a schematic cross-sectional view of a semiconductor power element according to a second embodiment of the present invention. In this embodiment, elements identical to those in the first embodiment will be indicated by the same reference numerals and will not be described further.

[0061] Refer to Figure 2. The difference between the semiconductor power device 20 of this embodiment and the semiconductor power device 10 of the first embodiment is that in the semiconductor power device 20, the field plate structure FPS is formed in the third etch stop layer ESL3, the second passivation layer 108 and the second etch stop layer ESL2, and the bottom of the field plate structure FPS is located in the second etch stop layer ESL2.

[0062] In detail, after performing the steps described in Figures 1A to 1E, the steps described in Figure 1F are not performed, so as to retain the third etch stop layer ESL3 on the second passivation layer 108 and the second etch stop layer ESL2 below the second trench TR2. In this way, the process steps of the semiconductor power device 20 can be further simplified.

[0063] Figure 3 is a schematic cross-sectional view of a semiconductor power element according to a third embodiment of the present invention. In this embodiment, elements identical to those in the first embodiment will be indicated by the same reference numerals and will not be described further.

[0064] Referring to Figure 3, the difference between the semiconductor power element 30 of this embodiment and the semiconductor power element 10 of the first embodiment is that: in the semiconductor power element 30, the gate structure GS is formed in the second passivation layer 108, the second etch stop layer ESL2, the first passivation layer 106, and the first etch stop layer ESL1, and does not extend downward into the barrier layer 104. Since there is a barrier layer 104 between the gate structure GS and the nitride channel layer 102, the two-dimensional electron gas 2DEG is continuous between the source S and the drain D. Therefore, the power transistor in the semiconductor power element 30 is a depletion-type (D-mode) power transistor. In addition, the field plate structure FPS is formed in the second passivation layer 108 and the second etch stop layer ESL2, and the bottom of the field plate structure FPS is located on the first passivation layer 106.

[0065] In detail, after performing the steps described in Figures 1A to 1D, in the step described in Figure 1E, the first trench TR1 extends downward only through the first passivation layer 106 to expose the first etch stop layer ESL1, and the second trench TR2 extends downward through the second passivation layer 108 to expose the second etch stop layer ESL2. Furthermore, in the step described in Figure 1F, in addition to removing the third etch stop layer ESL3 on the second passivation layer 108 and the second etch stop layer ESL2 exposed by the second trench TR2, the first etch stop layer ESL1 exposed by the first trench TR1 is also removed.

[0066] Figure 4 is a schematic cross-sectional view of a semiconductor power element according to a fourth embodiment of the present invention. In this embodiment, elements identical to those in the first embodiment will be indicated by the same reference numerals and will not be described further.

[0067] Referring to Figure 4, the difference between the semiconductor power element 40 of this embodiment and the semiconductor power element 10 of the first embodiment is that: in the semiconductor power element 40, the gate structure GS is formed in the third etch stop layer ESL3, the second passivation layer 108, the second etch stop layer ESL2, and the first passivation layer 106, and does not extend downward to the first etch stop layer ESL1 and the barrier layer 104. Since there is a barrier layer 104 between the gate structure GS and the nitride channel layer 102, the two-dimensional electron gas 2DEG is continuous between the source S and the drain D. Therefore, the power transistor in the semiconductor power element 40 is a depletion-type power transistor. In addition, the field plate structure FPS is formed in the third etch stop layer ESL3 and the second passivation layer 108, and the bottom of the field plate structure FPS is located on the second etch stop layer ESL2.

[0068] In detail, after performing the steps described in Figures 1A to 1D, in the step described in Figure 1E, the first trench TR1 extends downward only through the first passivation layer 106 to expose the first etch stop layer ESL1, and the second trench TR2 extends downward through the second passivation layer 108 to expose the second etch stop layer ESL2. Furthermore, after the step described in Figure 1E, the step described in Figure 1F is not performed, so that a third etch stop layer ESL3 is retained on the second passivation layer 108, the first etch stop layer ESL1 is retained below the first trench TR1, and the second etch stop layer ESL2 is retained below the second trench TR2.

[0069] In the above embodiments, after the semiconductor power device is formed, subsequent well-known processes can be performed. For example, after the semiconductor power device is formed, contact windows that form ohmic contacts with the source S and drain D, contact windows that are electrically connected to the gate structure GS, and contact windows that are electrically connected to the field plate structure FPS can be formed.

[0070] Although the present invention has been disclosed above by way of embodiments, it is not intended to limit the present invention. Anyone skilled in the art can make some modifications and refinements without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be determined by the appended claims. [Simplified Explanation of the Diagram]

[0071] Figures 1A to 1G are schematic cross-sectional views of the manufacturing process of a semiconductor power device according to the first embodiment of the present invention. Figure 2 is a schematic cross-sectional view of a semiconductor power device according to the second embodiment of the present invention. Figure 3 is a schematic cross-sectional view of a semiconductor power device according to the third embodiment of the present invention. Figure 4 is a schematic cross-sectional view of a semiconductor power device according to the fourth embodiment of the present invention.

Claims

1. A semiconductor power device, comprising: Base; A buffer layer is disposed on the substrate; A nitride channel layer is disposed on the buffer layer; A source and a drain are disposed on the nitride channel layer; a barrier layer is disposed on the nitride channel layer between the source and the drain; a first etch stop layer is disposed on the barrier layer, the source, and the drain; a first passivation layer is disposed on the first etch stop layer; A second etch stop layer is disposed on the first passivation layer; a second passivation layer is disposed on the second etch stop layer; a gate structure is disposed in the second passivation layer, the second etch stop layer and the first passivation layer; A spacer wall is disposed between the gate structure and the second passivation layer and the second etch stop layer; and a field plate structure is disposed in the second passivation layer, wherein the two-dimensional electron gas is located in the nitride channel layer between the source and the drain, and adjacent to the interface between the nitride channel layer and the barrier layer.

2. The semiconductor power device as claimed in claim 1, wherein the thickness of the second etch stop layer is greater than the thickness of the first etch stop layer.

3. The semiconductor power device as claimed in claim 1, wherein the gate structure further extends through the barrier layer.

4. The semiconductor power device as claimed in claim 3, wherein the two-dimensional electron gas is not present below the gate structure.

5. The semiconductor power device as claimed in claim 1, wherein the field plate structure further extends through the second etch stop layer.

6. The semiconductor power device of claim 1 further includes a third etch stop layer disposed on the second passivation layer, wherein the gate structure and the field plate structure further extend through the third etch stop layer.

7. The semiconductor power device as claimed in claim 6, wherein the thickness of the third etch stop layer is greater than the thickness of the second etch stop layer.

8. The semiconductor power device as claimed in claim 6, wherein the bottom of the field plate structure is located on the second etch stop layer.

9. The semiconductor power device as claimed in claim 1, wherein the gate structure comprises: First conductive layer; A dielectric layer is disposed on the sidewall and bottom surface of the first conductive layer; And a second conductive layer, disposed between the first conductive layer and the dielectric layer.

10. The semiconductor power device as claimed in claim 9, wherein the field plate structure comprises: The first conductive layer; The dielectric layer is disposed on the sidewall and bottom surface of the first conductive layer; And a second conductive layer, disposed between the first conductive layer and the gate dielectric layer.

11. The semiconductor power device as claimed in claim 1, wherein the width of the top of the gate structure is greater than the width of the bottom of the gate structure.

12. A method for manufacturing a semiconductor power device, comprising: A buffer layer is formed on the substrate; A nitride channel layer is formed on the buffer layer; A source and a drain are formed on the nitride channel layer; A barrier layer is formed on the nitride channel layer between the source and the drain; a first etch stop layer is formed on the barrier layer, the source, and the drain; a first passivation layer is formed on the first etch stop layer; a second etch stop layer is formed on the first passivation layer; a second passivation layer is formed on the second etch stop layer; a gate structure is formed in the second passivation layer, the second etch stop layer, and the first passivation layer; a spacer is formed between the gate structure, the second passivation layer, and the second etch stop layer; and a field plate structure is formed in the second passivation layer, wherein a two-dimensional electron gas is located in the nitride channel layer between the source and the drain, and adjacent to the interface between the nitride channel layer and the barrier layer.

13. A method of manufacturing a semiconductor power device as claimed in claim 12, wherein the gate structure comprises: First conductive layer; A dielectric layer is formed on the sidewalls and bottom surface of the first conductive layer; A second conductive layer is formed between the first conductive layer and the dielectric layer.

14. A method for manufacturing a semiconductor power device as claimed in claim 13, wherein the field plate structure comprises: The first conductive layer; The dielectric layer is formed on the sidewall and bottom surface of the first conductive layer; And a second conductive layer is formed between the first conductive layer and the gate dielectric layer.

15. A method for manufacturing a semiconductor power device as claimed in claim 14, wherein the method for forming the gate structure, the spacer wall, and the field plate structure comprises: After the second passivation layer is formed, a third etch stop layer is formed on the second passivation layer; A first etching process is performed to form a first trench in the third etch stop layer, the second passivation layer, and the second etch stop layer; the gap wall is formed on the sidewall of the first trench; a second etching process is performed to form a second trench in the third etch stop layer; A third etching process is performed to extend the first trench downward through the first passivation layer and to extend the second trench downward through the second passivation layer, wherein the first trench exposes the first etch stop layer and the second trench exposes the second etch stop layer; and the dielectric layer, the second conductive layer and the first conductive layer are sequentially formed in the first trench and the second trench.

16. The method of manufacturing a semiconductor power device as claimed in claim 15, further comprising, after performing the third etch process and before forming the dielectric layer, removing the third etch stop layer, the first etch stop layer exposed by the first trench, and the second etch stop layer exposed by the second trench.

17. A method of manufacturing a semiconductor power device as claimed in claim 14, wherein the thickness of the third etch stop layer is greater than the thickness of the second etch stop layer, and the thickness of the second etch stop layer is greater than the thickness of the first etch stop layer.

18. A method for manufacturing a semiconductor power device as claimed in claim 13, wherein the method for forming the first conductive layer includes performing a chemical vapor deposition process.

19. A method for manufacturing a semiconductor power device as claimed in claim 13, wherein the method for forming the second conductive layer includes performing an atomic layer deposition process.

20. A method of manufacturing a semiconductor power element as claimed in claim 12, wherein the width of the top of the gate structure is greater than the width of the bottom of the gate structure.

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