Semiconductor structure

Abstract

A semiconductor structure is provided. The semiconductor structure includes a substrate, an epitaxy layer, an isolation doping region, a first device, a second device, and a buried layer. The epitaxy layer includes a first epitaxial material layer and a second epitaxial material layer disposed on the substrate. The first epitaxial material layer and the second epitaxial material layer have different conductivity type. The isolation doping region extends from the top surface of the second epitaxial material layer to the top surface of the first epitaxial material layer and separates a first area and a second area of the semiconductor structure. The first device and the second device are disposed respectively in the first area and the second area. The buried layer is disposed in the first area and under the first device.

Description

[Technical Field]

[0001] This invention relates to semiconductor structures, and more particularly to semiconductor structures that integrate multiple different types of elements on the same substrate. [Previous Technology]

[0002] The semiconductor industry continues to improve the integration density of various electronic components by continuously reducing the minimum component size, allowing more components to be integrated within a given area. It is also attempting to integrate different types of semiconductor components on the same substrate. However, as the requirements for the electrical performance of semiconductor components continue to increase, the complexity of integrating semiconductor components also increases.

[0003] Taking laterally diffused metal-oxide-semiconductor (LDMOS) devices as an example, they can meet the requirements of high output power and drain-source breakdown voltage greater than 60 volts, and are mainly used in power amplifiers, power management ICs, and battery management ICs. The drive current of LDMOS devices is in the planar direction. Vertical metal-oxide-semiconductor (VDMOS) devices, on the other hand, have the characteristics of high voltage resistance and low on-resistance, and are widely used in power switch devices. The drive current of VDMOS devices flows vertically. Currently, integrating LDMOS and VDMOS devices with different drive current directions on a substrate not only increases the complexity of the fabrication method, but also makes the electrical performance of each device susceptible to the influence of other different types of devices, thus failing to meet application requirements. Therefore, integrating LDMOS and VDMOS devices is not as simple as individual devices; due to its relative difficulty and complexity, it presents a considerable challenge in integration and fabrication. [Summary of the Invention]

[0004] A semiconductor structure is provided. This semiconductor structure includes a substrate, an epitaxial layer, an isolation doped region, a first element, a second element, and a buried layer. The epitaxial layer includes a first epitaxial material layer and a second epitaxial material layer disposed on the substrate. The isolation doped region extends from the top surface of the second epitaxial material layer to the top surface of the first epitaxial material layer, and separates a first region and a second region of the semiconductor structure. The first element and the second element are respectively disposed in the first region and the second region. The buried layer is disposed in the first region and below the first element. The first epitaxial material layer, the isolation doped region, and the buried layer have a first conductivity type. The second epitaxial material layer has a second conductivity type different from the first conductivity type.

[0005] A semiconductor structure is provided. This semiconductor structure includes a substrate, an epitaxial layer, an isolation doped region, a first element, a second element, and c buried layers. The epitaxial layer includes a first epitaxial material layers and b second epitaxial material layers disposed on the substrate, where a is a positive integer greater than or equal to 1, and b is a positive integer greater than or equal to 1. The isolation doped region extends from the top surface of the a second epitaxial material layers to the top surface of the b first epitaxial material layers, and separates a first region and a second region of the semiconductor structure. The first element and the second element are respectively disposed in the first region and the second region. The c buried layers are disposed in the first region and below the first element, where c is a positive integer greater than or equal to 1. The a first epitaxial material layers, the isolation doped region, and the c buried layers have a first conductivity type. The b second epitaxial material layers have a second conductivity type different from the first conductivity type. The sum of a and b is greater than c, and the difference between the sum of a and b and c is 1.

Implementation Method

[0006] The following disclosure provides numerous embodiments or examples for implementing different elements of the provided semiconductor device. Specific examples of each element and its configuration are described below to simplify the description of embodiments of the invention. Of course, these are merely examples and are not intended to limit the embodiments of the invention. For example, if the description refers to a first element formed on a second element, it may include embodiments where the first and second elements are in direct contact, or embodiments where an additional element is formed between the first and second elements such that they are not in direct contact. Furthermore, the embodiments of the invention may repeat reference numerals and / or letters in different examples. Such repetition is for brevity and clarity and is not intended to indicate a relationship between the different embodiments discussed.

[0007] Furthermore, spatially related terms such as "below," "under," "below," "above," "above," and other similar expressions may be used in the following description to simplify the statement of the relationship between an element or component and other elements or components as shown in the figure. These spatially related terms include not only the direction depicted in the figure but also the different orientations of the device during use or operation. The device may be positioned in other directions (rotated 90 degrees or in other orientations), and the spatially related descriptions used herein may be interpreted accordingly.

[0008] Some variations of the embodiments are described below. In embodiments with different drawings and descriptions, similar element symbols are used to identify similar elements. It is understood that additional steps may be provided before, during, or after the method, and some described steps may be replaced or deleted for other embodiments of the method.

[0009] This disclosure provides a semiconductor structure comprising various types of metal-oxide-semiconductor (MOS) devices. Furthermore, by appropriately configuring epitaxial layers of different conductivity types according to the requirements of the application, each MOS device can exhibit excellent electrical performance. That is, embodiments of the present invention can integrate different types of MOS devices on the same substrate (e.g., a wafer) in a simple process and without incurring high manufacturing costs, while increasing the breakdown voltage.

[0010] This disclosure provides a semiconductor structure in which epitaxial material layers of different conductivity types are incorporated, allowing the integration of multiple semiconductor devices of different types on the same substrate (e.g., a wafer), particularly multiple semiconductor devices with different drive current directions. The semiconductor devices constructed using the epitaxial material layers of different conductivity types in the embodiments exhibit excellent electrical performance. Furthermore, the multilayer epitaxial material layers in the embodiments facilitate the construction of buried layers and / or isolation layers beneath the semiconductor devices, reducing the on-resistance of the semiconductor devices. Therefore, the semiconductor structure of this invention can integrate different types of semiconductor devices on the same substrate in a simple process without incurring high manufacturing costs, while increasing the breakdown voltage.

[0011] The application of the embodiments includes integrating multiple semiconductor devices with different current directions during operation on a substrate. Semiconductor devices are, for example, metal-oxide-semiconductor (MOS) devices, including complementary MOS (CMOS), lateral-diffused LDMOS, double-diffused MOS (DMOS), vertical-diffused MOS (VDMOS), or other MOS devices. For example, BCD (including bipolar, CMOS, and DMOS devices) and VDMOS devices. Vertically current-directed VDMOS devices and horizontally current-directed bipolar transistors, LDMOS devices, CMOS devices, or other semiconductor devices can be integrated on the same substrate. However, this disclosure is not limited to the above-described devices.

[0012] Figure 1 is a schematic cross-sectional view of semiconductor structure 1 according to some embodiments of the present disclosure.

[0013] According to the embodiment of Figure 1, multiple semiconductor devices of different types can be integrated on a substrate 100. By using epitaxial material layers with different conductivity types, current paths for semiconductor devices with horizontal operating currents can be provided, while simultaneously providing drift regions (high-voltage well regions) for semiconductor devices with vertical operating currents. In this way, a higher voltage platform can be provided without the need for additional embedding depth.

[0014] According to the embodiment of Figure 1, at least one semiconductor element with a vertical current direction and at least one semiconductor element with a horizontal current direction are integrated on the substrate 100. This embodiment of the invention is illustrated by integrating one semiconductor element with a vertical current direction and three semiconductor elements with horizontal current directions. Those skilled in the art can adjust the number and arrangement of the semiconductor elements as needed.

[0015] According to the embodiment of Figure 1, for example, a first element 11, a second element 12, a third element 13, and a fourth element 14 are respectively disposed in a first region A1, a second region A2, a third region A3, and a fourth region A4 to form a semiconductor structure 1. The first element 11, the second element 12, the third element 13, and the fourth element 14 are laterally separated (e.g., in the first direction D1). The first region A1, the second region A2, the third region A3, and the fourth region A4 will be separated from each other by subsequently formed isolation doped regions, as detailed below.

[0016] According to the embodiment in Figure 1, the first element 11 is a vertical metal-oxide-semiconductor device, such as a VDMOS device, wherein a split trench gate (SGT) structure is used as the gate structure 11G of the VDMOS device for related description. However, this disclosure is not limited thereto; in some other embodiments, the first element 11 may also include a general trench gate structure. The second element 12, the third element 13, and the fourth element 14 are non-vertical metal-oxide-semiconductor devices, such as CMOS devices, LDPMOS devices, and LDNMOS devices, respectively. However, the semiconductor devices that can be integrated in this disclosure are not limited to the above types.

[0017] According to the embodiment of Figure 1, the substrate 100 extends in a first direction D1 and a second direction D2, and has a thickness in a third direction D3. The substrate 100 is, for example, a silicon wafer doped with a first conductivity type. Subsequently, an epitaxial layer, appropriate plurality of well regions and plurality of heavily doped regions, gate structures, insulating layers, and contacts, and other related components will be formed on the substrate 100 to form the first element 11, the second element 12, the third element 13, and the fourth element 14.

[0018] In applications where a vertical metal-oxide-semiconductor device (MOSS) element is used as the first element 11, a substrate 100 having a first conductivity type can serve as the drain region of the first element 11, allowing the drive current to flow in the vertical direction (e.g., the third direction D3). In the embodiment of Figure 1, the first conductivity type is n-type, but this disclosure is not limited thereto. In some other embodiments, the first conductivity type can also be p-type, which is the opposite conductivity type. In some embodiments, the substrate 100 has a doping concentration of 1E18 to 1E22 cm⁻³.

[0019] According to the embodiment of Figure 1, a backplate metal layer 700 is formed below the substrate 100 (third direction D3) to contact the bottom surface of the substrate 100. The backplate metal layer 700 can serve as a drain terminal of the first element 11.

[0020] In other embodiments, a drain structure is formed to serve as the drain region of the first element 11, instead of forming a backplane metal layer 700 (see the description in Figure 8 below).

[0021] According to the embodiment of Figure 1, an epitaxial layer 200 is formed on the substrate 100 (third direction D3). The epitaxial layer 200 and the back metal layer 700 are formed on opposite sides of the substrate 100.

[0022] In some embodiments, the epitaxial layer 200 is a multilayer structure comprising at least one first epitaxial material layer 210 and at least one second epitaxial material layer 220, wherein the first epitaxial material layer 210 and the second epitaxial material layer 220 have different conductivity types. In some embodiments, the first epitaxial material layer 210 has the same first conductivity type as the substrate 100 (e.g., n-type), and the second epitaxial material layer 220 has a second conductivity type different from the substrate 100 (e.g., p-type). In the embodiment of Figure 1, the first conductivity type is n-type and the second conductivity type is p-type, but this disclosure is not limited thereto.

[0023] In detail, the epitaxial layer 200 includes a first epitaxial material layer 210 and b second epitaxial material layers 220, where a is a positive integer greater than or equal to 1, and b is a positive integer greater than or equal to 1. In the embodiment of Figure 1, a is 1 (a=1) and b is 1 (b=1).

[0024] In other embodiments, either a or b may be 1, or neither may be 1. For example, in the embodiment of Figure 4, a is 2 (a=2) and b is 1 (b=1); in the embodiment of Figure 5, a is 1 (a=1) and b is 2 (b=2); in the embodiment of Figure 6, a is 1 (a=1) and b is 3 (b=3); in the embodiment of Figure 7, a is 2 (a=2) and b is 2 (b=2).

[0025] In some embodiments, the doping concentration of the substrate 100 is greater than the doping concentration of the first epitaxial layer 210. In some embodiments, the first epitaxial layer 210 has a doping concentration of a first conductivity type (e.g., n-type) of 1E14~5E17 cm-3, and the second epitaxial layer 220 has a doping concentration of a second conductivity type (e.g., p-type) of 1E14~5E16 cm-3.

[0026] In some embodiments, the thicknesses of the first epitaxial material layer 210 and the second epitaxial material layer 220 may be the same or different. In some embodiments, the first epitaxial material layer 210 may be 1~12µm or 2~9µm, and the thickness of the second epitaxial material layer 220 may be 1~12µm or 2~9µm.

[0027] Generally speaking, the epitaxial layer 200 with a multilayer structure can adjust the voltage it carries. The thicker the epitaxial layer 200, the higher its voltage carrying capacity, but its on-resistance is also higher. Therefore, in this embodiment of the invention, a buried layer 300 is also provided in the epitaxial layer 200 to reduce the on-resistance.

[0028] According to the embodiment of Figure 1, a buried layer 300 is formed in the epitaxial layer 200. In some embodiments, the buried layer 300 is disposed in a first region A1 and below the first element 11 (third direction D3) to reduce the on-resistance of the first element 11. In some embodiments, the buried layer 300 has the same first conductivity type (e.g., n-type) as the substrate 100 and / or the first epitaxial material 210. In the embodiment of Figure 1, the first conductivity type is n-type, but this disclosure is not limited thereto.

[0029] In some embodiments, the semiconductor structure 1 includes c buried layers 300, where c is a positive integer and greater than or equal to 1. In embodiments of the present invention, the number (c) of buried layers 300 can be determined based on the number (a) of the first epitaxial material layer 210 and the number (b) of the second epitaxial material layer 220 in the epitaxial layer 200. In some embodiments, the sum of a and b is greater than c ((a+b)>c), and the difference between the sum of a and b and c is 1 ((a+b)-c=1). In the embodiment of Figure 1, the sum of a and b is 2 (a=1 and b=1), and c is 1 (c=1).

[0030] In other embodiments, c may not be 1. For example, in the embodiment of Figure 4, the sum of a and b is 3 (a=2 and b=1), and c is 2 (c=2); in the embodiment of Figure 5, the sum of a and b is 3 (a=1 and b=2), and c is 2 (c=2); in the embodiment of Figure 6, the sum of a and b is 4 (a=1 and b=3), and c is 3 (c=3); in the embodiment of Figure 7, the sum of a and b is 4 (a=2 and b=2), and c is 3 (c=3).

[0031] In some embodiments, the doping concentration of the buried layer 300 is greater than the doping concentration of the first epitaxial layer 210. In some embodiments, the buried layer 300 has a doping concentration of a first conductivity type (e.g., n-type) of 1E16~5E19cm-3.

[0032] In some embodiments, a buried layer 300 is formed after the formation of the first epitaxial material layer 210, and a second epitaxial material layer 220 is formed after the formation of the buried layer 300. Specifically, after epitaxial growth of the first epitaxial material layer 210, a predetermined dopant is implanted within a predetermined area of ​​the first epitaxial material layer 210 to form a buried material. Next, the second epitaxial material layer 220 is epitaxially grown and annealed, causing the buried material to diffuse from the first epitaxial material layer 210 into the second epitaxial material layer 220, thus forming the buried layer 300 as shown in Figure 1. That is, the buried layer 300 vertically spans the boundary between the first epitaxial material layer 210 and the second epitaxial material layer 220, and is simultaneously disposed in both the first epitaxial material layer 210 and the second epitaxial material layer 220. That is, the buried layer 300 extends from the first epitaxial material layer 210 into the second epitaxial material layer 220 in the third direction D3. In this way, it can be ensured that there is no concentration depression region between the buried layer 300 and the first high-pressure well region 1121 of the subsequently formed first element 11.

[0033] In addition, compared with directly setting the buried layer in the single-layer epitaxial layer, the embodiments of the present invention use a multi-layer epitaxial layer, which can set the buried layer in a deeper position by performing a placement process on different layers of epitaxial material, which is more conducive to reducing the on-resistance.

[0034] Next, semiconductor elements are formed at predetermined locations. According to the embodiment of Figure 1, a plurality of VDMOS elements are disposed in the first region A1 as first elements 11. Figure 1 uses a separated trench gate (SGT) structure as the gate structure 11G of the VDMOS elements, but this disclosure is not limited thereto.

[0035] The components of the first element 11 in the first region A1 of Figure 1 will be described in detail below.

[0036] According to the embodiment of Figure 1, a high-voltage well region 112 is formed on the buried layer 300. The high-voltage well region 112 in the first region A1 is a first high-voltage well region 1121 having a first conductivity type. The first high-voltage well region 1121 is disposed in the second epitaxial material layer 220. In the embodiment of Figure 1, the first conductivity type is n-type, and the first high-voltage well region 1121 is a deep high voltage n-well (DHVNW), but this disclosure is not limited thereto. In some embodiments, the doping concentration of the first high-voltage well region 1121 is greater than the doping concentration of the first epitaxial material layer 210 to further improve the electrical performance of a device 11. In some embodiments, the first high-voltage well region 1121 has a doping concentration of a first conductivity type (e.g., n-type) of 1E15~1E18 cm⁻³.

[0037] In some embodiments, a first high-pressure well region 1121 may be formed by implanting a dopant with a first conductivity type (e.g., an n-type dopant) in the second epitaxial material layer 220 through an ion implantation process.

[0038] According to the embodiment of Figure 1, a gate structure 11G and a terminal structure 11T are formed in the high-pressure well region 112 (first high-pressure well region 1121). In some embodiments, the first region A1 includes a central region A1c and a surrounding region A1p surrounding the central region A1c. In the embodiment of Figure 1, the surrounding region A1p is disposed on both sides of the central region A1c. The gate structure 11G is disposed in the central region A1c, and the terminal structure 11T is disposed in the surrounding region A1p. In the embodiment of Figure 1, the gate structure 11G and the terminal structure 11T are separated from the buried layer 300 by the first high-pressure well region 1121. That is, the gate structure 11G and the terminal structure 11T do not contact the top surface of the buried layer 300.

[0039] In some embodiments, the gate structure 11G includes a gate 11GE and a liner 11GL. The gate 11GE includes a bottom gate 1142 and a top gate 1146. The liner 11GL includes an insulating layer 1141, a dielectric layer 1143, and an insulating portion 1145. The insulating portion 1145 separates the bottom gate 1142 and the top gate 1146, and the insulating layer 1141 and the dielectric layer 1143 isolate the gate 11GE from the high-pressure well region 112. The bottom electrode 1142 can be used as a source or as a gate.

[0040] In some embodiments, the gate structure 11G is formed at a predetermined location by a lithography process and a patterning process (lithography process and etching process) and a deposition process. For example, a mask is first formed on the epitaxial layer 200, and a groove (not shown) is formed in the epitaxial layer 200 (e.g., in the second epitaxial material layer 220) by means of the mask. Next, an insulating layer 1141 and a bottom electrode 1142 are formed in the bottom of the groove, and then a dielectric layer 1143 and an insulating portion 1145 are formed. Next, a top gate 1146 is formed to form the gate structure 114 (11G).

[0041] In some embodiments, the mask may be a patterned photoresist formed of a photoresist material. In some other embodiments, the mask material may also be a rigid mask (HM) composed of an oxide layer and a nitride layer.

[0042] In some examples where patterned photoresist is used as a mask, the above-mentioned lithography and patterning processes include photoresist coating (e.g., spin coating), soft baking, mask alignment, exposure, post-exposure baking, photoresist development, cleaning and drying (e.g., hard baking), other suitable processes, or combinations of the foregoing processes, to form multiple openings (not shown) in the mask.

[0043] After the above-mentioned mask is formed, one or more etching processes are performed through the opening of the mask to remove a portion of the second epitaxial material layer 220, thereby forming a groove in the second epitaxial material layer 220. The above-mentioned etching processes include, for example, dry etching processes, wet etching processes, plasma etching processes, reactive ion etching processes, other suitable processes, or combinations of the foregoing processes.

[0044] It should be noted that the groove is located corresponding to the opening of the shield and is below the opening. Therefore, the formed groove is, for example, a successor to the opening and communicates with it. In some embodiments, the depth of the groove in the second epitaxial material layer 220 (e.g., along the third direction D3) is less than the depth in the high-pressure well region 112 (e.g., along the third direction D3). The size, shape, and position of the opening and groove of the shield depend on the size, shape, and position of the gate structure 11G to be formed in the actual application, and are not limited herein.

[0045] After the aforementioned grooves are formed in the second epitaxial layer 220, the mask can be removed by an ashing process, a wet etching process (e.g., acid etching), or other acceptable processes. After removing the mask, a cleaning process can be selectively performed to remove residues.

[0046] Subsequently, a shielding insulating layer is formed on the sidewall of the groove. The shielding insulating layer is, for example, silicon oxide, germanium oxide, other suitable semiconductor oxide materials, or a combination of the aforementioned materials. Furthermore, the shielding insulating layer can be compliantly formed on the sidewall and bottom surface of the groove, as well as on the top surface of the second epitaxial layer 220, by an oxidation process. The oxidation process can be thermal oxidation, radical oxidation, or other suitable processes.

[0047] In some embodiments, a thermal process, such as a rapid thermal annealing (RTA) process, may be selectively applied to the shielding insulation layer to increase the density of the shielding insulation layer.

[0048] A bottom electrode 1142 is formed on the aforementioned shielding insulating layer (in the lower part of the groove). The bottom electrode 1142 may be a single-layer or multi-layer structure, and is formed, for example, from amorphous silicon, polycrystalline silicon, other suitable conductive materials, or a combination of the aforementioned materials.

[0049] Specifically, an electrode material (not shown) can be deposited on a shielding insulating layer by a deposition process, and the electrode material fills the space in the groove outside the shielding insulating layer. Then, an excess portion of the electrode material is removed by a removal process, and the portion of the electrode material in the groove is etched back to make the electrode material recessed to a predetermined depth to form the bottom electrode 1142 as shown in Figure 1.

[0050] The above deposition process may be a physical vapor deposition (PVD) process, a chemical vapor deposition (CVD) process, other suitable processes, or a combination of the foregoing processes. In some embodiments, the electrode material may be selectively subjected to a thermal process, such as an annealing process.

[0051] The above-mentioned removal process may include a planarization process. The above-mentioned planarization process may include a chemical mechanical polishing (CMP) process, a mechanical polishing process, an etching process, other suitable processes, or a combination of the foregoing processes.

[0052] In some embodiments, the bottom electrode 1142 may optionally contain a dopant of a first conductivity type (e.g., an n-type dopant). In some examples, the dopant of the bottom electrode 1142 may be phosphorus (P) or other suitable dopant. In addition to reducing gate-drain capacitance (Cgd) to improve the switching characteristics of the semiconductor device, the bottom electrode 1142 of the separated trench gate structure can further enhance the effect of reducing the surface electric field (RESURF).

[0053] After the bottom electrode 1142 is formed, the upper portion of the masking insulating layer can be removed by an etching process. The remaining portion of the masking insulating layer forms the insulating layer 1141 located on the sidewall and bottom surface of the lower part of the groove. The etching process described above is, for example, a dry etching process, a wet etching process, a plasma etching process, a reactive ion etching process, other suitable processes, or a combination thereof. Furthermore, the top surface of the insulating layer 1141 may be higher or lower than the top surface of the bottom electrode 1142, or substantially coplanar with the top surface of the bottom electrode 1142, and has a slight dishing phenomenon.

[0054] A dielectric layer 1143 is formed on the insulating layer 1141 and the bottom electrode 1142 to serve as the gate dielectric layer of the subsequently formed top electrode 1146.

[0055] Specifically, a dielectric layer 1143 can be formed by a thermal oxidation process, extending from the top surface of the second epitaxial material layer 220 to the upper part of the groove, and covering the top surface of the insulating layer 1141 and the top surface of the bottom electrode 1142. This dielectric layer 1143 does not completely fill the groove. The aforementioned deposition process includes, for example, PVD, CVD, atomic layer deposition (ALD), other suitable deposition processes, or combinations of the aforementioned processes.

[0056] In some embodiments, the dielectric layer 1143 may comprise silicon oxide, hafnium oxide, zirconium oxide, aluminum oxide, alumina-hafnium alloy, silicon hafnium dioxide, silicon oxynitride hafnium, tantalum hafnium oxide, titanium hafnium oxide, zirconium hafnium oxide, other suitable high-k dielectric materials, or combinations thereof. In some embodiments, the material of the dielectric layer 1143 is different from the material of the underlying insulating layer 1141. In some other embodiments, the dielectric layer 1143 is made of the same material as the insulating layer 1141.

[0057] It should be noted that during the formation of the dielectric layer 1143, the bottom electrode 1142 is also oxidized, thus forming a thicker insulating portion 1145 above the bottom electrode 1142. In some embodiments, the insulating portion 1145 may also be formed by a deposition process. The insulating portion 1145 may, for example, comprise an insulating oxide. After the subsequent formation of the top electrode 1146, this insulating portion 1145 is located between the bottom electrode 1142 and the top gate 1146, and can serve to electrically isolate the bottom electrode 1142 and the top gate 1146.

[0058] Subsequently, a top gate 1146 is formed in the upper part of the groove. Specifically, a gate electrode material can be deposited on the dielectric layer 1143 and fill the space above the upper part of the groove outside the dielectric layer 1143 by a deposition process (e.g., PVD, CVD, other suitable processes, or combinations thereof), and a thermal process, such as an annealing process, can be selectively performed on the gate electrode material. Afterward, a portion of the gate electrode material is removed, for example, by a planarization process (including CMP, mechanical polishing, etching, other suitable processes, or combinations thereof) to remove the excess portion of the gate electrode material, thereby forming the top gate 1146.

[0059] In some embodiments, the top gate 1146 is located on the dielectric layer 1143 and is separated from the bottom electrode 1142 below by an insulating portion 1145. The top gate 1146 may be a single-layer or multi-layer structure.

[0060] In some embodiments, the top gate 1146 is formed of amorphous silicon, polycrystalline silicon, one or more metals, metal nitrides, metal silicates, conductive metal oxides, or combinations thereof. The aforementioned metals may include, but are not limited to, molybdenum (Mo), tungsten (W), titanium (Ti), tantalum (Ta), platinum (Pt), or hafnium (Hf). The aforementioned metal nitrides may include, but are not limited to, molybdenum nitride (MoN), tungsten nitride (WN), titanium nitride (TiN), and tantalum nitride (TaN). The aforementioned metal silicates may include, but are not limited to, tungsten silicate (WSix). The aforementioned conductive metal oxides may include, but are not limited to, ruthenium oxide (RuO2) and indium tin oxide (ITO).

[0061] In some embodiments, the top gate 1146 may optionally contain a dopant having a second conductivity type (e.g., p-type). Furthermore, the materials used to fabricate the top gate 1146 and the bottom electrode 1142 may be the same or different.

[0062] Accordingly, some example gate structures 11G have been fabricated, but this disclosure is not limited to the example gate structure 11G.

[0063] In some embodiments, the terminal structure 11T includes an insulating layer 1151 and an electrode 1152. The insulating layer 1151 isolates the electrode 1152 from the high-pressure well region 112. In the embodiment of Figure 1, the electrode 1152 may serve as the source of the first element 11.

[0064] In some embodiments, the terminal structure 11T is formed at a predetermined location by a photolithography and patterning process. For example, a mask is first formed on the epitaxial layer 200, and a groove (not shown) is formed in the epitaxial layer 200 (e.g., in the second epitaxial material layer 220) by the mask. Then, an insulating layer 1151 and an electrode 1152 are formed in the groove by a deposition, patterning, and removal process to form the terminal structure 115 (11T). The deposition, patterning, and removal processes are similar to those described above and will not be repeated here.

[0065] In some embodiments, the order in which the gate structure 114 (11G) and the terminal structure 115 (11T) are formed is not particularly limited, and those skilled in the art can adjust it according to actual application. For example, the gate structure 114 (11G) and the terminal structure 115 (11T) can be formed simultaneously, or the terminal structure 115 (11T) can be formed first and then the gate structure 114 (11G).

[0066] According to the embodiment of Figure 1, a well region 116 is formed in the high-pressure well region 112. Specifically, the well region 116 in the first region A1 is a second well region 1162 having a second conductivity type, and the second well region 1162 is disposed between the gate structures 11G and between the gate structure 11G and the terminal structure 11T. In the embodiment of Figure 1, the second conductivity type is p-type, but this disclosure is not limited thereto. In some embodiments, the second well region 1162 has a doping concentration of the second conductivity type (e.g., p-type) of 1E16~5E17 cm⁻³.

[0067] According to the embodiment of Figure 1, a heavily doped region 118 is formed in the well region 116. The heavily doped region 118 in the first region A1 includes a first heavily doped region 1181 having a first conductivity type and a second heavily doped region 1182 having a second conductivity type. In the embodiment of Figure 1, the first conductivity type is n-type and the second conductivity type is p-type, but this disclosure is not limited thereto. In some embodiments, the first heavily doped region 1181 has a doping concentration of 1E18~1E22cm-3 for the first conductivity type (e.g., n-type), and the second heavily doped region 1182 has a doping concentration of 1E18~1E22cm-3 for the second conductivity type (e.g., p-type).

[0068] Accordingly, the fabrication of the first element 11 of the example is completed, but this disclosure is not limited to the first element 11 of this example. In addition, since the driving current flows from the source to the drain, it can be seen that the driving current flows from the central region A1c of the first element 11 through the substrate 100 and the buried layer 300 to the epitaxial layer 200 to the source contact (i.e., along the third direction D3).

[0069] According to the embodiment of Figure 1, an isolation doped region 400 is formed between the first element 11 and the second element 12. In some embodiments, the isolation doped region 400 is also formed between the second element 12 and the third element 13, and between the third element 13 and the fourth element 14. In other words, the isolation doped region 400 is disposed at locations not belonging to the first region A1, the second region A2, the third region A3, and the fourth region A4. That is, the isolation doped region 400 is disposed between the elements to isolate them from each other.

[0070] In some embodiments, the isolation doped region 400 extends downward from the top surface of the epitaxial layer 200 to the bottom surface of the first epitaxial material 210 so that the semiconductor elements (e.g., the first element 11 and the second element 12) achieve good electrical isolation from each other.

[0071] In some embodiments, the isolation doped region 400 has a first conductivity type. In the embodiment of Figure 1, the first conductivity type is n-type, but this disclosure is not limited thereto. In some embodiments, the isolation doped region 400 has a doping concentration of 5E15 to 5E17 cm⁻³ for the first conductivity type (e.g., n-type).

[0072] In some embodiments, isolation doped regions 400 are formed at predetermined locations using lithography and ion implantation processes. For example, a mask (not shown) is first formed on the epitaxial layer 200 where each element is to be formed, and a dopant of a first conductivity type (e.g., an n-type dopant) is implanted in the areas not covered by the mask. The lithography and ion implantation processes are similar to those described above and will not be repeated here.

[0073] According to the embodiment of Figure 1, a C MOS element is provided in the second region A2 as an example of the second element 12; a p-type LDMOS element is provided in the third region A3 as an example of the third element 13; and an n-type LDMOS element is provided in the fourth region A4 as an example of the fourth element 14.

[0074] The components in the second element 12, the third element 13, and the fourth element 14 in Figure 1 will be described in detail below. It should be noted that similar or identical components in the second region A2, the third region A3, and the fourth region A4 can be formed simultaneously or separately according to actual needs. For simplicity, this embodiment of the invention uses the simultaneous formation of similar or identical components in different regions as an example, and will be described in detail below.

[0075] According to the embodiment of Figure 1, high-voltage well regions 132 and 142 are formed in the second epitaxial material layer 220. The second element 12 in the second region A2 does not have a high-voltage well region. In other embodiments, the second element 12 in the second region A2 may also have a high-voltage well region (not shown) of a second conductivity type (e.g., p-type) and have a doping concentration of, for example, 1E15~1E17 cm⁻³. The high-voltage well region 132 of the third element 13 in the third region A3 is a second high-voltage well region 1322 of the second conductivity type. The high-voltage well region 142 of the fourth element 14 in the fourth region A4 has a first high-voltage well region 1421 of a first conductivity type and a second high-voltage well region 1422 of a second conductivity type interleaved. In some embodiments, the first high-voltage well region 1421 is sandwiched between the second high-voltage well regions 1422. In the embodiment of Figure 1, the first conductivity type is n-type and the second conductivity type is p-type, but this disclosure is not limited thereto.

[0076] In some embodiments, the doping concentration of the first high-pressure well region 1421 is greater than the doping concentration of the first epitaxial material layer 210. In some embodiments, the first high-pressure well region 1421 has a doping concentration of a first conductivity type (e.g., n-type) of 1E15~1E17 cm⁻³, and the second high-pressure well regions 1322 and 1422 have a doping concentration of a second conductivity type (e.g., p-type) of 1E15~1E17 cm⁻³.

[0077] In some embodiments, high-pressure well regions 132 and 142 are formed at predetermined locations by a photolithography process and an ion implantation process. For example, a mask (not shown) is first formed on the epitaxial layer 200, and dopants of a first conductivity type and / or a second conductivity type are implanted in the areas not covered by the mask. The photolithography process and the ion implantation process are similar to those described above and will not be repeated here.

[0078] According to the embodiment of Figure 1, well regions 126, 136, and 146 are formed in the second epitaxial material layer 220. The well region 126 of the second element 12 in the second region A2 has a first well region 1261 of a first conductivity type and a second well region 1262 of a second conductivity type that are adjacent to each other. The well region 136 of the third element 13 in the third region A3 is a first well region 1361 of the first conductivity type. The well region 146 of the fourth element 14 in the fourth region A4 has a second well region 1462 of the second conductivity type. In the embodiment of Figure 1, the first conductivity type is n-type and the second conductivity type is p-type, but this disclosure is not limited thereto.

[0079] In some embodiments, the doping concentration of the second well region 1262 and / or the second well region 1462 is greater than the doping concentration of the second epitaxial material layer 220. In some embodiments, the first well regions 1261 and 1361 have a doping concentration of 5E16~5E17 cm⁻³ for a first conductivity type (e.g., n-type), and the second well regions 1262 and 1462 have a doping concentration of 5E16~5E17 cm⁻³ for a second conductivity type (e.g., p-type).

[0080] In some embodiments, well regions 126, 136, and 146 are formed at predetermined locations using a photolithography process and an ion implantation process. For example, a mask (not shown) is first formed on the epitaxial layer 200, and dopants of a first conductivity type and / or a second conductivity type are implanted in the areas not covered by the mask. The photolithography process and the ion implantation process are similar to those described above and will not be repeated here.

[0081] According to the embodiment in Figure 1, heavily doped regions 128, 138, and 148 are formed in well regions 126, 136, and 146 and / or high-pressure well regions 132 and 142. The heavily doped region 128 of the second element 12 in the second region A2 has a first heavily doped region 1281 of a first conductivity type and a second heavily doped region 1282 of a second conductivity type. The heavily doped region 138 of the third element 13 in the third region A3 has a first heavily doped region 1381 of a first conductivity type and a second heavily doped region 1382 of a second conductivity type. The heavily doped region 148 of the fourth element 14 in the fourth region A4 has a first heavily doped region 1481 of a first conductivity type and a second heavily doped region 1482 of a second conductivity type. In the embodiment in Figure 1, the first conductivity type is n-type and the second conductivity type is p-type, but this disclosure is not limited to this.

[0082] In some embodiments, the first heavily doped regions 1281, 1381 and 1481 have a doping concentration of a first conductivity type (e.g., n-type) of 1E18 to 1E22 cm-3, and the second heavily doped regions 1282, 1382 and 1462 have a doping concentration of a second conductivity type (e.g., p-type) of 1E18 to 1E22 cm-3.

[0083] In some embodiments, heavily doped regions 128, 138, and 148 are formed at predetermined locations using a photolithography process and an ion implantation process. For example, a mask (not shown) is first formed on the epitaxial layer 200, and dopants of a first conductivity type and / or a second conductivity type are implanted in the areas not covered by the mask. The photolithography process and the ion implantation process are similar to those described above and will not be repeated here.

[0084] According to the embodiment of Figure 1, a shallow trench isolation 500t is formed in the second epitaxial material layer 220 to isolate different doped regions and well regions. In some embodiments, the shallow trench isolation 500t extends downward from the top surface of the epitaxial layer 200 but does not contact the bottom surface of the well region. In some embodiments, the top surface of the shallow trench isolation 500t is substantially coplanar with the top surface of the epitaxial layer 200.

[0085] In some embodiments, the shallow trench isolation 500t includes an insulating material, which may include silicon oxide, germanium oxide, hafnium oxide, zirconium oxide, aluminum oxide, alumina hafnium alloy, silicon hafnium dioxide, silicon hafnium oxynitride, tantalum hafnium oxide, titanium hafnium oxide, zirconium hafnium oxide, other suitable materials, or combinations of the foregoing materials.

[0086] In some embodiments, shallow trench isolation 500t is formed at predetermined locations by lithography, deposition, patterning, and removal processes. For example, a mask (not shown) is first formed on the epitaxial layer 200, and a portion of the second epitaxial material 220 is removed from the area not covered by the mask to form an opening. Then, suitable material is filled into the opening, and excess material is removed, thereby forming a shallow trench isolation 500t in the opening. The lithography, deposition, patterning, and removal processes are similar to those described above and will not be repeated here.

[0087] In some embodiments, the formation order of high-pressure well regions 132 and 142, well regions 126, 136 and 146, heavily doped regions 128, 138 and 148, and shallow trench isolation 500t is not particularly limited. For example, high-pressure well regions 132 and 142 can be formed first, followed by shallow trench isolation 500t, and then well regions 136 and 146 and heavily doped regions 128, 138 and 148 can be formed sequentially after the formation of shallow trench isolation 500t.

[0088] According to the embodiment of Figure 1, a gate insulating layer 500o is formed on the epitaxial layer 200. In some embodiments, the gate insulating layer 500o spans a first region A1, a second region A2, a third region A3, and a fourth region A4. In some embodiments, the gate insulating layer 500o can be a dielectric material, which may include silicon oxide, hafnium oxide, zirconium oxide, aluminum oxide, alumina-hafnium dioxide alloy, silicon hafnium dioxide, silicon oxynitride hafnium, tantalum hafnium oxide, titanium hafnium oxide, zirconium hafnium oxide, other suitable high-k dielectric materials, or combinations of the foregoing materials.

[0089] In some embodiments, the gate insulating layer 500° is formed by a thermal oxidation process in a blanket-like manner. The deposition process is similar to that described above and will not be repeated here.

[0090] According to the embodiment of Figure 1, gates 12GE, 13GE, and 14GE are formed on the gate insulating layer 500o. In some embodiments, gate 12GE and gate insulating layer 500o in the second region A2 constitute gate structure 12G. In some embodiments, gate 13GE and gate insulating layer 500o in the third region A3 constitute gate structure 13G. In some embodiments, gate 14GE and gate insulating layer 500o in the fourth region A4 constitute gate structure 14G. In the embodiment of Figure 1, gate structure 12G, gate structure 13G, and gate structure 14G are planar gate structures, but this disclosure is not limited thereto.

[0091] In some embodiments, a gate is formed between two adjacent heavily doped regions having the same conductivity type. For example, in the second element 12, a gate 12G is formed between two second heavily doped regions 1282 (serving as a source region and a drain region, respectively) in the first well region 1261, and another gate 12G is formed between two first heavily doped regions 1281 (serving as a source region and a drain region, respectively) in the second well region 1262. In the third element 13, a gate 13G is formed between two second heavily doped regions 1382 (serving as a source region and a drain region, respectively), and another gate 13G is formed between two second heavily doped regions 1382 (serving as a source region and a drain region, respectively). In the fourth element 14, a gate 14G is formed between two first heavily doped regions 1481 (serving as a source region and a drain region, respectively), and another gate 14G is formed between two first heavily doped regions 1481 (serving as a source region and a drain region, respectively).

[0092] In some embodiments, gates 12GE, 13GE, and 14GE comprise conductive materials, which may include amorphous silicon, polycrystalline silicon, other suitable conductive materials, or combinations thereof. In some embodiments, gates 12GE, 13GE, and 14GE are formed at predetermined locations by a deposition process and a patterning process. The patterning process and deposition process are similar to those described above and will not be repeated here.

[0093] Accordingly, the fabrication of the example second element 12, third element 13, and fourth element 14 is completed, but this disclosure is not limited to the example second element 12, third element 13, and fourth element 14. Furthermore, since the drive current flows from the source to the drain, it can be seen that the drive current of the second element 12, third element 13, and fourth element 14 flows along the extension direction of the epitaxial layer 200. For example, the drive current of the second element 12 flows in the channel region between the first heavily doped regions 1281 on both sides of the gate 12G and in the channel region between the second heavily doped regions 1282 on both sides of the gate 12G (i.e., along the first direction D1). The drive current of the third element 13 flows in the channel region between the second heavily doped regions 1382 on both sides of the gate 13G (i.e., along the first direction D1). The drive current of the fourth element 14 flows in the channel region between the first heavily doped regions 1481 on both sides of the gate 14G (i.e., along the first direction D1).

[0094] It should be noted that although this specification describes the first element 11, the isolation doped region 400, the second element 12, the third element 13, the fourth element 14, etc., those skilled in the art can adjust the formation order according to their needs. For example, the isolation doped region 400 can be formed first and then the first element 11, etc., but this disclosure is not limited thereto.

[0095] After completing the first element 11, the second element 12, the third element 13 and the fourth element 14, other components may be formed. The other components will be described below.

[0096] According to the embodiment of Figure 1, an insulating capping layer 500 is formed on the epitaxial layer 200. In some embodiments, the insulating capping layer 500 comprises a dielectric material, which may be similar to the gate insulating layer 500o, and will not be described in detail here. In some embodiments, the insulating capping layer 500 is formed by a deposition process. The deposition process is similar to that described above, and will not be described in detail here.

[0097] It should be noted that in the embodiment of Figure 1, the gate insulating layer 500o and the insulating cap layer 500 have the same material, and therefore there is no obvious boundary. In other embodiments, the gate insulating layer 500o and the insulating cap layer 500 may also be made of different materials.

[0098] According to the embodiment of Figure 1, contacts are formed that penetrate the insulating cap layer 500 and connect to each heavily doped region. Specifically, in the first region A1, a contact is formed that connects to the second heavily doped region 1182. In the second region A2, contacts formed sequentially from left to right are respectively connected to the second heavily doped region 1282 (as a bulk region), the first heavily doped region 1281 (as a source region), the gate 12G, the first heavily doped region 1281 (as a drain region), the second heavily doped region 1282 (as a source region), the gate 12G, the second heavily doped region 1282 (as a drain region), and the first heavily doped region 1281 (as a bulk region).

[0099] In the third region A3, the contacts formed sequentially from left to right are respectively connected to the second heavily doped region 1382 (as a drain region), the gate 13G, the first heavily doped region 1382 (as a source region), the first heavily doped region 1381 (as a substrate region), the second heavily doped region 1382 (as a source region), the gate 13G, and the second heavily doped region 1382 (as a drain region).

[0100] In the fourth region A4, the contacts formed sequentially from left to right are respectively connected to the second heavily doped region 1482 (as the source region), the first heavily doped region 1482 (as the drain region), the gate 14G, the second heavily doped region 1482 (as the source region), the first heavily doped region 1481 (as the substrate region), the second heavily doped region 1482 (as the source region), the gate 14G, the first heavily doped region 1481 (as the drain region), and the second heavily doped region 1482 (as the source region).

[0101] It should be noted that the second heavily doped region 1282 in the second element 12, the first heavily doped region 1381 in the third element 13, and the second heavily doped region 1482 in the fourth element 14, which serve as the substrate region, can be used to prevent the channel region between the source region and the drain region from being interfered with, thereby stabilizing the channel region signal.

[0102] In some embodiments, the contact is formed by a photolithography process, a patterning process, a deposition process, and a removal process. For example, a mask is first formed on an insulating cap layer 500, and a groove (not shown) is formed in the insulating cap layer 500 by means of the mask. Then, conductive material is filled into the groove, and the excess portion is removed to form the contact. The photolithography process and the patterning process are similar to those described above, and will not be repeated here.

[0103] Accordingly, the semiconductor structure 1 of Figure 1 is fabricated. Continuing on, in this embodiment of the invention, by applying a multilayer epitaxial layer structure to integrate semiconductor elements with different driving current directions on the same substrate, the breakdown voltage can be further improved. Furthermore, the multilayer epitaxial layer structure facilitates the placement of buried layers at deeper locations, further reducing on-resistance.

[0104] Figure 2 is a schematic cross-sectional view of semiconductor structure 2 according to some embodiments of the present disclosure. Semiconductor structure 2 is similar to semiconductor structure 1, except that semiconductor structure 2 further includes an isolation layer 600 formed in epitaxial layer 200. In some embodiments, isolation layer 600 is disposed in second region A2, third region A3, and fourth region A4, and is disposed below second element 12, third element 13, and fourth element 14 (third direction D3) to increase breakdown voltage, for example, to above 80V.

[0105] In some embodiments, the isolation layer 600 is spaced apart from the first epitaxial material layer 210 by the second epitaxial material layer 220. That is, the isolation layer 600 and the first epitaxial material layer 210 have a distance d2 in the third direction D3, so that the second element 12, the third element 13, and the fourth element 14 are further isolated from the underlying first epitaxial material layer 210 and the breakdown voltage is improved.

[0106] In some embodiments, the isolation layer 600 has the same second conductivity type (e.g., p-type) as the second epitaxial material 220. In the embodiment of Figure 2, the second conductivity type is p-type, but this disclosure is not limited thereto.

[0107] In some embodiments, the semiconductor structure 2 includes d isolation layers 600, where d is a positive integer greater than or equal to 1. The number (d) of isolation layers 600 may be related to the number (b) of the second epitaxial material layers 220 in the epitaxial layer 200. In some embodiments, b is greater than or equal to d (b≥d). In the embodiment of Figure 2, b is 1 (b=1) and d is 1 (d=1), that is, b equals d (b=d).

[0108] In other embodiments, b may not be equal to d. For example, in the embodiment of Figure 5, b is 2 (b=2) and d is 1 (d=1); in the embodiment of Figure 6, b is 3 (b=3) and d is 2 (d=2); in the embodiment of Figure 7, b is 2 (b=2) and d is 1 (d=1).

[0109] In some embodiments, the doping concentration of the isolation layer 600 is greater than the doping concentration of the second epitaxial material layer 220. In some embodiments, the isolation layer 600 has a doping concentration of a second conductivity type (e.g., p-type) of 1E15 to 5E17 cm⁻³.

[0110] In some embodiments, an isolation layer 600 is formed after the formation of the second epitaxial material layer 220. Specifically, after the epitaxial growth of the second epitaxial material layer 220, a predetermined dopant is implanted within a predetermined area of ​​the second epitaxial material layer 220 by an ion implantation process to form the isolation layer 600.

[0111] As above, by setting an isolation layer under a non-vertical semiconductor element (such as the second element 12), the non-vertical semiconductor element can be further isolated from the first epitaxial material layer 210 having a first conductivity type and the breakdown voltage can be improved.

[0112] Figure 3 is a schematic cross-sectional view of the semiconductor structure 3 according to some embodiments of the present disclosure. The semiconductor structure 3 is similar to the semiconductor structure 1, except that the buried layer 300 extends toward and contacts the substrate 100. This is more conducive to reducing on-resistance and high-current operation (good heat dissipation).

[0113] Figure 4 is a cross-sectional schematic diagram of semiconductor structure 4 according to some embodiments of the present disclosure. Semiconductor structure 4 is similar to semiconductor structure 1, except that the first epitaxial material layer 210 in epitaxial layer 200 includes two first epitaxial material layers 2101 and 2102, and the buried layer 300 includes two buried layers 310 and 320.

[0114] Since the buried layer 300 is formed after the first epitaxial material layer 2102, the buried layer 300 may not reach the expected depth. To address this, by forming the buried layer 310 after the formation of the first epitaxial material layer 2101 and the buried layer 320 after the formation of the first epitaxial material layer 2102, the buried layers 310 and 320 can be connected, further reducing the on-resistance.

[0115] In some embodiments, the doping concentration of the buried layer 320 is less than the doping concentration of the buried layer 310. That is, the doping concentration of the buried layer 320 away from the substrate 100 is less than the doping concentration of the buried layer 310 closer to the substrate 100. For example, the buried layer 310 may have a doping concentration of a first conductivity type (e.g., n-type) of 1E18~5E19 cm⁻³, and the buried layer 320 may have a doping concentration of a first conductivity type (e.g., n-type) of 1E16~5E19 cm⁻³.

[0116] Similar to the buried layer in semiconductor structure 1, since an annealing process is also performed after the formation of the second epitaxial material layer 220, the buried layer 310 is formed simultaneously in the first epitaxial material layer 2101 and the first epitaxial material layer 2102, and the buried layer 320 is formed simultaneously in the first epitaxial material layer 2102 and the second epitaxial material layer 220. This ensures the continuity of the buried layer, thereby further reducing the on-resistance.

[0117] Figure 5 is a schematic cross-sectional view of semiconductor structure 5 according to some embodiments of the present disclosure. Semiconductor structure 5 is similar to semiconductor structure 2, except that the second epitaxial material layer 220 in epitaxial layer 200 includes two second epitaxial material layers 2201 and 2202, and the buried layer 300 includes two buried layers 310 and 320.

[0118] Furthermore, in the embodiment of Figure 5, the isolation layer 600 can reach a deeper depth. Specifically, the isolation layer 600 and the first epitaxial material layer 210 have a distance d5 in the third direction D3. Compared to the distance d2 in the embodiment of Figure 2, the embodiment of Figure 5 has the isolation layer 600 formed before the second epitaxial material layer 2202 is formed, so the isolation layer can be set at a deeper depth, making the distance d5 smaller than the distance d2.

[0119] In some embodiments, an isolation layer 600 is formed after the formation of the second epitaxial material layer 2201, and a second epitaxial material 2202 is formed after the formation of the isolation layer 600. Specifically, after epitaxial growth of the second epitaxial material layer 2201, a predetermined dopant is implanted within a predetermined area of ​​the second epitaxial material layer 2201 by an ion implantation process to form an isolation material. Next, the second epitaxial material layer 2202 is epitaxially grown and annealed, causing the embedded material to diffuse from the second epitaxial material layer 2201 into the second epitaxial material layer 2202, thereby forming the isolation layer 600 as shown in Figure 5. That is, the isolation layer 600 is vertically positioned across the boundary between the second epitaxial material layer 2201 and the second epitaxial material layer 2202, and is simultaneously disposed within both the second epitaxial material layer 2201 and the second epitaxial material layer 2202. That is, the isolation layer 600 extends from the second epitaxial material layer 2201 into the second epitaxial material layer 2202 on the third direction D3. In this way, the isolation layer 600 can reach a deeper position and enhance the isolation capability between the semiconductor device and the first epitaxial material layer 210.

[0120] In some embodiments, by forming a buried layer 310 after forming the first epitaxial material layer 210, and also forming a buried layer 320 after forming the second epitaxial material layer 2201, the buried layers 310 and 320 can be connected, further reducing on-resistance. Similar to the buried layer in semiconductor structure 1, since an annealing process is also performed after forming the second epitaxial material layer 2202, the buried layer 310 is formed simultaneously in both the first epitaxial material layer 210 and the second epitaxial material layer 2201, and the buried layer 320 is formed simultaneously in both the second epitaxial material layer 2201 and the second epitaxial material layer 2202. This ensures the continuity of the buried layers, further reducing on-resistance.

[0121] Furthermore, the doping concentrations of buried layers 310 and 320 are similar to those of buried layers 310 and 320 in Figure 4, and will not be repeated here.

[0122] Figure 6 is a schematic cross-sectional view of semiconductor structure 6 according to some embodiments of the present disclosure. Semiconductor structure 6 is similar to semiconductor structure 5, except that the second epitaxial material layer 220 in epitaxial layer 200 includes three second epitaxial material layers 2201, 2202 and 2203, and the buried layer 300 includes three buried layers 310, 320 and 330, and the isolation layer 600 includes two isolation layers 610 and 620.

[0123] In some embodiments, multiple second epitaxial material layers 220 help increase the thickness of the epitaxial layer and improve the voltage withstand capability of the semiconductor device. Furthermore, multiple layers of second epitaxial material layers 220 also help form multiple isolation layers 600, which further helps to isolate the semiconductor device from the first epitaxial material layer 210.

[0124] In some embodiments, the doping concentration of the isolation layer 620 is greater than that of the isolation layer 610. That is, the doping concentration of the isolation layer 620 away from the substrate 100 is greater than that of the isolation layer 610 closer to the substrate 100. For example, the isolation layer 610 may have a doping concentration of a second conductivity type (e.g., p-type) of 1E15 to 5E17 cm⁻³, and the isolation layer 620 may have a doping concentration of a second conductivity type (e.g., p-type) of 1E16 to 5E18 cm⁻³.

[0125] In some embodiments, buried layers 310, 320, and 330 may have the same or different thicknesses. For example, in the embodiment of Figure 6, buried layers 310, 320, and 330 have the same thickness. In some embodiments, buried layers 310, 320, and 330 may have the same or different doping concentrations. For example, in the embodiment of Figure 6, the doping concentration of buried layer 310 (e.g., 1E18~5E19 cm⁻³) is the same as that of 320, while the doping concentration of buried layer 330 (e.g., 1E16~5E19 cm⁻³) is different from that of buried layer 310. In other embodiments, the doping concentration of buried layer 300 decreases with distance from substrate 100. For example, the doping concentration of buried layer 330 is less than that of buried layer 320, and the doping concentration of buried layer 320 is less than that of buried layer 310.

[0126] In some embodiments, the formation of multiple second epitaxial material layers 220, multiple buried layers 300, and multiple isolation layers 600 is similar to that described above, and will not be repeated here. Since an annealing process is also performed after the formation of the second epitaxial material layer 2203, the isolation layers 610 and 620 can be connected.

[0127] Figure 7 is a schematic cross-sectional view of semiconductor structure 7 according to some embodiments of the present disclosure. Semiconductor structure 7 is similar to semiconductor structure 5, except that the first epitaxial material layer 210 in epitaxial layer 200 includes two first epitaxial material layers 2101 and 2102, and the buried layer 300 includes three buried layers 310, 320 and 330.

[0128] Similar to what was previously described, due to the annealing process, the buried layer 310 is simultaneously disposed in the first epitaxial material layers 2101 and 2102, the buried layer 320 is simultaneously disposed in the first epitaxial material layer 2102 and the second epitaxial material layer 2201, and the buried layer 330 is simultaneously disposed in the second epitaxial material layers 2201 and 2202. The doping concentration of the buried layers 310, 320 and 330 is similar to that in Figure 6 and will not be repeated here.

[0129] Figure 8 is a schematic cross-sectional view of the semiconductor structure 8 according to some embodiments of the present disclosure. The semiconductor structure 8 is similar to the semiconductor structure 2, except that the semiconductor structure 8 replaces the backplane metal layer with a drain structure 11D. Therefore, since the drain structure 11D is disposed in the high-pressure well region 1121 in the form of a trench, the drain of the first element 11 will not affect the second element 12, the third element 13, and the fourth element 14, thereby reducing interference between elements and improving the performance of the semiconductor structure.

[0130] In some embodiments, the drain structure 11D is disposed in the surrounding region A1p of the first region A1. In some embodiments, the drain structure 11D is disposed on the outermost side of the first element 11. In some embodiments, the drain structure 11D extends from the top surface of the epitaxial layer 200 into the buried layer 300.

[0131] In some embodiments, the drain structure 11D includes an insulating layer 1191 and an electrode 1192. The insulating layer 1191 isolates the electrode 1192 from the high-pressure well region 112.

[0132] In some embodiments, a drain structure 11D is formed at a predetermined location by a photolithography and patterning process. For example, a mask is first formed on the epitaxial layer 200, and a groove (not shown) is formed in the epitaxial layer 200 (e.g., in the second epitaxial material layer 220) by the mask. Then, an insulating layer 1191 and an electrode 1192 are formed in the groove by a deposition, patterning, and removal process to form a drain structure 119 (11D). The deposition, patterning, and removal processes are similar to those described above and will not be repeated here.

[0133] In some embodiments, the terminal structure 115 (11T) may be formed first and then the drain structure 119 (11D) may be formed, but this disclosure is not limited thereto.

[0134] In some embodiments, a contact is formed through the insulating cover layer 500 and connected to the drain structure 11D, and its formation is similar to that of other contacts, which will not be described in detail here.

[0135] As above, in this embodiment of the invention, the drain structure replaces the backplane metal layer, so that the drain of the vertical semiconductor device (e.g., the first element 11) is isolated, and the performance of the non-vertical semiconductor device (e.g., the second element 12) will not be affected, thereby further improving the performance of integrating different semiconductor devices.

[0136] In summary, the semiconductor structure provided in this disclosure embodiment can integrate various types of semiconductor devices, especially semiconductor devices with different current directions, on the same substrate (e.g., a wafer). In the application of the embodiment, vertical semiconductor devices with a vertical current direction, such as VDMOS devices, and non-vertical semiconductor devices with a non-vertical current direction (e.g., horizontal direction), such as CMOS, LDPMOS, and LDNMOS, can be integrated.

[0137] The semiconductor structure provided in this disclosure embodiment, by means of epitaxial layers of multilayer structure containing epitaxial material layers of different conductivity types, can provide a vertical semiconductor device current path while providing a higher voltage platform, and at the same time provide a non-vertical semiconductor device drift region (high-voltage well region).

[0138] The semiconductor structure provided in this disclosure embodiment can reduce the on-resistance of the vertical semiconductor device by providing a buried layer under the vertical semiconductor device. Furthermore, by using a multilayer epitaxial layer, the buried layer can be placed at a deeper location, which is even more beneficial for reducing the on-resistance.

[0139] The semiconductor structure provided in this disclosure embodiment can increase the isolation capability and improve the breakdown voltage of a non-vertical semiconductor device by setting an isolation layer under it. Furthermore, by having different conductivity types between the isolation layer (e.g., p-type) and the underlying epitaxial layer (e.g., n-type), unwanted vertical electric fields can be avoided at the non-vertical semiconductor device.

[0140] The semiconductor structure provided in this disclosure embodiment, by distributing isolation doped regions between semiconductor devices, enables these semiconductor devices to be electrically isolated from each other, thereby achieving good electrical performance. For example, according to the embodiment, BCD (including bipolar devices, CMOS devices, and DMOS devices) and VDMOS devices can be integrated on the same wafer to comprehensively solve the design challenges of complex, high-power applications. The semiconductor structure provided in this disclosure embodiment, by using a drain structure as the drain for vertical semiconductor devices, prevents non-vertical semiconductor devices from being affected by the drain, thereby improving integration performance.

[0141] Furthermore, when integrating different semiconductor components, similar parts can be fabricated together in the same process, which can save steps. For example, well regions or heavily doped regions of the same conductivity type can be formed in the same process. Therefore, the process of the embodiment is simple and does not significantly increase additional manufacturing costs.

[0142] Although the embodiments and advantages of this disclosure have been disclosed above, it should be understood that anyone skilled in the art can make modifications, substitutions, and refinements without departing from the spirit and scope of this disclosure. Furthermore, the scope of protection of this disclosure is not limited to the processes, machines, manufacturing, material composition, apparatus, methods, and steps described in the specific embodiments of this specification. Anyone skilled in the art can understand from the disclosure of some embodiments of this disclosure the current or future development of processes, machines, manufacturing, material composition, apparatus, methods, and steps, as long as they can perform substantially the same function or obtain substantially the same results in the embodiments described herein, and can be used according to some embodiments of this disclosure. Therefore, the scope of protection of this disclosure includes the aforementioned processes, machines, manufacturing, material composition, apparatus, methods, and steps. In addition, each claim constitutes an individual embodiment, and the scope of protection of this disclosure also includes combinations of various claim claims and embodiments. [Simplified Explanation of the Diagram]

[0143] Figures 1 to 8 are schematic cross-sectional views of semiconductor structures according to some different embodiments of the present disclosure.

Claims

1. A semiconductor structure, comprising: One substrate; An epitaxial layer is disposed on the substrate, wherein the epitaxial layer includes: a first epitaxial material layer disposed on the substrate and having a first conductivity type; The semiconductor structure comprises: a second epitaxial layer disposed on the first epitaxial layer and having a second conductivity type different from the first conductivity type; an isolation doped region extending from the top surface of the second epitaxial layer to the top surface of the first epitaxial layer, having the first conductivity type and separating a first region and a second region of the semiconductor structure; a first element disposed in the first region; a second element disposed in the second region; and a buried layer disposed in the first region and having the first conductivity type, the buried layer being disposed under the first element.

2. The semiconductor structure as claimed in claim 1, wherein the buried layer is disposed in the epitaxial layer and extends from the first epitaxial material layer to the second epitaxial material layer.

3. The semiconductor structure as claimed in claim 1, wherein the buried layer contacts the top surface of the substrate.

4. The semiconductor structure as claimed in claim 1 further includes an isolation layer disposed in the second region and having the second conductivity type, and the isolation layer is disposed in the second epitaxial material layer and disposed under the second element.

5. The semiconductor structure as claimed in claim 4, wherein the isolation layer is spaced apart from the first epitaxial material layer by the second epitaxial material layer.

6. The semiconductor structure as claimed in claim 4, wherein the doping concentration of the isolation layer is greater than the doping concentration of the second epitaxial material layer.

7. The semiconductor structure as claimed in claim 4, wherein the epitaxial layer further includes another second epitaxial material layer disposed on the second epitaxial material layer and having the second conductivity type, wherein the isolation layer further extends into the other second epitaxial material layer.

8. The semiconductor structure as claimed in claim 1, wherein the epitaxial layer further includes another first epitaxial material layer disposed between the first epitaxial material layer and the second epitaxial material layer and having the first conductivity type.

9. The semiconductor structure as claimed in claim 8 further includes another buried layer disposed thereon, wherein the doping concentration of the buried layer is greater than the doping concentration of the other buried layer.

10. The semiconductor structure as claimed in claim 1, wherein the substrate serves as a drain of the first element.

11. The semiconductor structure as claimed in claim 1, further comprising a drain structure as a drain of the first element, wherein the drain structure extends from the top surface of the epitaxial layer into the buried layer.

12. The semiconductor structure as claimed in claim 1, wherein the driving current of the first element flows from the epitaxial layer toward the substrate, and the driving current of the second element flows along the extension direction of the epitaxial layer.

13. The semiconductor structure as claimed in claim 1 further includes a high-voltage well region disposed in the first region and having the first conductivity type, and the high-voltage well region is disposed in the second epitaxial material layer.

14. The semiconductor structure as claimed in claim 13, wherein the first element is disposed in the high-pressure well region, and the first element is a vertically diffused metal-oxide-semiconductor (VDMOS) device.

15. The semiconductor structure as claimed in claim 1, further comprising another isolation doped region extending from the top surface of the second epitaxial layer to the top surface of the first epitaxial layer, and the other isolation doped region having the first conductivity type and separating the second region of the semiconductor structure from a third region.

16. The semiconductor structure as claimed in claim 15 further includes a third element disposed in the third region, wherein a drive current of the third element flows along the top surface of the epitaxial layer.

17. The semiconductor structure as claimed in claim 1, further comprising a backplane metal layer disposed on the substrate opposite to the epitaxial layer.

18. The semiconductor structure as described in claim 1, wherein the epitaxial layer comprises: a first epitaxial layer is disposed on the substrate, wherein the a first epitaxial layer has the first conductivity type, and a is a positive integer greater than or equal to 1; and b second epitaxial layers are disposed on the a epitaxial layer, wherein the b second epitaxial layers have the second conductivity type, and b is a positive integer greater than or equal to 1; wherein the isolation doped region extends from the top surface of the b second epitaxial layers to the top surface of the a first epitaxial layer; wherein the buried layer includes c buried layers, where c is a positive integer greater than or equal to 1, wherein the sum of a and b is greater than c, and the difference between the sum of a and b and c is 1.

19. The semiconductor structure of claim 18, wherein when c is greater than or equal to 2, the doping concentration of the buried layer away from the substrate is less than the doping concentration of the buried layer near the substrate.

20. The semiconductor structure as claimed in claim 18 further includes d isolation layers disposed in the second region and having the second conductivity type, and the d isolation layers are disposed under the second element and in the epitaxial layer, wherein d is a positive integer and is greater than or equal to 1.

21. The semiconductor structure as described in claim 20, wherein b is greater than or equal to d.

22. The semiconductor structure as described in claim 20, wherein when d is greater than or equal to 2, the doping concentration of the isolation layer farther from the substrate is greater than the doping concentration of the isolation layer closer to the substrate.

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