Method for producing electrical isolation between high-voltage bipolar-CMOS-DMOS (HV-BCD) devices

Abstract

Techniques are described for robust transistor isolation in high-voltage Bipolar-CMOS-DMOS (HV-BCD) devices. Embodiments incorporate silicon-boron (Si:B) epitaxially grown (EPI) buried layers into HV-BCD devices, such between a P- substrate and a P- EPI layer. Such structures reduce parasitic NPN transistor effects by controlling the alpha ratio, linked to boron concentration and electron diffusion barriers. Some embodiments add co-doped layers with oxygen and / or carbon to control P- EPI layer features, such as thickness, dopant profile, and breakdown voltage (Vbd). Co-doping can be achieved by low-pressure chemical vapor deposition (LPCVD).

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