Semiconductor device and manufacturing method thereof

Abstract

A method includes: forming a dielectric liner in an opening above a source / drain (S / D) feature in a semiconductor structure; forming a recess in the S / D feature through the opening via plasma etching; removing a byproduct from forming the recess via a wet cleaning process; and forming a silicide contact that extends from a sidewall of the opening above the S / D feature to a bottom of the opening in the recess in the S / D feature.

Claims

1. A method for manufacturing a semiconductor device, comprising: A dielectric pad is formed in an opening of a source / drain feature in a semiconductor structure; A groove is formed in the source / drain feature through the opening via plasma etching; a byproduct forming the groove is removed via a wet cleaning process; and a silicon contact is formed extending from one side wall of the opening above the source / drain feature to the bottom of the opening in the groove of the source / drain feature.

2. The method as described in claim 1, wherein the opening comprises a cone shape.

3. The method as described in claim 1, wherein forming the groove includes forming the groove, wherein the bottom of the opening in the groove extends to the underside of a first nanosheet.

4. The method as described in claim 1, wherein forming the silicate contact includes forming the silicate contact on the dielectric pad and on the source / drain feature in the groove.

5. A semiconductor device, comprising: A gate structure surrounding a plurality of nanosheets; A source / drain characteristic is present in the vicinity of the plurality of nanosheets; A dielectric pad is located above the source / drain feature; a groove is located in and below the source / drain feature; and a siliconized contact extends from the dielectric pad above the source / drain feature into the groove in the source / drain feature.

6. The semiconductor device as claimed in claim 5, wherein a length of about 8 nm to about 16 nm is measured across a top of a first nanosheet of the plurality of nanosheets.

7. The semiconductor device as claimed in claim 5, wherein the silicate contact includes an operable depth between about 14 nm and about 37 nm for measuring a height from a top of a first nanosheet of the plurality of nanosheets to a bottom of the silicate contact.

8. The semiconductor device as claimed in claim 5, wherein the silicon contact includes a circumferential angle of a bottom tapered profile between about 95° and about 135°.

9. A method for manufacturing a semiconductor device, comprising: A dielectric pad is formed in an opening above a source / drain feature in a semiconductor structure; A groove is dry-etched through the opening in the source / drain feature; a wet cleaning is performed using a chemical substance that has high wet etching selectivity for the material of the source / drain feature and the material of the dielectric pad due to a dry etching byproduct in the groove. And forming a silicon contact that extends from one side wall of the opening above the source / drain feature to the bottom of the opening in the groove of the source / drain feature.

10. The method as described in claim 9, wherein forming the silicate contact includes forming the silicate contact using titanium silicate, cobalt silicate, nickel silicate, or copper silicate.

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