Gate dielectrics of nanostructure transistors and the methods of forming the same

Abstract

A method includes forming a plurality of semiconductor nanostructures comprising a lower semiconductor nanostructure and a topmost semiconductor nanostructure over the lower semiconductor nanostructure, forming interfacial layers contacting the plurality of semiconductor nanostructures, and depositing high-k dielectric layers encircling the interfacial layers. A topmost high-k dielectric layer of the high-k dielectric layers encircling the topmost semiconductor nanostructure includes a topmost horizontal portion overlapping the topmost semiconductor nanostructure, a bottom horizontal portion overlapped by the topmost semiconductor nanostructure, and a sidewall portion on a sidewall of the topmost semiconductor nanostructure. A first one of the topmost horizontal portion, the bottom horizontal portion, and the sidewall portion has a first thickness. A second one of the topmost horizontal portion, the bottom horizontal portion, and the sidewall portion has a second thickness smaller than the first thickness.

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