Semiconductor device and method for making semiconductor device

Abstract

A Deep Trench Capacitor (DTC) structure and method of forming the same including forming a transistor on an electrode within a DTC trench, the trench including alternating layers of a high K dielectric material and metal electrode material for functioning as a capacitor. The electrode transistor structure is formed to control electrical conductivity from the transistor gate to the connected metallic electrode layer of the DTC trench by the application of a gate voltage to switch on and off a capacitance provided by a first capacitor, i.e., first electrode(s) and high K dielectric pair, within the DTC trench. A DTC stacking structure provides the stacking and bonding of DTC wafers and dies by bonding electrical contact pairs or groups of each DTC wafer to provide a stacked DTC structure and / or device.

Description

Technical Field

[0001] This disclosure relates to a semiconductor device having a capacitor and a method for manufacturing the same. Prior Technology

[0002] The following discussion relates to integrated circuits (ICs) employing capacitor devices and / or structures and their fabrication. Summary of the Invention

[0003] Some embodiments of this disclosure provide a method for manufacturing a semiconductor device, comprising: forming a first trench in a substrate, the first trench including a first trench bottom and a plurality of first trench sides; forming a first group of alternating layers in the first trench including alternating layers of electrodes and dielectric layers, the alternating layers of the first group covering the first trench bottom and the plurality of first trench sides, and the alternating layers of the first group including a first metal electrode layer, a second metal electrode layer, and a first dielectric layer disposed between the first metal electrode layer and the second metal electrode layer to form a first capacitor, each of the first metal electrode layer and the second metal electrode layer including a first longitudinal end and a second longitudinal end; forming a filled dielectric region in a central region of the first trench, the filled dielectric region being formed in the first trench. A dielectric region extends along a longitudinal length of the first trench, and the dielectric region forms a core dielectric region of the first trench, the core dielectric region being at least partially surrounded by alternating layers of the first group; a thin-film transistor structure is formed on the first longitudinal end of the first metal electrode layer, the thin-film transistor structure including a gate region, a dielectric region, and a semiconductor region, the semiconductor region being operatively connected to the first metal electrode layer, the thin-film transistor structure being configured to control the conductivity from the gate region of the thin-film transistor structure to the first metal electrode layer by applying a gate voltage to switch on and off a capacitance provided by the first capacitor; and a first metal contact is formed on the gate region of the thin-film transistor structure, and a second metal contact is formed on the first longitudinal end of the second metal electrode.

[0004] Some embodiments of this disclosure provide a semiconductor device comprising: a semiconductor substrate; a first trench formed in the semiconductor substrate, the first trench including a first trench bottom and a plurality of first trench sides; a first group of alternating layers including alternating electrode layers and dielectric layers formed in the first trench, the first group of alternating layers covering the first trench bottom and the plurality of first trench sides, and the first group of alternating layers including a first metal electrode layer, a second metal electrode layer, and a first dielectric layer disposed between the first metal electrode layer and the second metal electrode layer to form a first capacitor, each of the first metal electrode layer and the second metal electrode layer including a first longitudinal end and a second longitudinal end; a filling A dielectric region is formed in the first trench at a central region of the first trench, the filling dielectric region extending along a longitudinal length of the first trench and forming a core dielectric region of the first trench, the core dielectric region being at least partially surrounded by alternating layers of the first group; and a thin-film transistor structure is formed on the first longitudinal end of the first metal electrode layer, the thin-film transistor structure including a gate region, a dielectric region, and a semiconductor region operatively connected to the first metal electrode layer, the thin-film transistor structure being configured to control the conductivity from the gate region of the thin-film transistor structure to the first metal electrode layer by applying a gate voltage to switch on and off a capacitance provided by the first capacitor.

[0005] Some embodiments of this disclosure provide a method of manufacturing a semiconductor device, comprising: forming a first deep trench capacitor structure in a first semiconductor substrate, the first deep trench capacitor structure including a plurality of planarized metal contacts electrically connected to a plurality of electrodes within a trench formed in the first semiconductor substrate, and the plurality of planarized metal contacts extending into an intermetallic region formed on the first semiconductor substrate; and forming a second deep trench capacitor structure in a second semiconductor substrate, the second deep trench capacitor structure including a plurality of planarized metal contacts electrically connected to a plurality of electrodes within a trench formed in the second semiconductor substrate, and the plurality of planarized metal contacts extending into an intermetallic region formed on the first semiconductor substrate; and forming a second deep trench capacitor structure in a second semiconductor substrate, the second deep trench capacitor structure including a plurality of planarized metal contacts electrically connected to a plurality of electrodes within a trench formed in the second semiconductor substrate, and the plurality of planarized metal contacts extending into an intermetallic region formed in the first semiconductor substrate. Metal contacts extend into an intermetallic region formed on the second semiconductor substrate; the first deep trench capacitor structure is bonded to the second deep trench capacitor structure by bonding each of the plurality of planarized metal contacts of the first deep trench capacitor structure to a corresponding one of the plurality of planarized metal contacts of the second deep trench capacitor structure, thereby electrically connecting the first deep trench capacitor structure and the second deep trench capacitor structure; and a first integrated circuit interconnect structure is formed, the first integrated circuit interconnect structure including a plurality of metal contacts electrically connected to the plurality of electrodes within the first deep trench capacitor structure to provide an integrated circuit (IC) including a stacked deep trench capacitor (DTC) structure. Simple Explanation of the Diagram

[0006] The various aspects of this disclosure can be best understood by reading the following detailed description in conjunction with the accompanying drawings. Note that, in accordance with industry standard practice, the features are not drawn to scale. In fact, for clarity of discussion, the dimensions of the features may be arbitrarily increased or decreased. Figure 1A is a cross-sectional view of an integrated circuit (IC) structure (Embodiment 1A) according to an exemplary embodiment of the present disclosure. This IC structure includes a planar adjustable stacked structure for deep trench capacitors (DTCs). This embodiment includes a plurality of discrete deep trench capacitor structures CapA1, CapB1, and CapC1, each of which has a trench extending from an intermetallic dielectric region into the substrate. Each of these deep trench capacitor structures has a planar electrode contact interface, and wherein the deep trench capacitor structures CapB1 and CapC1 are adjustable. Figure 1B is a top view of the integrated circuit structure shown in Figure 1A (Embodiment 1A) according to an exemplary embodiment of the present disclosure. Figure 1C is a schematic diagram of the integrated circuit shown in Figure 1A (Implementation 1A). Figure 1D is a cross-sectional view of an integrated circuit (IC) structure (Embodiment 1B) according to an exemplary embodiment of the present disclosure. This IC structure includes a planar adjustable stacked structure for a deep trench capacitor (DTC) structure. This embodiment includes a plurality of discrete deep trench capacitor structures CapA1, CapB1, and CapC1, wherein each of the CapA1 and CapB1 deep trench capacitor structures has a trench extending from an inter-metal dielectric region into the substrate, and the CapC1 deep trench capacitor structure has a relatively shallow trench only within the inter-metal dielectric region. Each of these deep trench capacitor structures has a planar electrode contact interface, and the deep trench capacitor structures CapB1 and CapC1 are adjustable. Figure 1E is a cross-sectional view of an integrated circuit (IC) structure (Embodiment 1C) comprising a planar adjustable stacked structure for a deep trench capacitor (DTC) structure according to an exemplary embodiment of the present disclosure. This embodiment includes a plurality of discrete deep trench capacitor structures CapA1, CapB1, and CapC1, wherein each of the CapA1 and CapB1 deep trench capacitor structures has a trench extending from an intermetallic dielectric region into the substrate, and the CapC1 deep trench capacitor structure has a relatively shallow trench only within the substrate. Each of these deep trench capacitor structures has a planar electrode contact interface, and the deep trench capacitor structures CapB1 and CapC1 are adjustable. Figure 2A is a cross-sectional view of an integrated circuit (IC) structure (Embodiment 2A) according to an exemplary embodiment of this disclosure. This IC structure includes a 2.5D-like adjustable stacked structure for a deep trench capacitor (DTC) structure. This embodiment includes a plurality of discrete deep trench capacitor structures CapA2, CapB2, and CapC2. Each of these deep trench capacitor structures includes a stepped metal-insulator-metal (MIM) electrode contact interface that extends into an intermetallic dielectric region. Each of the CapA2 and CapB2 deep trench capacitor structures has a trench only within a first substrate, while the CapC2 deep trench capacitor structure has a trench only within a second substrate. The deep trench capacitor structure CapC2 is adjustable to be operatively / selectively connected to capacitor electrodes outside the deep trench capacitor structure CapA2 to increase the capacitance of this structure. Figure 2B is a cross-sectional view of an integrated circuit (IC) structure (Embodiment 2B) according to an exemplary embodiment of this disclosure. This IC structure includes a 2.5D-type adjustable stacked structure for a deep trench capacitor (DTC) structure. This embodiment includes a plurality of discrete deep trench capacitor structures CapA2, CapB2, and CapC2, wherein the CapA2 deep trench capacitor structure has trenches extending from a first intermetallic dielectric region into a first substrate and includes planar electrode contact interfaces; the CapB2 deep trench capacitor structure extends only into the first substrate and includes planar electrode contact interfaces; and the CapC2 deep trench capacitor structure has trenches only within a second substrate and includes a stepped MIM electrode contact interface extending into a second intermetallic dielectric region. The CapC2 deep trench capacitor structure is adjustable to be operatively / selectively connected to capacitor electrodes outside the CapA2 deep trench capacitor structure to increase the capacitance of this structure. Figure 3A is a cross-sectional view of an integrated circuit (IC) structure (Embodiment 3A) according to an exemplary embodiment of this disclosure. This IC structure includes a 3D-like adjustable stacked structure for a deep trench capacitor (DTC) structure. This embodiment includes a plurality of discrete deep trench capacitor structures CapA3 and CapB3, each of which includes a stepped metal-insulator-metal (MIM) electrode contact interface extending into an intermetallic dielectric region. The CapA3 deep trench capacitor structure has a double trench extending only within a first substrate, and the CapB3 deep trench capacitor structure has a double trench extending only within a second substrate. The CapB3 deep trench capacitor structure is adjustable to be operatively / selectively connected to one of the plurality of capacitor electrodes of the CapA2 deep trench capacitor structure to increase the capacitance of this structure. Figure 3B is a cross-sectional view of an integrated circuit (IC) structure (Embodiment 3B) according to an exemplary embodiment of the present disclosure, which includes a 3D-like adjustable stacked structure for a deep trench capacitor (DTC) structure. This embodiment includes a plurality of discrete deep trench capacitor structures CapA3(1), CapA3(2), and CapB3, each of which includes a stepped metal-insulator-metal (MIM) electrode interface extending into an intermetallic dielectric region. Each of the CapA3(1) and CapA3(2) deep trench capacitor structures has a trench extending only within a first substrate, and the CapB3 deep trench capacitor structure has a trench extending only within a second substrate. The deep trench capacitor structure CapB3 is adjustable to be operatively / selectively connected to one of the plurality of electrodes of the deep trench capacitor structure CapA3(1) to increase the capacitance of this structure. Figure 3C is a cross-sectional view of an integrated circuit (IC) structure (embodiment 3C) according to an exemplary embodiment of the present disclosure. This IC structure includes a 3D-like adjustable stacked structure for a deep trench capacitor (DTC) structure. This embodiment includes a plurality of discrete deep trench capacitor structures CapA3(1), CapA3(2), CapB3(1), and CapB3(2), each of which includes a planar electrode contact interface, wherein each of the CapA3(1) and CapA3(2) deep trench capacitor structures has The deep trench capacitor structures CapB3(1) and CapB3(2) have trenches extending only within the first substrate. The deep trench capacitor structure CapB3(1) is operatively / selectively connected to one of the multiple electrodes of the deep trench capacitor structure CapA3(1) to increase the capacitance of the structure. The deep trench capacitor structure CapB3(2) is operatively / selectively connected to one of the multiple electrodes of the deep trench capacitor structure CapA3(2) to increase the capacitance of the structure. Figures 4A through 4N illustrate various manufacturing stages associated with the fabrication of an integrated circuit structure (Embodiment 1A) according to an exemplary embodiment of this disclosure. Figure 4A shows the formation of a stop layer and an intermetallic dielectric layer on a substrate; Figure 4B shows the stages of etching trenches and depositing trench pads; Figure 4C shows the stages of depositing electrodes and high-k dielectric (High K, HK) dielectric material and depositing filler dielectric material; Figure 4D shows the removal of the filler dielectric material and grinding the longitudinal ends of the electrodes, as well as the formation of a back-end of line (BEOL) transistor (e.g., a thin film transistor on the longitudinal end of a single electrode). The process involves several stages: Figure 4E shows the deposition of intermetallic dielectric material on the trench structure and the back-end process transistor; Figure 4F shows the deposition of an etch stop layer followed by the deposition of additional intermetallic dielectric material; Figure 4G shows the formation of multiple electrical contacts leading to the trench electrode and the back-end process gate; Figure 4H shows the grinding of the top surface, deposition of additional intermetallic dielectric material, and etching of the second trench; Figure 4I shows the formation of the second trench electrode, a high dielectric constant layer between the multiple electrodes, and filling the second trench with dielectric filler material. The stages of the two trench cores; Figure 4J shows the stage of forming multiple contacts leading to the first trench, as well as the patterned metallization layer M1 and the etch stop layer; Figure 4K shows the stage of grinding the etch stop layer, depositing additional intermetallic dielectric material, and forming another etch stop layer; Figure 4L shows the formation of multiple contacts (leading to the second trench electrode); Figure 4M shows the formation of multiple vias V1 (electrically connected to the patterned metallization layer M1); and Figure 4N shows the completed structure after forming another patterned metallization layer M (M is 2 to N) electrically connected to the first trench vias V1 and the second trench contacts. Figures 5A through 5F illustrate various manufacturing stages associated with the fabrication of an integrated circuit structure (Embodiment 2A) according to an exemplary embodiment of this disclosure. Figure 5A shows the formation of a trench pad layer and an intermetallic dielectric layer on a substrate; Figure 5B shows the stage of etching a first trench and a second trench and depositing additional pad material in the trenches; Figure 5C shows the deposition of electrodes and high dielectric constant (High) materials in both the first trench and the second trench. Figure 5D shows the stages of depositing and filling dielectric material in the first and second trenches; Figure 5D shows the stages of removing the filled dielectric material, depositing an etch stop layer, depositing additional intermetallic dielectric material, performing a patterned photoresist lithography process (4 times) to form the electrode stepped structure shown, forming multiple electrode metal contacts, and polishing these electrode contacts; Figure 5E shows the next stage including the joining of a similarly formed second deep trench capacitor structure, wherein the polished metal contacts are joined to stack the first deep trench capacitor structure and the second deep trench capacitor structure; and Figure 5F shows the final stage of the manufacturing process, including polishing this structure to expose multiple electrode metal contacts of the second deep trench capacitor structure, forming an etch stop layer, depositing additional intermetallic dielectric material, forming multiple metal contacts electrically connected to the electrodes of the second deep trench capacitor structure, and performing a patterned deposition process to form a metallized circuit layer M1. Figures 6A to 6D illustrate the various manufacturing stages associated with the manufacture of the integrated circuit structure (Embodiment 3A) according to an exemplary embodiment of this disclosure. Figure 6A shows the initial stage of two deep trench capacitor wafers after grinding (only one is shown); Figure 6B shows the bonding of the wafers via multiple metal contacts bonding each of the wafers; Figure 6C shows the stages of grinding this structure to expose the electrodes of one of the wafers, depositing intermetallic dielectric material, forming multiple metal contacts leading to multiple electrodes in the top wafer trench, and subsequently depositing intermetallic dielectric material and patterned metallization circuitry and a passivation layer, which provide multiple electrical connections of the resulting three-dimensional stacked deep trench capacitor structure on the first side, and similar to Figure 6C, Figure 6D shows the stages of grinding this structure to expose the electrodes of one of the wafers, depositing intermetallic dielectric material, forming multiple metal contacts leading to multiple electrodes in the top wafer trench, and subsequently depositing intermetallic dielectric material and patterned metallization circuitry and a passivation layer, which provide multiple electrical connections of the resulting three-dimensional stacked deep trench capacitor structure on the second side. Implementation

[0007] The following disclosure provides numerous different implementations or embodiments to carry out various features of the provided subject matter. Specific embodiments of components and arrangements are described below to simplify this disclosure. These are, of course, merely embodiments and are not intended to be limiting. For example, in the following description, forming a first feature above or on top of a second feature may include implementations where the first and second features are formed in direct contact, and may also include implementations where additional features may be formed between the first and second features, thus the first and second features may not be in direct contact. Additionally, reference numerals and / or letters may be repeated in various embodiments of this disclosure. This repetition is for the purpose of simplicity and clarity, and does not in itself imply a relationship between the various implementations and / or configurations discussed.

[0008] Numerical values ​​in the specification and claims of this application should be understood to include the same numerical value when reduced to the same significant figures, as well as numerical values ​​that differ from the stated value by less than the experimental error of the measurement technique of the type described in this application in determining that value. All ranges disclosed herein include the stated endpoints.

[0009] The term "approximately" can be used to include any variable numerical value without altering the fundamental function of that value. When used with a range, "approximately" also indicates a range defined by the absolute values ​​of its two endpoints; for example, "approximately 2 to approximately 4" also indicates a range "from 2 to 4". The term "approximately" may refer to plus or minus 10% of the number shown.

[0010] This disclosure relates to structures composed of multiple distinct layers. When the terms "on" or "above" are used to refer to two distinct layers (including the substrate), they simply mean that one layer is on or above the other. These terms do not require that the two layers be in direct contact with each other and allow other layers to be in between. For example, all layers in this structure can be considered to be "on" the substrate, even if they are not all in direct contact with the substrate. The term "directly" can be used to indicate that two layers are in direct contact with each other, with no layers in between. Furthermore, when referring to performing process steps on the substrate, this should be interpreted as performing such steps on any layers that may be present on the substrate, depending on the context.

[0011] Furthermore, spatially relative terms such as “below,” “lower,” “lower,” “higher,” “upper,” and similar terms may be used herein to describe the relationship between one element or feature and another, as illustrated in the diagrams. In addition to the directions depicted in the diagrams, spatially relative terms are intended to cover different orientations of the device in use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatially relative descriptive terms used herein can be interpreted in the same manner.

[0012] The term "layer" as used in this document may include a single layer or multiple layers.

[0013] As used herein, "conductive characteristics" refers to metallized contacts, patterned metallized contacts, or other electrically conductive metal contacts.

[0014] The term "intermetal dielectric" (IMD) as used in this article refers to a dielectric layer / insulating material layer between two metal layers.

[0015] As used in this article, the term "interlayer dielectric" (ILD) refers to a structure of insulating material disposed between two conductive layers.

[0016] In this article, the terms "circuit" and "metalline" refer to conductive paths constructed during the back end of line (BEOL) process, which transmit electrical signals through the circuit pattern of a semiconductor wafer.

[0017] As used herein, the terms "stacked" and "vertically stacked" refer to the stacking or formation of two or more transistor structures, wherein the first and second transistors are arranged or formed in a substantially elongated pattern, in contrast to a planar structure comprising two or more transistor structures arranged side by side. The terms "vertical" or "vertically" are not relative to gravity and may include lateral arrangements, wherein the first transistors are laterally stacked and formed adjacent to a second lateral transistor, as disclosed herein.

[0018] Some embodiments disclosed herein relate to semiconductor devices, including stacked capacitor device structures and methods of forming thereof. Specifically, this disclosure provides deep trench capacitor (DTC) structures, deep trench capacitor devices, and deep trench capacitor integrated circuits (ICs) having various trench depths and / or deep trench capacitor structure types integrated and fabricated into silicon substrates and / or dielectric regions, providing tunable / adjustable or variable capacitance performance of the resulting structures, devices, and / or integrated circuits. Furthermore, the tunable capacitor structure enables precise control of the capacitance of the resulting deep trench capacitor structure for integration with other integrated circuit devices or structures to meet the specific functional requirements of the resulting integrated circuit or device.

[0019] The additional embodiments disclosed herein include the use of wafer and / or die stacking arrangements, wherein the bonding of multiple semiconductor wafers is achieved by bonding multiple electrical contacts (electrically connected to the deep trench capacitor electrodes of the first and second wafers) at wafer bonding boundaries to bond the first and second wafers (e.g., bottom and top wafers), and providing a completed deep trench capacitor structure that includes one or more capacitor structures selectively using each of these wafers, depending on the selection of these electrode contacts for the wafer bonding process. In other words, as will be further described below, this disclosure provides configurable deep trench capacitor structures that use wafer bonding processes to selectively provide selectable or configurable deep trench capacitor structures with selectable or configurable capacitance in a single or shared device, thereby providing a variety of stacking structures (e.g., planar / 2.5D / 3D) that enable deep trench capacitors to have diverse applications in three-dimensional integrated circuits (3DIC).

[0020] Deep trench capacitors (DTCs) are semiconductor devices used to add capacitance to a variety of integrated circuits. One advantage of using DTCs is that they can be packaged at high density and provide higher capacitance per unit area than other capacitor devices. DTCs are used in a wide range of integrated circuit applications, such as networking, communications, optical communications, medical devices, and automotive electronics.

[0021] According to some embodiments, multiple deep trench capacitor structures are formed in one or more silicon substrates and / or intermetallic dielectric layers, wherein these deep trench capacitor structures (i.e., wafers or dies) are bonded to multiple electrode contact holes. Back-end processing (BEOL) formed transistors, such as IGZO thin-film transistors (TFTs), form one or more electrodes, each associated with one or more capacitors of the deep trench capacitor to provide tunable functionality for the deep trench capacitor structure. Specifically, the back-end processing transistors are functionally used to effectively turn on and off conductive paths (from a voltage source applied to the deep trench capacitor device to the electrodes / electrode layers within the trenches of the deep trench capacitor structure), and the switched electrodes are operatively associated with a dielectric layer (for storing a portion of the charge capacitance of this device). In other words, by switching the downstream process transistor on and off, the capacitance of the underlying deep trench capacitor structure can be adjusted or calibrated, where switching the downstream process transistor on provides a relatively high capacitance, and switching the downstream process transistor off provides a relatively low capacitance.

[0022] Furthermore, a deep trench capacitor stack structure and its formation method are disclosed, wherein (1) the deep trench capacitor stack structure or device provides different capacitances simultaneously within a single deep trench capacitor or integrated circuit product; (2) the disclosed deep trench capacitor structure can be extended horizontally and vertically, providing a relatively large surface area to increase capacitance; and (3) the disclosed three-dimensional integrated circuit structure allows circuit connections to both sides of the stacked wafer structure, providing a variety of three-dimensional structural applications. In addition, incorporating the adjustable back-end process capacitors disclosed herein into the deep trench capacitor stack structure allows for precise adjustment of the required capacitance in the deep trench capacitor product without structural modification.

[0023] According to some embodiments, the deep trench capacitor trenches are 1) entirely within the substrate, 2) within the intermetallic dielectric, or 3) within both the substrate and the intermetallic dielectric layer. These deep trench capacitor structure locations provide flexibility allowing for different device designs and can also reduce the trench depth within the substrate, thereby minimizing the risk of wafer breakage. Furthermore, having deep trench capacitor trenches only within the intermetallic dielectric can reduce the complexity of the insulating layer fabrication process, i.e., directly depositing the electrode / high dielectric constant (HK) layer.

[0024] Referring to Figure 1A, a cross-sectional view of an integrated circuit (IC) structure (Embodiment 1A) according to an exemplary embodiment 1001A of this disclosure is shown. This IC structure includes a planar adjustable stacked structure for a deep trench capacitor (DTC) structure. This embodiment includes a plurality of discrete deep trench capacitor structures CapA1, CapB1, and CapC1, each having trenches 110A, 110B, and 110C extending from intermetallic dielectric regions 106A and / or 106B into the substrate. Each of these deep trench capacitor structures has a planar electrode contact interface, and deep trench capacitor structures CapB1 and CapC1 are adjustable. Figure 1B is a top view of the IC structure shown in Figure 1A (Embodiment 1A) according to an exemplary embodiment of this disclosure, while Figure 1C is a schematic diagram of the IC shown in Figure 1A (Embodiment 1A).

[0025] More specifically, referring to Figures 1A to 1C, the structure 1001A disclosed includes the following.

[0026] A first deep trench capacitor structure, CapA1, includes a trench 110A, a pad 120 formed in a substrate 102, and the trench 110A extending into intermetallic dielectric (IMD) regions 106A and 106B formed on the substrate 102. The capacitive function of the deep trench capacitor structure CapA1 is provided by alternating layers of electrode materials E1A, E2A, E3A, and E4A and high dielectric constant (HK) dielectric materials HK1A, HK2A, HK3A, and HK4A, which surround a core material of the filling dielectric 126 of the trench 110A. Operationally, to store charge within the multiple high dielectric constant dielectric layers HK1A to HK4A of the trench 110A, a voltage is applied to one or more of these electrodes E1A to E4A through multiple electrical contacts (e.g., multiple contact holes 140A1, 140A2, 140A3, and 140A4, respectively).

[0027] During the manufacturing process, trench 110A is etched to a total depth TDA, wherein the trench depth TDA consists of an initial trench depth TDA1 (within the substrate 102) and an additional trench depth TDA2 (within the intermetallic dielectric layer or regions 106A and 106B).

[0028] The second deep trench capacitor structure CapB1 includes a trench 110B, a pad 120 formed in a substrate 102, and the trench 110B extending into intermetallic dielectric (IMD) regions 106A and 106B formed on the substrate 102. The capacitive function of the deep trench capacitor structure CapB1 is provided by alternating layers of electrode materials E1B, E2B, E3B, and E4B, and high dielectric constant (HK) dielectric materials HK1B, HK2B, HK3B, and HK4B, which surround a core material of the filling dielectric 126 of the trench 110B. Operationally, to store charge within the multiple high dielectric constant dielectric layers HK1B to HK4B of the trench 110B, a voltage is applied to one or more of the multiple electrodes E1B to E4B through multiple electrical contacts (e.g., multiple contact holes 140B1, 140B2, 140B3, and 140B4, respectively).

[0029] During the manufacturing process, trench 110B is etched to a total depth TDB, wherein the trench depth TDB consists of an initial trench depth TDB1 (within the substrate 102) and an additional trench depth TDB2 (within the intermetallic dielectric layer or regions 106A and 106B).

[0030] Unlike the deep trench capacitor structure CapA1, the deep trench capacitor structure CapB1 includes a back-end transistor 130B formed on electrode E1B, such as an indium gallium zinc oxide (IGZO) thin-film transistor (TFT). The back-end transistor 130B is either not in contact with any adjacent electrode or is isolated from any adjacent electrode. The back-end transistor includes a gate region 131B, a gate dielectric region 132B, and an active semiconductor region 133B made of IGZO or other suitable semiconductor materials. In operation, the back-end transistor is selectively turned on or off to adjust or change the capacitance of the deep trench capacitor structure CapB1. Specifically, the back-end transistor 130B is functionally used to effectively turn on and off conductive paths. (From a voltage source applied to the deep trench capacitor device contact 140B1 to the electrode / electrode layer E1B within the trench 110B), wherein the switched electrode E1B is operatively associated with dielectric layers HK1B / HK2B (for storing a portion of the charge capacitance of this device). In other words, the capacitance of the underlying deep trench capacitor structure CapB1 can be calibrated or adjusted by switching the downstream process transistor 130B on and off, wherein switching the downstream process transistor 130B on provides a relatively high capacitance, and switching the downstream process transistor 130B off provides a relatively low capacitance of the device.

[0031] The third deep trench capacitor structure CapB1 includes a trench 110C and a pad 120 formed in a substrate 102. The trench 110C extends only into the intermetallic dielectric (IMD) region 106A formed on the substrate 102 (unlike CapA1 and CapB1, which extend into the interlayer dielectric 106B). The capacitive function of the deep trench capacitor structure CapC1 is provided by alternating layers of electrode materials E1C, E2C, E3C, and E4C and high dielectric constant (HK) dielectric materials HK1C, HK2C, HK3C, and HK4C, which surround a core material of the filling dielectric 126 of the trench 110C. In operation, in order to store charge within the multiple high dielectric constant dielectric layers HK1C to HK4C in the trench 110C, a voltage is applied to one or more of the multiple electrodes E1C to E4C through multiple electrical contacts (e.g., multiple contact holes 140C1, 140C2, 140C3 and 140C4 respectively).

[0032] During the manufacturing process, trench 110A is etched to a total depth TDC, wherein the trench depth TDC consists of an initial trench depth TDC1 (within the substrate 102) and an additional trench depth TDC2 (within the intermetallic dielectric layer or region 106A).

[0033] Unlike the deep trench capacitor structure CapA1 and similar to the deep trench capacitor structure CapB1, the deep trench capacitor structure CapC1 includes a back-end transistor 130C formed on the electrode E1C, such as an indium gallium zinc oxide (IGZO) thin-film transistor (TFT). The back-end transistor includes a gate region 131C, a gate dielectric region 132C, and an active semiconductor region 133C made of IGZO or other suitable semiconductor materials. In operation, the back-end transistor is selectively turned on or off to adjust or change the capacitance of the deep trench capacitor structure CapC1. Specifically, the back-end transistor 130C... This can be used to effectively turn the conductive path (from the voltage source applied to the deep trench capacitor device contact 140C1 to the electrode / electrode layer E1C within the trench 110C), wherein the switched electrode E1B is operatively associated with the dielectric layers HK1C / HK2C (for storing a portion of the charge capacitance of this device). In other words, by switching the downstream process transistor 130C on and off, the capacitance of the underlying deep trench capacitor structure CapC1 can be calibrated or adjusted, wherein switching the downstream process transistor 130C on provides a relatively high capacitance, while switching the downstream process transistor 130C off provides a relatively low capacitance of the device.

[0034] Patterned metallization or metal layers M2 (2 to N) 152 are patterned and formed to connect to the electrical interface and to the deep trench capacitors CapA1 and CapB1 structures to the external circuit, and to provide the necessary interconnection of multiple electrodes for the desired operation of the deep trench capacitors. Furthermore, metallization or metal layers M1 151, multiple vias 160, and M2 (2-N) 152 are formed to connect to the electrical interface and to the deep trench capacitor CapC1 structure to the external circuit, and to provide the necessary interconnection of multiple electrodes for the desired operation of the deep trench capacitors, for example, selectively connecting multiple deep trench capacitor structures. To accommodate variations in capacitance, a wide range of designs for these metal layers 151 can be implemented, wherein, for example, the depth of the deep trench capacitor trenches can be individually varied within the intermetallic dielectric of the different metal (2 to N) layers. Furthermore, as will be described below with reference to Figure 1C, the connection for the high voltage 4 and low voltage 2 (Hi-Volt 4 and Lo-Volt 2) on the upper metal layer can be on the same layer or on different metal layers.

[0035] During the deep trench capacitor trench fabrication process, etch stop layers 104A, 104B, 104C, 104D, and 104E are used to provide the necessary etch stop functionality to fabricate the various deep trench capacitor structural layers and features described and shown in Figure 1A, including but not limited to multiple intermetallic dielectric regions 106A, 106B, 106C, 106D, and 106E. A passivation layer 180 is formed throughout the deep trench capacitor structure to protect the deep trench capacitor structure from the influence of the surrounding environment.

[0036] For ease of understanding, referring to Figures 1C, 1A, and 1B, the equivalent circuit of a 4-electrode / 3-capacitor structure is shown. This equivalent circuit includes multiple capacitors CA1, CA2, and CA3, as well as a high-voltage potential connection / source 4 and a low-voltage potential connection / source 2. The equivalent capacitor circuit shown represents a single deep trench capacitor structure, i.e., CapA1, CapB1, and / or CapC1 as shown in Figures 1A and 1B.

[0037] The 4-electrode / 3-capacitor structure corresponds to the following implementation 1A 1001A: CA1, CA2, and CA3 each represent multiple layers of alternating electrode-dielectric-electrode layers, where E1A-HK1A-E2A is denoted as CA1; E2A-HK2A-E3A is denoted as CA2; and E3A-HK3A-E4A is denoted as CA4. The adjustable device 130B in Figure 1C represents, for example, a deep trench capacitor structure CapB1 back-end process transistor 130B. The optional adjustable device shown in the schematic diagram of Figure 1C is simply illustrated to indicate that any one or more deep trench capacitor devices or structures can be formed to include back-end process transistors on the electrodes to provide the ability to switch the capacitor branches in the trenches of the deep trench capacitor structure on (ON) or off (OFF), thereby providing an adjustable or tunable capacitance function for the deep trench capacitor. Furthermore, as shown in Figure 1A, each of the multiple electrodes and multiple high-dielectric-constant dielectric charge-retaining regions extend to different lengths around the trench of the deep trench capacitor, with the outer electrode / high-dielectric-constant dielectric layer being longer than the inner electrode / high-dielectric-constant dielectric layer. As a result, the outer electrode / high-dielectric-constant dielectric layer has a relatively higher capacitance than the inner electrode / high-dielectric-constant dielectric layer.

[0038] In operation, the back-end transistor can be independently controlled by applying a gate voltage. The operating principle of the back-end transistor involves adjusting the gate voltage to control whether current flows through it. Different gate voltage levels can be applied through various metal pattern designs, or the thickness of the back-end transistor can be adjusted to change the voltage it can withstand. This allows for fine-tuning of the required capacitance to suit the voltage requirements of the product or device.

[0039] Compared to the stepped MIM electrode contact interface structure 402 or non-planar profile shown in Figure 2B, other features of the disclosed deep trench capacitor structure shown in Figures 1A and 1B include planar structures, including planar electrode contact interface structures or interconnect structures 401. Furthermore, the disclosed deep trench capacitor structure of Embodiment 1A 1001A provides a structure that accommodates multiple deep trench capacitor devices, such as deep trench capacitor structures CapA1, CapB1, and CapC1, which have different trench depths, or more generally, these deep trench capacitor devices are themselves different types of deep trench capacitor devices or structures.

[0040] According to some example implementations, the substrate used herein may comprise an advanced wafer or a silicon-based wafer.

[0041] According to some exemplary embodiments, the electrodes of the deep trench capacitor can be made of TiN, Ru, carbon, polycrystalline silicon, etc., and the dielectric of the high dielectric constant capacitor of the deep trench capacitor can be made of aluminum oxide (Al2O3), zirconium dioxide (ZrO2), hafnium dioxide (HfO2), etc.

[0042] According to some example implementations, the deep trench capacitor stack structure can be any number of electrode layers / high-k capacitor dielectric film layers, any number of intermetallic dielectric film layers and metal layers, and the deep trench capacitor trench is not limited to a specific shape or contour used within the silicon substrate and / or intermetallic dielectric film.

[0043] Referring to Figure 1D, a cross-sectional view of an integrated circuit (IC) structure (Embodiment 1B) according to an exemplary embodiment of this disclosure is shown. This IC structure includes a planar adjustable stacked structure for a deep trench capacitor (DTC) structure. This embodiment includes a plurality of discrete deep trench capacitor structures CapA1, CapB1, and CapC1, wherein each of the CapA1 and CapB1 deep trench capacitor structures has a trench extending from an intermetallic dielectric region into the substrate, and the CapC1 deep trench capacitor structure has a relatively shallow trench only within the intermetallic dielectric region. Each of these deep trench capacitor structures has a planar electrode contact interface 401, and the deep trench capacitor structures CapB1 and CapC1 are adjustable.

[0044] According to this embodiment, unlike Embodiment 1A 1001A, these deep trench capacitor structures include a plurality of deep trench capacitor structures, wherein not all deep trench capacitor trenches extend into the substrate 102. The deep trench capacitor CapC1 trench 110C is etched only in the intermetallic dielectric region 106A, and the trench 110C has a trench depth of TDC / TDC2.

[0045] Referring to Figure 1E, a cross-sectional view of an integrated circuit (IC) structure (Embodiment 1C) according to an exemplary embodiment of this disclosure is shown. This IC structure includes a planar, adjustable stacked structure for a deep trench capacitor (DTC) structure. Unlike Embodiments 1A 1001A and 1B, this embodiment includes a plurality of discrete deep trench capacitor structures CapA1, CapB1, and CapC1, wherein each of the CapA1 and CapB1 deep trench capacitor structures has trenches 110A and 110B extending from intermetallic dielectric regions 106A and 106B into the substrate 102, and the CapC1 deep trench capacitor structure includes a relatively shallow trench 110C only within the substrate 102. As previously described in Embodiments 1A 1001A and 1B 1001B, each of the plurality of deep trench capacitor structures has a planar electrode contact interface 401, and the deep trench capacitor structures CapB1 and CapC1 are adjustable.

[0046] Referring to Figure 2A, a cross-sectional view of an integrated circuit (IC) structure (Embodiment 2A) according to an exemplary embodiment of this disclosure is shown. This IC structure includes a type 2.5D adjustable stacked structure for a deep trench capacitor (DTC) structure. This stacked structure includes a single-sided metal-patterned circuit or layer / line 251 for electrical connection to external devices and / or configuration and control of the underlying deep trench capacitor structures CapA2, CapB2, and CapC2. Compared to multiple embodiments 1A 1001A, 1B 1001B and 1C 1001C, embodiment 2A 2001A includes a 2.5D type stacked structure of multiple deep trench capacitor wafers or dies (DTC(W / D)1 and DTC(W / D)2), wherein each deep trench capacitor wafer has a stepped metal-insulator-metal (MIM) electrode contact interface structure 402 extending into the intermetallic dielectric region, wherein each of the CapA2 and CapB2 deep trench capacitor structures has double trenches "210A1 and 210A2" and "210B1 and 210B2" respectively within the first substrate 202AB of wafer DTC(W / D)1, and the CapC2 deep trench capacitor structure has double trenches 210C1 and 210C2 within the second substrate 202C of wafer DTC(W / D)2.

[0047] The deep trench capacitor structure CapC2 can be calibrated via transistor 130C, which is operatively / selectively connected to electrode E1 of the deep trench capacitor structure CapC2 to increase the capacitance of this structure. Wafer DTC(W / D)1 and DTC(W / D)2 are bonded at or near the bonding boundary BB by bonding multiple pairs of contact holes (contact holes 240A1, 240C1; 240A2, 240C2; 240A3, 240C3; 240B1, 240C4; 240B2, 240C5; and 240B3, 240C6). As shown in Figure 2A, this embodiment may include N deep trench capacitor structures, wherein the N+1th and N-1th deep trench capacitor structures or dies are formed on wafer DTC(W / D)1 adjacent to deep trench capacitor structures CapA2 and CapB2, where N = 1, 2, ... N. Furthermore, this embodiment may include M deep trench capacitor structures, wherein the M+1 and M-1 deep trench capacitor structures or dies are formed on the wafer DTC(W / D)2 adjacent to the deep trench capacitor structure CapC2, where M = 1, 2, ... M.

[0048] More specifically, the disclosed structure 2001A includes the following.

[0049] The first deep trench capacitor structure CapA2 includes double trenches 210A1 and 210A2, with a pad 120 formed in a substrate 202AB. The capacitive function of the deep trench capacitor structure CapA2 is provided by alternating layers of multiple electrode materials E1, E2, and E3 and a high-k (HK) dielectric material (not identified by reference numerals in Figure 2A for clarity), which surround a core material 126 of the filling dielectric material of trenches 210A1 and 210A2. Operationally, to store charge within the multiple high-k dielectric layers of trenches 210A1 and 210A2, voltage is applied to one or more of the electrodes E1 to E3 through multiple electrical contacts (e.g., multiple contact holes 240A1, 240A2, and 240A3, respectively).

[0050] During the manufacturing process, trenches 210A1 and 210A2 are etched to a total depth TDA1 / TDA, wherein the trench depth TDA1 / TDA is within the substrate 202AB. A stepped MIM electrode contact interface structure 402 formed on the substrate 202AB within the intermetallic dielectric region 206AB provides the necessary electrode connections to multiple contacts 240A1, 240A2, and 240A3.

[0051] The formation of the second deep trench capacitor structure CapB2 is similar to that of the deep trench capacitor structure CapA2, including double trenches 210B1 and 210B2, with a pad 120 formed in the substrate 202AB. The capacitive function of the deep trench capacitor structure CapB2 is provided by alternating layers of electrode materials E1, E2, and E3 and high-k dielectric (HK) dielectric material (not referred to by reference numerals in Figure 2A for clarity), which surround the core material of the filling dielectric 126 of the trenches 210B1 and 210B2. Operationally, to store charge within the multiple high-k dielectric layers of the trenches 210B1 and 210A2, voltage is applied to one or more of the multiple electrodes E1 to E3 through multiple electrical contacts (e.g., multiple contact holes 240B1, 240B2, and 240B3, respectively).

[0052] During the manufacturing process, trenches 210B1 and 210B2 are etched to a total depth TDB1 / TDB, wherein the trench depth TDB1 / TDB is within the substrate 202AB. A stepped MIM electrode contact interface structure 402 is formed within the intermetallic dielectric region 206AB on the substrate 202AB and provides the necessary electrode connections to a plurality of contacts 240B1, 240B2 and 240B3.

[0053] The formation of the third deep trench capacitor structure CapC2 is similar to the formation of deep trench capacitor structures CapA2 and CapB2 on another substrate 202C, i.e., wafer or die DTC(W / D)2, including dual trenches 210C1 and 210C2, with a pad 120 formed in the substrate 202C. The capacitive function of the deep trench capacitor structure CapC2 is provided by alternating layers of electrode materials E1 to E9 and high dielectric constant (HK) dielectric material layers (not referred to by reference numerals in Figure 2A for clarity), which surround the core material of the filling dielectric 126 of trenches 210C1 and 210C2. Operationally, in order to store charge within the multiple high dielectric constant dielectric layers of trenches 210C1 and 210C2, a voltage is applied to one or more of the multiple electrodes E1 to E9 through multiple electrical contacts (e.g., multiple contact holes C1 to C9 respectively).

[0054] During the manufacturing process, trenches 210C1 and 210C2 are etched to a total depth TDC1 / TDC, wherein the trench depth TDC1 / TDC is within the substrate 202C. A stepped MIM electrode contact interface structure 402 formed on the substrate 202C within the intermetallic dielectric region 206C1 provides the necessary electrode connections to a plurality of contacts 240C1 to 240C6 leading to the wafer / die DTC (W / D) 1.

[0055] Unlike the deep trench capacitor structures CapA2 and CapB2, the deep trench capacitor structure CapC2 includes a back-end transistor 130C, such as an indium gallium zinc oxide (IGZO) thin-film transistor (TFT) formed on electrode E1C. The back-end transistor 130C is either not in contact with any adjacent electrode or is isolated from any adjacent electrode. The back-end transistor includes a gate region 131C, a gate dielectric region 132C, and an active semiconductor region 133C made of IGZO or other suitable semiconductor materials. In operation, the back-end transistor is selectively turned on or off to adjust or change the deep trench capacitor structure CapC2. The capacitance of apC2. Specifically, the back-end transistor 130C is functionally used to effectively turn the conductive path (from the voltage source applied to the deep trench capacitor device contact C1 to the electrode / electrode layer E1 within the trench 210C1), wherein the switched electrode E1 is operatively associated with the dielectric layer (for storing a portion of the charge capacitance of this device). In other words, by switching the back-end transistor 130C on and off, the capacitance of the underlying deep trench capacitor structure CapC2 can be calibrated or adjusted, wherein switching the back-end transistor 130C on provides a relatively high capacitance, while switching the back-end transistor 130C off provides a relatively low capacitance of the device.

[0056] The patterned metallization or metal layer M1 251 is patterned and formed to provide a side-mounted metallization connection electrical interface, connect the deep trench capacitor CapC2 structure to an external circuit, and provide the necessary interconnection of multiple electrodes for the desired operation of the deep trench capacitor, such as selectively connecting multiple deep trench capacitor structures.

[0057] During the deep trench capacitor trench fabrication process, multiple etch stop layers 204A, 204B, 204C, and 204D are used to provide the necessary etch stop functionality to fabricate the various deep trench capacitor structural layers and features described and shown in Figure 2A, including but not limited to multiple intermetallic dielectric regions 206AB, 206C1, 206C2, and 206C3. A passivation layer (not shown) is formed throughout the deep trench capacitor structure to protect it from the surrounding environment.

[0058] Referring to Figure 2B, a cross-sectional view of an integrated circuit (IC) structure (Embodiment 2B) according to an exemplary embodiment of this disclosure is shown. This IC structure includes a 2.5D-type adjustable stacked structure for a deep trench capacitor (DTC) structure. This embodiment includes a plurality of discrete deep trench capacitor structures CapA2, CapB2, and CapC2, wherein the CapA2 deep trench capacitor structure has trenches extending from a first intermetallic dielectric region into a first substrate and includes planar electrode contact interfaces 401. The CapB2 deep trench capacitor structure extends only into the first substrate and includes planar electrode contact interfaces 401. The CapC2 deep trench capacitor structure has trenches only within a second substrate and includes stepped MIM electrode contact interfaces 402 extending into a second intermetallic dielectric region. The CapC2 deep trench capacitor structure is adjustable to be operatively / selectively connected to capacitor electrodes outside the CapA2 deep trench capacitor structure to increase the capacitance of this structure.

[0059] The deep trench capacitor structure CapC2 can be tuned via transistor 130C, which is operatively / selectively connected to electrode E1 of CapC2 to increase the capacitance of this structure. Wafer DTC(W / D)1 and wafer DTC(W / D)2 are bonded at or near the bonding boundary BB by joining multiple pairs of contact holes (contact holes 240A1, 240C1; 240A2, 240C2; 240A3, 240C3; 240B1, 240C4; 240B2, 240C5; and 240B3, 240C6). As shown in Figure 2B, this embodiment can include N deep trench capacitor structures, wherein the N+1th and N-1th deep trench capacitor structures or dies are formed on wafer DTC(W / D)1 adjacent to deep trench capacitor structures CapA2 and CapB2, where N = 1, 2, ... N. Furthermore, this embodiment may include M deep trench capacitor structures, wherein the M+1 and M-1 deep trench capacitor structures or dies are formed on the wafer DTC(W / D)2 adjacent to the deep trench capacitor structure CapC2, where M = 1, 2, ... M.

[0060] More specifically, the disclosed structure 2001B includes the following.

[0061] The first deep trench capacitor structure CapA2 includes a trench 210A and a pad 120 formed in a substrate 202AB. The capacitive function of the deep trench capacitor structure CapA2 is provided by alternating layers of electrode materials E1, E2, and E3 and a high-k (HK) dielectric material (not indicated by reference numerals in Figure 2A for clarity), which surround a core material of the filling dielectric 126 of the trench 210A. Operationally, to store charge within the multiple high-k dielectric layers of the trench 210A, a voltage is applied to one or more of the electrodes E1 to E3 through multiple electrical contacts (e.g., multiple contact holes 240A1, 240A2, and 240A3, respectively).

[0062] During the manufacturing process, trenches 210A and 210A2 are etched to a total depth TDA, wherein trench depth TDA1 is within the substrate 202AB, and an additional trench depth TDA2 is etched within the intermetallic dielectric region 206AB1. A planar electrode contact interface structure 401 is formed within the intermetallic dielectric region 206AB on the substrate 202AB and provides the necessary electrode connections to a plurality of contacts 240A1, 240A2, and 240A3.

[0063] The second deep trench capacitor structure CapB2 includes a trench 210B and a pad 120 formed in a substrate 202AB. The capacitive function of the deep trench capacitor structure CapB2 is provided by alternating layers of electrode materials E1, E2, and E3 and a high-k dielectric material (not referred to by reference numerals in Figure 2A for clarity), which surround a core material of the filling dielectric 126 of the trench 210B. Operationally, to store charge within the multiple high-k dielectric layers of the trench 210B, a voltage is applied to one or more of the electrodes E1 to E3 through multiple electrical contacts (e.g., multiple contact holes 240B1, 240B2, and 240B3, respectively).

[0064] During the manufacturing process, trench 210B is etched to a total depth TDB1, wherein the trench depth TDB1 is entirely or completely within the substrate 202AB. A planar electrode contact interface structure 401 is formed on the substrate 202AB and provides the necessary electrode connections to contacts 240B1, 240B2, and 240B3.

[0065] The formation of the third deep trench capacitor structure CapC2 is similar to the formation of CapC2 in Embodiment 2001A described above with reference to Figure 2A, and will not be repeated here. Unlike the deep trench capacitor structures CapA2 and CapB2, the deep trench capacitor structure CapC2 includes a back-end transistor 130C, such as an indium gallium zinc oxide (IGZO) thin-film transistor (TFT). The back-end transistor 130C is formed on the electrode E1C and is either not in contact with any adjacent electrode or is isolated from any adjacent electrode. The back-end transistor includes a gate region 131C, a gate dielectric region 132C, and an active semiconductor region 133C made of IGZO or other suitable semiconductor materials, as previously described with reference to CapC2 in Figure 2A.

[0066] The patterned metallization or metal layer M1 251 is patterned and formed to provide a side-mounted metallization connection electrical interface and connect the deep trench capacitor CapC2 structure to an external circuit, and provide the necessary interconnection of multiple electrodes for the desired operation of the deep trench capacitor, such as selectively connecting multiple deep trench capacitor structures.

[0067] During the deep trench capacitor trench fabrication process, etch stop layers 204A(1), 204A(2), 204B, 204C, and 204D are used to provide the necessary etch stop functionality to fabricate the various deep trench capacitor structural layers and features described and shown in Figure 2A, including but not limited to multiple intermetallic dielectric regions 206AB1, 206AB2, 206C1, 206C2, and 206C3. A passivation layer (not shown) is formed throughout the deep trench capacitor structure to protect it from the surrounding environment.

[0068] Referring to Figure 3A, a cross-sectional view of an integrated circuit (IC) structure (Embodiment 3A) 3001A according to an exemplary embodiment of this disclosure is shown. This IC structure includes a 3D-like adjustable stacked structure for a deep trench capacitor (DTC) structure. This embodiment includes a plurality of discrete deep trench capacitor structures CapA3 and CapB3, each of which includes a stepped metal-insulator-metal (MIM) electrode contact interface 402 extending into an intermetallic dielectric region. The CapA3 deep trench capacitor structure has a double trench extending only within a first substrate, and the CapB3 deep trench capacitor structure has a double trench extending only within a second substrate. The deep trench capacitor structure CapB3 is adjustable to be operatively / selectively connected to one of the plurality of capacitor electrodes of the deep trench capacitor structure CapA2 to increase the capacitance of this structure.

[0069] The deep trench capacitor structure CapB3 can be calibrated via transistor 130B, which is operatively / selectively connected to the electrode E1 of the deep trench capacitor structure CapB3 to increase the capacitance of this structure. The wafer deep DTC(W / D)1 and wafer DTC(W / D)2 are bonded at or near the bonding boundary BB by bonding multiple pairs of contact holes (contact holes 340A1, 340B1; 340A2, 340B2; 340A3, 340B3; 340A4, 340B4; 340A5, 340B5; and 340A6, 340B6). As shown in Figure 3A, this embodiment may include N deep trench capacitor structures, wherein the N+1th and N-1th deep trench capacitor structures or dies are formed on wafer DTC(W / D)1 adjacent to the deep trench capacitor structure CapA3, where N = 1, 2, ... N. Furthermore, this implementation may include M deep trench capacitor structures, wherein the M+1th and M-1th deep trench capacitor structures or dies are formed on wafer DTC(W / D)2 adjacent to deep trench capacitor structure CapB3, where M = 1, 2, ... M. Additionally, the deep trench capacitor structures include a "selective connection" configuration, wherein, depending on the desired capacitance of the structure and / or product requirements, the electrodes in the deep trench capacitors may be selectively unconnected or connected in the middle.

[0070] More specifically, the disclosed structure 3001A includes the following.

[0071] The first deep trench capacitor structure CapA3 includes dual trenches 310A1 and 310A2, with a pad 120 formed in a substrate 302A. The capacitive function of the deep trench capacitor structure CapA3 is provided by alternating layers of electrode materials E1, E2, and E3 and a high dielectric constant (HK) dielectric material (not referred to by reference numerals in Figure 3A for clarity), which surround the core material of the filling dielectric 126 of the trenches 310A1 and 310A2. In operation, in order to store charge within multiple high dielectric constant layers in trenches 310A1 and 310A2, voltage is applied to one or more of multiple electrodes E1 to E3 through multiple electrical contacts (e.g., multiple contact holes 340A1, 340A2 and 340A3 respectively), and / or voltage is applied to one or more of multiple electrodes E9 to E12 through multiple electrical contacts (multiple contact holes 340A4, 340A5 and 340A6 respectively); or multiple electrodes E1 to E12 and multiple contact holes C1 to C12 respectively.

[0072] During the manufacturing process, trenches 310A1 and 310A2 are etched to the total depth of TDA, wherein the trench depth TDA is entirely within the substrate 302A. A stepped MIM electrode contact interface structure 402 formed on the substrate 302A within the intermetallic dielectric region 306A1 provides the necessary electrode connections to multiple contacts 340A1, 340A2, and 340A3.

[0073] The formation of the second deep trench capacitor structure CapB3 is similar to that of the deep trench capacitor structure CapA3, including dual trenches 310B1 and 310B2, with a pad 120 formed in the substrate 302B. The capacitive function of the deep trench capacitor structure CapB3 is provided by alternating layers of electrode materials E1, E2, and E3 and a high-dielectric-constant (HK) dielectric material (not referred to by reference numerals in Figure 3A for clarity), which surround the core material of the filling dielectric 126 of trenches 310B1 and 310B2. Operationally, to store charge within the multiple high-dielectric-constant dielectric layers of trenches 310B1 and 310B2, a voltage is applied to one or more of the multiple electrodes E1 to E12 through multiple electrical contacts (e.g., multiple contact holes C1 to C12, respectively).

[0074] During the manufacturing process, trenches 310B1 and 310B2 are etched to a total depth TDB, wherein the trench depth TDB is entirely within the substrate 302B. A stepped MIM electrode contact interface structure 402 is formed within the intermetallic dielectric region 306B1 on the substrate 302B and provides the necessary electrode connections to multiple contacts 340B1, 340B2, 340B3, 340B4, 340B5, and 340B6.

[0075] Unlike the deep trench capacitor structure CapA3, the deep trench capacitor structure CapB3 includes a back-end transistor 130B, such as an indium gallium zinc oxide (IGZO) thin-film transistor (TFT) formed on electrode E1. The back-end transistor 130B is either not in contact with any adjacent electrode or is isolated from any adjacent electrode. The back-end transistor includes a gate region, a gate dielectric region, and an active semiconductor region made of IGZO or other suitable semiconductor materials. In operation, the back-end transistor is selectively turned on or off to adjust or change the capacitance of the deep trench capacitor structure CapB3. Specifically, the back-end transistor 130B is functionally used to effectively turn on and off the conductive path (from the voltage source applied to the deep trench capacitor device contact C1 to the electrode / electrode layer E1 within the trench 310B1), wherein the switched electrode E1 is operatively associated with the dielectric layer (for storing a portion of the charge capacitance of this device). In other words, by switching the downstream process transistor 130B on and off, the capacitance of the underlying deep trench capacitor structure CapB3 can be calibrated or adjusted, wherein the downstream process transistor 130C on provides a relatively high capacitance, while the downstream process transistor 130C off provides a relatively low capacitance.

[0076] The patterned metallization or metal layer M1 251 is patterned and formed to provide a metallized connection electrical interface on both sides, connect the deep trench capacitors CapA3 and CapB3 structures to an external circuit, and provide the necessary interconnection of multiple electrodes for the desired operation of these deep trench capacitors, such as selectively connecting multiple deep trench capacitor structures.

[0077] During the deep trench capacitor trench fabrication process, multiple etch stop layers 304A, 304B, 304C, 304D, 304E, and 304F are used to provide the necessary etch stop functionality to fabricate the various deep trench capacitor structural layers and features described and shown in Figure 3A, including but not limited to multiple intermetallic dielectric regions 306A1, 306A2, 306A3, 306B1, 306B2, and 306B3. A passivation layer (not shown) is formed throughout the deep trench capacitor structure to protect it from the surrounding environment.

[0078] Referring to Figure 3B, a cross-sectional view of an integrated circuit (IC) structure (embodiment 3B) 3001B is shown, including a 3D-type adjustable stacked structure for a deep trench capacitor (DTC) structure according to an exemplary embodiment of the present disclosure. This embodiment includes a plurality of discrete deep trench capacitor structures CapA3(1), CapA3(2), and CapB3, each of which includes a stepped metal-insulator-metal (MIM) electrode interface 402 extending into an intermetallic dielectric region. Each of the CapA3(1) and CapA3(2) deep trench capacitor structures has a trench extending only within a first substrate, and the CapB3 deep trench capacitor structure has a trench extending only within a second substrate. The deep trench capacitor structure CapB3 is adjustable to be operatively / selectively connected to one of the plurality of electrodes of the deep trench capacitor structure CapB3 to increase the capacitance of the structure.

[0079] As previously described with reference to Figure 3A, the deep trench capacitor structure CapB3 can be calibrated via transistor 130B, which is operatively / selectively connected to electrode E1 of the deep trench capacitor structure CapB3 to increase the capacitance of this structure, and wafer DTC(W / D)1 and wafer DTC(W / D)2 are bonded at or near the bonding boundary BB by bonding multiple pairs of contact holes (contact holes 340A1, 340B; 340A2, 340B2; 340A3, 340B3; 340A4, 340B4; 340A5, 340B5; and 340A6, 340B6). As shown in Figure 3B, this embodiment may include N deep trench capacitor structures, wherein the N+1th and N-1th deep trench capacitor structures or dies are formed on wafer DTC(W / D)1 adjacent to deep trench capacitor structures CapA3(1) and / or CapA3(2), where N = 1, 2, ... N. Further, this embodiment may include M deep trench capacitor structures, wherein the M+1th and M-1th deep trench capacitor structures or dies are formed on wafer DTC(W / D)2 adjacent to deep trench capacitor structure CapB3, where M = 1, 2, ... M.

[0080] For further details regarding implementation method 3B 3001B, please refer to Figure 3A and its associated detailed description, which depict the same deep trench capacitor structures CapA3 and CapB3.

[0081] The patterned metallization or metal layer M1 251 is patterned and formed to provide a metallization connection electrical interface on both sides, and connects the deep trench capacitors CapA3(1) and CapA3(2) and CapB3 structure to an external circuit, and provides the necessary interconnection of multiple electrodes for the desired operation of the deep trench capacitors, such as selectively connecting multiple deep trench capacitor structures.

[0082] During the deep trench capacitor trench fabrication process, etch stop layers 304A, 304B, 304C, 304D, 304E, and 304F are used to provide the necessary etch stop functionality to fabricate the various deep trench capacitor structural layers and features described and shown in Figure 3A, including but not limited to multiple intermetallic dielectric regions 306A1, 306A2, 306A3, 306B1, 306B2, and 306B3. A passivation layer (not shown) is formed throughout the deep trench capacitor structure to protect it from the surrounding environment.

[0083] Referring to Figure 3C, a cross-sectional view of an integrated circuit (IC) structure (embodiment 3C) 3001C according to an exemplary embodiment of this disclosure is shown. This IC structure includes a 3D-type adjustable stacked structure for a deep trench capacitor (DTC) structure. This embodiment includes a plurality of discrete deep trench capacitor structures CapA3(1), CapA3(2), CapB3(1), and CapB3(2), each of which includes a planar electrode contact interface 401, wherein CapA3(1) and CapA3(2) are deep trench capacitor structures. Each of the deep trench capacitor structures has a trench extending only within the first substrate 302A. The deep trench capacitor structures CapB3(1) and CapB3(2) have a trench extending only within the second substrate 302B. The deep trench capacitor structure CapB3(1) can be operatively / selectively connected to one of the multiple electrodes of the deep trench capacitor structure CapA3(1) to increase the capacitance of this structure. The deep trench capacitor structure CapB3(2) can be operatively / selectively connected to one of the multiple electrodes of the deep trench capacitor structure CapA3(2) to increase the capacitance of this structure.

[0084] The deep trench capacitor structure CapB3(2) can be calibrated via transistor 130B, which is operatively / selectively connected to electrode E1 of the deep trench capacitor structure CapB3 to increase the capacitance of the structure, and wafer DTC(W / D)1 and wafer DTC(W / D)2 are bonded at or near the bonding boundary BB by bonding multiple pairs of contact holes (contact holes 340A1, 340B1; 340A2, 340B2; 340A3, 340B3; and 340A4, 340B4 for each of the deep trench capacitor structures CapA3(1), CapA3(2), CapB3(1) and CapB3(2)). As shown in Figure 3C, this embodiment may include N deep trench capacitor structures, wherein the N+1th and N-1th deep trench capacitor structures or dies are formed on wafer DTC(W / D)1 adjacent to deep trench capacitor structures CapA3(1) and / or CapA3(2), where N = 1, 2, ... N. Further, this embodiment may include M deep trench capacitor structures, wherein the M+1th and M-1th deep trench capacitor structures or dies are formed on wafer DTC(W / D)2 adjacent to deep trench capacitor structures CapB3(1) and / or CapB3(2), where M = 1, 2, ... M.

[0085] More specifically, the disclosed structure 3001A includes the following.

[0086] The first deep trench capacitor structure CapA3(1) includes a trench 310A1 and a pad 120 formed in a substrate 302A. The capacitive function of the deep trench capacitor structure CapA3(1) is provided by alternating layers of electrode materials E1, E2, E3 and E4 and high dielectric constant (HK) dielectric material (not referred to by reference numerals in Figure 3A for clarity), which surround a core material of filling dielectric 126 of the trench 310A1. In operation, in order to store charge within the multiple high dielectric constant dielectric layers of the trench 310A1, a voltage is applied to one or more of the multiple electrodes E1 to E4 through multiple electrical contacts (e.g., multiple contact holes 340A1, 340A2, 340A3 and 340A4, respectively).

[0087] During the manufacturing process, trench 310A1 is etched to a total depth TDA, wherein the trench depth TDA is entirely within the substrate 302A. A planar electrode contact interface structure 401 is formed on the substrate 302A to provide the necessary electrode connections to multiple contacts 340A1, 340A2, 340A3 and 340A4 and multiple contacts C1 to C4.

[0088] The second deep trench capacitor structure CapA3(2) includes a trench 310A2, with a pad 120 formed in a substrate 302A. The capacitive function of the deep trench capacitor structure CapA3(2) is provided by alternating layers of electrode materials E1, E2, E3, and E4 and a high dielectric constant (HK) dielectric material (not referred to by reference numerals in Figure 3C for clarity), which surround a core material of the filling dielectric 126 of the trench 310A2. In operation, in order to store charge within the multiple high dielectric constant layers of the trench 310A2, a voltage is applied to one or more of the multiple electrodes E1 to E4 through multiple electrical contacts (e.g., multiple contact holes C1-C4 respectively) and / or through multiple contacts C1 to C4.

[0089] During the manufacturing process, trench 310A2 is etched to a total depth TDA, wherein the trench depth TDA is entirely within the substrate 302A. A planar electrode contact interface structure 401 is formed on the substrate 302A to provide the necessary electrode connections to a plurality of contacts 340A1, 340A2, 340A3 and 340A4 and a plurality of contacts C1 to C4.

[0090] The third deep trench capacitor structure CapB3(1) includes a trench 310B1 and a pad 120 formed in a substrate 302B. The capacitive function of the deep trench capacitor structure CapB3(1) is provided by alternating layers of electrode materials E1, E2, E3 and E4 and high dielectric constant (HK) dielectric material (not referred to by reference numerals in Figure 3C for clarity), which surround a core material of filling dielectric 126 of the trench 310B1. In operation, in order to store charge within the multiple high dielectric constant layers of the trench 310B1, a voltage is applied to one or more of the multiple electrodes E1 to E4 through multiple electrical contacts (e.g., multiple contact holes 340B1, 340B2, 340B3 and 340B4, respectively) and / or multiple contacts C1 to C4.

[0091] During the manufacturing process, trench 310B1 is etched to a total depth TDA, wherein the trench depth TDA is entirely within the substrate 302B. A planar electrode contact interface structure 401 is formed on the substrate 302B to provide the necessary electrode connections to a plurality of contacts 340B1, 340B2, 340B3 and 340B4, and a plurality of contacts C1 to C4.

[0092] The fourth deep trench capacitor structure CapB3(2) includes a trench 310B2 and a pad 120 formed in a substrate 302B. The capacitive function of the deep trench capacitor structure CapB3(2) is provided by alternating layers of electrode materials E1, E2, E3 and E4 and high dielectric constant (HK) dielectric material (not referred to by reference numerals in Figure 3C for clarity), which surround a core material of filling dielectric 126 of the trench 310B2. In operation, in order to store charge within the multiple high dielectric constant layers of the trench 310B2, a voltage is applied to one or more of the multiple electrodes E1 to E4 through multiple electrical contacts (e.g., multiple contact holes 340B1, 340B2, 340B3 and 340B4, respectively) and / or multiple electrical contacts C1 to C4.

[0093] During the manufacturing process, trench 310B2 is etched to a total depth TDA, wherein the trench depth TDA is entirely within the substrate 302B. A planar electrode contact interface structure 401 is formed on the substrate 302B to provide the necessary electrode connections to the multiple contacts 340B1, 340B2, 340B3 and 340B4, and the multiple contacts C1 to C4.

[0094] The patterned metallization or metal layer M1 251 is patterned and formed to provide a metallized connection electrical interface on both sides, and connects the deep trench capacitors CapA3(1) and CapA3(2) and CapB3(1) and CapB3(2) structures to an external circuit, and provides necessary interconnection of multiple electrodes for the required operation of the deep trench capacitors, such as selectively connecting multiple deep trench capacitor structures.

[0095] During the deep trench capacitor trench fabrication process, etch stop layers 304A, 304B, 304C, 304D, 304E, and 304F are used to provide the necessary etch stop functionality to fabricate the various deep trench capacitor structural layers and features described and shown in Figure 3B, including but not limited to multiple intermetallic dielectric regions 306A1, 306A2, 306A3, 306B1, 306B2, and 306B3. A passivation layer (not shown) is formed throughout the deep trench capacitor structure to protect it from the surrounding environment.

[0096] According to some example implementations, and with reference to multiple implementations 1A, 1B, 1C, 2A, 2B, 3A, 3B and 3C, the thicknesses of the electrodes, high dielectric constant capacitor dielectric, filling dielectric material, etch stop layer and trench pad can vary from about 1 angstrom (A) to 10 micrometers (μm).

[0097] According to some example embodiments, and with reference to multiple embodiments 1A, 1B, 1C, 2A, 2B, 3A, 3B, and 3C, the thickness of the intermetallic dielectric layer can vary from approximately 1 angstrom to approximately 1 millimeter (mm); the thickness of the back-end process transistor can vary from approximately 1 angstrom to approximately 1 micrometer; the trench depth (i.e., TDA, TDB, and TDC) ranges from approximately 1 nanometer to approximately 500 micrometers; and the size of the contact holes ranges from approximately 1 nanometer to approximately 1 centimeter (cm). Furthermore, by aligning these contact holes and using a thermocompression bonding process, and with adjustable hole sizes, alignment accuracy can be improved.

[0098] According to the example embodiments, multiple embodiments 1A, 1B, 1C, 2A, 2B, 3A, 3B, and 3C are formed on one or more wafers made of semiconductor material, wherein the deep trench capacitor embodiment structure is constructed or formed thereon via relevant semiconductor manufacturing techniques, including but not limited to photolithography, such as applying a photoresist layer, patterning a photoresist layer, developing a photoresist layer, then etching, followed by planarization and cleaning, to apply a pattern / structure in a given layer. While the specific semiconductor manufacturing processes required to form the disclosed embodiments shown and described are not the focus of this disclosure, for completeness, a general description of the semiconductor manufacturing processes is provided below.

[0099] Semiconductor substrate materials may include silicon, such as crystalline silicon or polycrystalline silicon. In alternative embodiments, the substrate may be made of other elemental semiconductors, such as germanium, or may include compound semiconductors such as silicon carbide (SiC), gallium arsenide (GaAs), gallium arsenide, gallium phosphide, indium arsenide (InAs), indium phosphide (InP), silicon germanium, silicon germanium carbide, gallium arsenide, or gallium phosphide indium. In certain embodiments, the wafer substrate is silicon.

[0100] Generally, photoresist layers can be applied via methods such as spin coating or spraying, roll coating, dip coating, or extrusion coating. Typically, in spin coating, the substrate is placed on a rotating platform, which may include vacuum chucks to hold the substrate in place. The photoresist components are then applied to the central region of the substrate. The speed of the rotating platform is then increased to uniformly diffuse the resist from the central region of the substrate to the periphery. The rotation speed of the platform is then fixed, which controls the final thickness of the photoresist layer.

[0101] Next, the photoresist components are baked or cured to remove the solvent and harden the photoresist layer. In some specific embodiments, baking is performed at a temperature of about 90°C to about 110°C. Baking can be performed using a heating plate, oven, or similar equipment. As a result, a photoresist layer is formed on the substrate.

[0102] The photoresist layer is then patterned by exposure to radiation. The radiation can be any wavelength of light carrying the desired photomask pattern. In several specific embodiments, extreme ultraviolet (EUV) light with a wavelength of about 13.5 nanometers (nm) is used for patterning because such light allows for smaller feature sizes. This results in some portions of the photoresist layer being exposed to radiation, while other portions remain unexposed. This exposure causes some portions of the photoresist to become soluble in the developer, while other portions remain insoluble.

[0103] Following exposure to radiation, an additional photoresist baking step (post-exposure bake, PEB) may be performed. For example, this may help release acid leaving groups (ALGs) or other important molecules in the chemically amplified photoresist.

[0104] The photoresist layer is then developed using a developer. The developer can be an aqueous solution or an organic solvent. During the development step, the soluble portion of the photoresist layer is dissolved and washed away, leaving the photoresist pattern. A typical example of a developer is aqueous tetramethylammonium hydroxide (TMAH). Other developers may include 2-heptanone, ethyl butyrate, ethyl isovalerate, cyclohexanone, 5-methyl-2-hexanone, methyl-2-hydroxyisobutyrate, ethyl lactate, or propylene glycol monomethyl ether acetate, ethyl valerate, propyl butyrate, ethyl hexanoate, butyl butyrate, butyl isobutyrate, 2,5-dimethyl-4-hexanone, 2,6-dimethyl-4-heptanone, propyl isobutyrate, or propyl isobutyrate. Generally, any suitable developer can be used. Sometimes, a post-development baking or "hard baking" may be performed to stabilize the photoresist pattern after development for optimal performance in subsequent steps.

[0105] Next, several portions of the layer beneath the patterned photoresist layer are now exposed. Etching transfers the photoresist pattern to the layer beneath the patterned photoresist layer. After use, the patterned photoresist layer is removed, for example using various solvents such as N-methyl-pyrrolidone (NMP) or alkaline media, or using other stripping agents at high temperatures, or via dry etching using oxygen plasma.

[0106] Generally, any etching steps used in this article can be performed using wet etching, dry etching, or plasma etching processes, such as reactive ion etching (RIE) or inductively coupled plasma (ICP) or combinations thereof, as appropriate. Etching can be anisotropic. Depending on the material, etchants may include carbon tetrafluoride (CF4), hexafluoroethane (C2F6), octafluoropropane (C3F8), fluoroform (CHF3), difluoromethane (CH2F2), fluoromethane (CH3F), trifluoromethane (CHF3), fluorocarbons, nitrogen (N2), hydrogen (H2), oxygen (O2), argon (Ar), xenon (Xe), xenon difluoride (XeF2), helium (He), carbon monoxide (CO), carbon dioxide (CO2), fluorine (F2), chlorine (Cl2), oxygen (O2), hydrogen bromide (HBr), hydrogen fluoride (HF), nitrogen trifluoride (NF3), sulfur hexafluoride (SF6), boron trichloride (BCl3), ammonia (NH3), bromine (Br2), nitrogen trifluoride (NF3), or similar substances, or combinations thereof in various proportions. For example, silicon dioxide can be wet-etched using hydrofluoric acid and ammonium fluoride. Alternatively, silicon dioxide can be dry-etched using mixtures of various CHF3, O2, CF4 and / or H2.

[0107] Planarization can be performed to obtain a flat surface. For example, a chemical mechanical polishing (CMP) process can be used to perform planarization. Generally, CMP is performed using a rotating stage with polishing pads attached. The substrate is attached to a rotating carrier. A slurry or solution containing various chemicals and abrasives is dispensed onto the polishing pads or wafer substrate. During polishing, both the polishing pads and the carrier rotate, which causes mechanical and chemical effects on the surface of the wafer substrate and / or its top layers, removing unwanted material and producing a highly flat surface. A post-CMP cleaning step is then performed, using a rotating brush and cleaning solution to clean one or both sides of the wafer substrate.

[0108] Finally, a cleaning step, such as wet cleaning, can be performed between the various process steps. The cleaning solution will depend on the etching formulation and the exposed layers. Examples of cleaning solutions may include deionized water, diluted HF, and other relevant solutions.

[0109] The dielectric structure or dielectric layer of the disclosed device can be made of any suitable combination of various dielectric materials. Various embodiments of the dielectric materials may include silicon dioxide (SiO2), silicon nitride (Si3N4), silicon carbide (SiC), hafnium dioxide (HfO2), zirconium dioxide (ZrO2), aluminum oxide (Al2O3), silicon oxynitride (SiOxNy), hafnium oxynitride (HfOxNy) or zirconium oxynitride (ZrOxNy), hafnium silicate (ZrSixOy) or zirconium silicate (ZrSixOy) or silicon carboxyl nitride (SiCxOyNz), or hexagonal boron nitride (hBN). Other dielectric materials may include tantalum oxide (Ta2O5), nitrides such as silicon nitride, polycrystalline silicon, phosphosilicate glass (PSG), fluorosilicate glass (FSG), undoped silicate glass (USG), high-stress undoped silicate glass (HSUSG), and high-stress undoped silicate glass (BSG).

[0110] Any conductive material discussed herein can generally be any conductive metal or conductive oxide. Examples of suitable metals may include copper, aluminum, nickel, chromium, gold, germanium, silver, titanium, tungsten, platinum, tantalum, ruthenium, cobalt, rhodium, palladium, or zirconium; composite materials such as TiN, WN, or TaN; or alloys thereof, such as AlCu. Examples of suitable conductive oxides may include indium tin oxide (ITO), zinc oxide (ZnO), tin oxide (SnO), zinc aluminum oxide (AlZnO), indium oxide (InO), or cadmium oxide (CdO). The deposited metal or oxide material may be deposited, for example, via evaporation or sputtering, electroplating, chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or other suitable methods.

[0111] Referring to Figures 4A to 4N, various manufacturing stages associated with the manufacture of an integrated circuit structure (Embodiment 1A) according to an exemplary embodiment of this disclosure are illustrated.

[0112] Figure 4A shows a pad layer 120, an etch stop layer 104A, and an intermetallic dielectric layer 106A formed on a substrate 102.

[0113] Figure 4B shows the stage from etching trench 110C to depositing trench liner 120 at trench depth TDC1 within trench 110C.

[0114] Figure 4C shows the stages of deposited electrodes E1C, E2C, E3C, and E4C, and high dielectric constant (high K) dielectric material layers / regions HK1C, HK2C, HK3C, and HK4C. Filler dielectric material 126 is deposited on the structure providing the dielectric core of trenches 110C.

[0115] Figure 4D illustrates the stages of removing a portion of the dielectric filler material 126, grinding the longitudinal ends of electrodes E1C to E4C, and forming a back-to-line (BEOL) transistor 130C (e.g., a thin-film transistor (TFT)) on a single longitudinal end of an electrode.

[0116] Figure 4E illustrates the next stage of depositing additional intermetallic dielectric material 106A on the deep trench capacitor structure.

[0117] Figure 4F shows the next stage of the deposition of the etch stop layer 104B and the subsequent deposition of the additional intermetallic dielectric material 106B.

[0118] Figure 4G shows the stages of forming multiple electrical contacts 140C1, 140C2, 140C3 and 140C4 that lead to the trench electrode and the gate of the back-end process transistor 130C, thereby completing the formation of a single deep trench capacitor structure within the substrate 102.

[0119] Figure 4H shows the stages of grinding the top surface, depositing additional intermetallic dielectric material, and etching the second trench 110B to a depth of TDB1 within the substrate 102 and a depth of TDB2 within the dielectric materials 106A and 106B.

[0120] Figure 4I illustrates the stages of forming multiple second trench electrodes E1B, E2B, E3B and E4B, multiple high dielectric constant layers HK1B, HL2B, HK3B and HK4B between these electrodes, and filling the core of the second trench 110B with dielectric filling material 126.

[0121] Figure 4J illustrates the stage of patterning a metallization layer M1 for electrical connection to multiple contacts 140C1, 140C2, 140C3 and 140C4 and forming an etch stop layer 104C.

[0122] Figure 4K illustrates the stages of grinding the etch stop layer 104C, depositing additional intermetallic dielectric material 106C, and forming another etch stop layer 104D.

[0123] Figure 4L illustrates the formation of the back-end process transistor 130B, which forms multiple electrical contacts 140B1, 140B2, 140B3 and 140B4 that connect to the second trench electrodes E1B, E2B, E3B and E4B.

[0124] Figure 4M illustrates the formation of multiple vias V1 160 electrically connected to the patterned metallization layer M1.

[0125] Figure 4N shows the completed structure after forming another patterned metallization layer M (2 to N) electrically connected to the first deep trench capacitor via V1 160 and multiple second deep trench capacitor contacts 140B1, 140B2, 140B3 and 140B4.

[0126] Referring to Figures 5A through 5F, various manufacturing stages associated with the fabrication of an integrated circuit structure (Embodiment 2A) according to an exemplary embodiment of this disclosure are illustrated, including a type 2.5D forming process flow.

[0127] Figure 5A shows a trench liner layer 120 and an intermetallic dielectric layer 206AB formed on a substrate 202AB.

[0128] Figure 5B illustrates the stage of etching the first trench 210A1 and the second trench 210A2 respectively and depositing additional padding material 120 in the trenches.

[0129] Figure 5C shows the stages of progressively depositing multiple electrode layers E1, E2, E3 and E4 and multiple high dielectric constant (high K) dielectric layers HK1, HK2, HK3 and HK4 in both the first trench 210A1 and the second trench 210A2, and depositing filling dielectric material 126 in both the first trench 210A1 and the second trench 210A2.

[0130] After performing these steps as described in Figure 5C, successive photolithography and etching processes are performed to finally complete the stepped structure shown in Figure 5D. Figure 5D illustrates the stages of removing the filled dielectric material 126, depositing an etch stop layer, depositing additional intermetallic dielectric material 206AB, performing a patterned photoresist photolithography process (4 times) to form the electrode stepped structure shown, and forming and polishing these electrode metal contacts 340A1, 340A2, 340A3, 340A4, 340A5, and 340A6.

[0131] Figure 5E illustrates the next stage, including bonding the second deep trench capacitor structure DTC(W / D)2 onto the substrate 202C in a similar manner, wherein the polished metal contacts are bonded to stack the first deep trench capacitor structure (DTC(W / D1)) and the second (DTC(W / D)2) deep trench capacitor structure. Specifically, multiple electrical contact pairs are bonded: contacts 240A1 to 240C1, contacts 240A2 to 240C2, contacts 240A3 to 240C3, contacts 240B1 to 240C4, contacts 240B2 to 240C5, and contacts 240B3 to 240C6.

[0132] Figure 5F illustrates the final stage of the manufacturing process, including grinding the structures to expose the electrode metal contacts of the second deep trench capacitor structure DTC(W / D)2, forming an etch stop layer 204E, depositing additional intermetallic dielectric material 206C3, forming multiple metal contacts C1 to C9 electrically connected to the electrodes of the second deep trench capacitor structure, and performing a patterned deposition process to form a metallized circuit layer M1.

[0133] Referring to Figures 6A through 6D, various manufacturing stages associated with the fabrication of an integrated circuit structure (Embodiment 3A) according to an exemplary embodiment of this disclosure are illustrated, including a 3D-like process flow initially using two identical polished wafers (DTC(W / D)1 and DTC(W / D)2).

[0134] Figure 6A shows two deep trench capacitor wafers, DTC(W / D)1 and DTC(W / D)2, in the initial stage after grinding (only one is shown), including trenches of TDA / B depth. Figures 3A and 3A's description provide further structural details of the structures shown.

[0135] Figure 6B illustrates the bonding of wafers DTC(W / D)1 and DTC(W / D)2 at or near the bonding boundary BB via multiple metal contacts of each of these wafers. Figures 3A and 3B provide further structural details of the illustrated structure.

[0136] Figure 6C shows the stages of grinding this structure to expose multiple electrodes of one of these wafers (DTC(W / D1)), depositing intermetallic dielectric material, forming multiple metal contacts using the formed vias V1 360l leading to multiple electrodes in the top wafer trench, subsequently depositing intermetallic dielectric material and patterned metallization layer circuitry, and a passivation layer. These metal contacts and metallization layer circuitry provide multiple electrical connections on the first side of the resulting three-dimensional stacked structure of the deep trench capacitor. Figures 3A and the description of Figure 3A provide further structural details of the structure shown.

[0137] Similar to Figure 6C, Figure 6D illustrates the stages of grinding this structure to expose multiple electrodes on another wafer DTC(W / D)2, depositing intermetallic dielectric material, using the formed vias V1 360 to form multiple metal contacts leading to the electrodes in the trench of the top wafer DTC(W / D)2, subsequently depositing intermetallic dielectric material and patterned metallization layer circuitry M2 252, and a passivation layer. These metal contacts and metallization layer circuitry provide multiple electrical connections on the second side of the resulting three-dimensional stacked structure of the deep trench capacitor. Figures 3A and 3A's description provide further structural details of the illustrated structure.

[0138] The figures above illustrate an example embodiment where, according to an example embodiment, the process is reduced to a single chemical mechanical polishing (CMP) process by minimizing multiple photolithography and etching processes (as shown in Figures 4A to 4N). As shown in Figures 5A to 5F and Figures 6A to 6D, a three-dimensional structure is formed by using multiple contacts to bond two wafers. The final step includes polishing the back side to achieve circuit connections on both sides, realizing a three-dimensional integrated circuit structure, as shown in Figures 6A to 6D.

[0139] Based on the foregoing discussion, it is evident that this disclosure offers several advantages. However, it should be understood that other embodiments may provide additional advantages, and not all advantages need to be disclosed herein, nor do all embodiments require specific advantages. One advantage is that the disclosed deep trench capacitor structure, apparatus, and method of forming thereof provide an tunable deep trench capacitor structure for integration into various integrated circuits, which in turn improves the performance and manufacturability of high-performance integrated circuits.

[0140] Some further implementation methods are described below.

[0141] In a non-limiting illustrative embodiment, a method for forming a deep trench stacked capacitor structure in a semiconductor substrate includes: forming a first trench in the substrate, the first trench including a first trench bottom and a plurality of sides of the first trench; forming a first group of alternating electrode layers and dielectric layers in the first trench, the first group of alternating layers covering the first trench bottom and the plurality of sides of the first trench, and the first group of alternating layers including a first metal electrode layer, a second metal electrode layer, and a first dielectric layer disposed between the first metal electrode layer and the second metal electrode layer to form a first capacitor, each of the first metal electrode layer and the second metal electrode layer including a first longitudinal end and a second longitudinal end; forming a dielectric-filled region in the central region of the first trench, filling... A dielectric region extends along the longitudinal length of the first trench, and a core dielectric region of the first trench is formed by filling the dielectric region. The core dielectric region is at least partially surrounded by alternating layers of a first group. A thin-film transistor (TFT) structure is formed on the first longitudinal end of the first metal electrode layer. The TFT structure includes a gate region, a dielectric region, and a semiconductor region. The semiconductor region is operatively connected to the first metal electrode layer. The TFT structure is configured to control the conductivity from the TFT gate to the first metal electrode layer by applying a gate voltage to switch the capacitance provided by the first capacitor on and off. A first metal contact is formed on the TFT gate region, and a second metal contact is formed on the first longitudinal end of the second metal electrode.

[0142] In some embodiments, forming the alternating electrode layers and dielectric layers of the first group in the trench further includes: forming a second dielectric layer and a third metal electrode, the second dielectric layer being disposed between the second metal electrode layer and the third metal electrode layer to form a second capacitor having a capacitance greater than that of the first capacitor, the third metal electrode layer including a first longitudinal end and a second longitudinal end; and forming a third metal contact on the first longitudinal end of the third metal electrode.

[0143] In some embodiments, the method further includes: operatively connecting the first metal contact and the second metal contact to an integrated circuit (IC) voltage output, the IC voltage output including a first voltage operatively applied to the first metal contact and a second voltage operatively applied to the second metal contact, the first voltage being greater than the second voltage.

[0144] In some embodiments, the method further includes forming a pad layer in the first trench before forming a first group of alternating electrode layers and dielectric layers in the trench.

[0145] In some embodiments, the method further includes: forming a metallization layer circuit that provides multiple electrical connections to other multiple deep trench capacitor structures operatively connected to the first trench first metal contact and the first trench second metal contact.

[0146] In some embodiments, the method further includes: forming a second trench in the substrate, the second trench including a second trench bottom and a plurality of second trench sides, and the second trench being separated from the first trench via the substrate; forming a second group of alternating electrode layers and dielectric layers in the second trench, the second group of alternating layers covering the second trench bottom and the plurality of second trench sides, and the second group of alternating layers including a first metal electrode layer, a second metal electrode layer, and a first dielectric layer disposed between the first metal electrode layer and the second metal electrode layer, to form a first... A capacitor, each of the first metal electrode layer and the second metal electrode layer includes a first longitudinal end and a second longitudinal end; a filled dielectric region is formed in a central region of the second trench, the filled dielectric region extending along a longitudinal length of the second trench, and the filled dielectric region forms a core dielectric region of the second trench, the core dielectric region being at least partially surrounded by alternating layers of the second group; and a first metal contact is formed on the first longitudinal end of the first metal contact, and a second metal contact is formed on the first longitudinal end of the second metal electrode.

[0147] In some embodiments, the method further includes: forming a metallization layer circuit that electrically connects the first metal contact of the first trench and the first metal contact of the second trench, and electrically connects the second metal contact of the first trench and the second metal contact of the second trench.

[0148] In some embodiments, the first trench has a first trench depth, the second trench has a second trench depth, and the first trench depth is different from the second trench depth.

[0149] In another non-limiting illustrative embodiment, the deep trench capacitor (DTC) structure includes: a semiconductor substrate; a first trench formed in the substrate, the first trench including a first trench bottom and a plurality of first trench sides; a first group of alternating electrode layers and dielectric layers formed in the first trench, the first group of alternating layers covering the first trench bottom and the plurality of first trench sides, and the first group of alternating layers including a first metal electrode layer, a second metal electrode layer, and a first dielectric layer disposed between the first metal electrode layer and the second metal electrode layer to form a first capacitor, each of the first metal electrode layer and the second metal electrode layer including a first longitudinal end and a second longitudinal end; and a filled dielectric region formed in the first trench in the central region of the trench. A dielectric region extends along the longitudinal length of the first trench and fills the dielectric region to form a core dielectric region of the first trench, the core dielectric region being at least partially surrounded by a first group of alternating layers; a thin-film transistor (TFT) structure is formed on a first longitudinal end of a first metal electrode layer, the TFT structure including a gate region, a dielectric region, and a semiconductor region, the semiconductor region being operatively connected to the first metal electrode layer, the TFT structure being configured to control the conductivity from the TFT gate to the first metal electrode layer by applying a gate voltage to switch the capacitance provided by a first capacitor on and off; and a first metal contact is formed on the TFT gate region and a second metal contact is formed on the first longitudinal end of a second metal electrode.

[0150] In some embodiments, the alternating electrode layers and dielectric layers of the first group in the trench further include: a first metal contact and a second metal contact, the first metal contact being formed on the gate region of the thin-film transistor, and the second metal contact being formed on the first longitudinal end of the second metal electrode; a second dielectric layer and a third metal electrode, the second dielectric layer being disposed between the second metal electrode layer and the third metal electrode layer to form a second capacitor having a capacitance greater than that of the first capacitor, the third metal electrode layer including a first longitudinal end and a second longitudinal end; and a third metal contact formed on the first longitudinal end of the third metal electrode.

[0151] In some embodiments, the semiconductor device further includes: operably connecting the first metal contact and the second metal contact to an integrated circuit (IC) voltage output, the IC voltage output including a first voltage operably applied to the first metal contact and a second voltage operably applied to the second metal contact, the first voltage being greater than the second voltage.

[0152] In some embodiments, the semiconductor device further includes: a pad layer formed in the first trench, wherein alternating electrodes and dielectric layers of the first group in the trench are formed on the pad layer.

[0153] In some embodiments, the semiconductor device further includes: a metallization layer circuit providing electrical connections to a plurality of other deep trench capacitor structures operatively connected to the first trench first metal contact and the first trench second metal contact.

[0154] In some embodiments, the semiconductor device further includes: a second trench formed in the substrate, the second trench including a second trench bottom and a plurality of second trench sides, and the second trench being separated from the first trench via the substrate; a second group of alternating electrode layers and dielectric layers formed in the second trench, the second group of alternating layers covering the second trench bottom and the plurality of second trench sides, and the second group of alternating layers including a first metal electrode layer, a second metal electrode layer, and a first dielectric layer disposed between the first metal electrode layer and the second metal electrode layer to form a first capacitor. Each of the first metal electrode layer and the second metal electrode layer includes a first longitudinal end and a second longitudinal end; a filled dielectric region formed in a central region of the second trench, the filled dielectric region extending along a longitudinal length of the second trench and forming a core dielectric region of the second trench, the core dielectric region being at least partially surrounded by the alternating plurality of layers of the second group; and a first metal contact and a second metal contact, the first metal contact being formed on a first longitudinal end of the first metal contact and the second metal contact being formed on a first longitudinal end of the second metal electrode.

[0155] In some embodiments, the semiconductor device further includes: a metallization layer circuit electrically connected to the first trench first metal contact and the second trench first metal contact, and electrically connected to the first trench second metal contact and the second trench second metal contact.

[0156] In some embodiments, the first trench has a first trench depth, the second trench has a second trench depth, and the first trench depth is different from the second trench depth.

[0157] In another non-limiting illustrative embodiment, a method of forming an integrated circuit (IC) including a stacked deep trench capacitor (DTC) structure includes: forming a first deep trench capacitor structure in a first semiconductor substrate, the first deep trench capacitor structure including a plurality of planarized metal contacts electrically connected to a plurality of electrodes within a trench formed in the first substrate, and the plurality of planarized metal contacts extending into an inter-metal region formed on the first semiconductor substrate; and forming a second deep trench capacitor structure in a second semiconductor substrate, the second deep trench capacitor structure including a plurality of planarized metal contacts electrically connected to a plurality of electrodes within a trench formed in the second substrate. A plurality of electrodes and a plurality of planarized metal contacts extend into an intermetallic region formed on a second semiconductor substrate; the first deep trench capacitor structure is bonded to the second deep trench capacitor structure by bonding each of the plurality of planarized metal contacts of the first deep trench capacitor structure to a corresponding of the plurality of planarized metal contacts of the second deep trench capacitor structure, thereby electrically connecting the first deep trench capacitor structure and the second deep trench capacitor structure; and a first integrated circuit interconnect structure is formed, the first integrated circuit interconnect including a plurality of metal contacts electrically connected to a plurality of electrodes within the first deep trench capacitor structure to provide an integrated circuit (IC) including a stacked deep trench capacitor (DTC) structure.

[0158] In some embodiments, the method further includes: forming a first metallization layer circuit that provides multiple electrical connections with other multiple deep trench capacitor structures operatively connected to the first integrated circuit interconnect structure.

[0159] In some embodiments, the method further includes forming a second integrated circuit interconnect structure including a plurality of metal contacts electrically connected to a plurality of electrodes within a second deep trench capacitor structure to provide an integrated circuit (IC) including a stacked deep trench capacitor (DTC) structure.

[0160] In some embodiments, the method further includes: forming a thin-film transistor (TFT) structure on a first longitudinal end of a first metal electrode layer of the first deep trench capacitor structure, the TFT structure including a gate region, a dielectric region and a semiconductor region, the semiconductor region being operatively connected to the first metal electrode layer, the TFT structure being configured to control conductivity from the TFT gate to the first metal electrode layer by applying a gate voltage to switch on and off a capacitance provided by the first capacitor, the first capacitor being provided by alternating electrode layers and dielectric layers in the first deep trench capacitor structure.

[0161] Some embodiments of this disclosure provide a method for manufacturing a semiconductor device, comprising: forming a first trench in a substrate, the first trench including a first trench bottom and a plurality of first trench sides; forming a first group of alternating layers in the first trench including alternating layers of electrodes and dielectric layers, the alternating layers of the first group covering the first trench bottom and the plurality of first trench sides, and the alternating layers of the first group including a first metal electrode layer, a second metal electrode layer, and a first dielectric layer disposed between the first metal electrode layer and the second metal electrode layer to form a first capacitor, each of the first metal electrode layer and the second metal electrode layer including a first longitudinal end and a second longitudinal end; forming a filled dielectric region in a central region of the first trench, the filled dielectric region being formed in the first trench. A dielectric region extends along a longitudinal length of the first trench, and the dielectric region forms a core dielectric region of the first trench, the core dielectric region being at least partially surrounded by alternating layers of the first group; a thin-film transistor structure is formed on the first longitudinal end of the first metal electrode layer, the thin-film transistor structure including a gate region, a dielectric region, and a semiconductor region, the semiconductor region being operatively connected to the first metal electrode layer, the thin-film transistor structure being configured to control the conductivity from the gate region of the thin-film transistor structure to the first metal electrode layer by applying a gate voltage to switch on and off a capacitance provided by the first capacitor; and a first metal contact is formed on the gate region of the thin-film transistor structure, and a second metal contact is formed on the first longitudinal end of the second metal electrode.

[0162] In some embodiments, the method of manufacturing a semiconductor device further includes forming a pad layer in the first trench before forming the alternating plurality of layers of the first group in the first trench.

[0163] In some embodiments, the method of manufacturing a semiconductor device further includes: forming a metallization layer circuit that provides multiple electrical connections to a plurality of other deep trench capacitor structures operatively connected to the first metal contact of the first trench and the second metal contact of the first trench.

[0164] In some embodiments, the method of manufacturing a semiconductor device further includes: forming a second trench in a substrate, the second trench including a second trench bottom and a plurality of second trench sides, and the second trench being separated from the first trench via the substrate; forming a second group of alternating layers in the second trench including alternating layers of electrodes and dielectric layers, the second group of alternating layers covering the second trench bottom and the plurality of second trench sides, and the second group of alternating layers including a first metal electrode layer, a second metal electrode layer, and a first electrode layer disposed between the first metal electrode layer and the second metal electrode layer. A dielectric layer for forming a first capacitor, each of the first metal electrode layer and the second metal electrode layer including a first longitudinal end and a second longitudinal end; a filled dielectric region is formed in a central region of the second trench, the filled dielectric region extending along a longitudinal length of the second trench, and the filled dielectric region forming a core dielectric region of the second trench, the core dielectric region being at least partially surrounded by alternating layers of the second group; and a first metal contact is formed on the first longitudinal end of the first metal contact, and a second metal contact is formed on the first longitudinal end of the second metal electrode.

[0165] In some embodiments, the method of manufacturing a semiconductor device further includes: forming a metallization layer circuit that electrically connects the first metal contact of the first trench and the first metal contact of the second trench, and electrically connects the second metal contact of the first trench and the second metal contact of the second trench.

[0166] Some embodiments of this disclosure provide a semiconductor device comprising: a semiconductor substrate; a first trench formed in the semiconductor substrate, the first trench including a first trench bottom and a plurality of first trench sides; a first group of alternating layers including alternating electrode layers and dielectric layers formed in the first trench, the first group of alternating layers covering the first trench bottom and the plurality of first trench sides, and the first group of alternating layers including a first metal electrode layer, a second metal electrode layer, and a first dielectric layer disposed between the first metal electrode layer and the second metal electrode layer to form a first capacitor, each of the first metal electrode layer and the second metal electrode layer including a first longitudinal end and a second longitudinal end; a filling A dielectric region is formed in the first trench at a central region of the first trench, the filling dielectric region extending along a longitudinal length of the first trench and forming a core dielectric region of the first trench, the core dielectric region being at least partially surrounded by alternating layers of the first group; and a thin-film transistor structure is formed on the first longitudinal end of the first metal electrode layer, the thin-film transistor structure including a gate region, a dielectric region, and a semiconductor region operatively connected to the first metal electrode layer, the thin-film transistor structure being configured to control the conductivity from the gate region of the thin-film transistor structure to the first metal electrode layer by applying a gate voltage to switch on and off a capacitance provided by the first capacitor.

[0167] In some embodiments, in a semiconductor device, the alternating plurality of layers of the first group in the first trench further include: a first metal contact and a second metal contact, the first metal contact being formed on the gate region of the thin-film transistor structure, the second metal contact being formed on the first longitudinal end of the second metal electrode; a second dielectric layer and a third metal electrode, the second dielectric layer being disposed between the second metal electrode layer and the third metal electrode layer to form a second capacitor having a capacitance greater than that of the first capacitor, the third metal electrode layer including a first longitudinal end and a second longitudinal end; and a third metal contact being formed on the first longitudinal end of the third metal electrode.

[0168] In some embodiments, the semiconductor device further includes: a pad layer formed in the first trench, wherein alternating plurality of layers of the first group in the first trench are formed on the pad layer.

[0169] In some embodiments, the semiconductor device further includes: a metallization layer circuit providing electrical connections to a plurality of other deep trench capacitor structures operatively connected to a first metal contact of the first trench and a second metal contact of the first trench.

[0170] In some embodiments, the semiconductor device further includes: a second trench formed in the semiconductor substrate, the second trench including a second trench bottom and a plurality of second trench sides, and the second trench being separated from the first trench via the semiconductor substrate; a second group of alternating layers, including alternating electrode layers and dielectric layers, formed in the second trench, the second group of alternating layers covering the second trench bottom and the plurality of second trench sides, and the second group of alternating layers including a first metal electrode layer, a second metal electrode layer, and a first dielectric layer disposed between the first metal electrode layer and the second metal electrode layer, so as to... A first capacitor is formed, each of the first metal electrode layer and the second metal electrode layer including a first longitudinal end and a second longitudinal end; a filled dielectric region is formed in the second trench in a central region of the second trench, the filled dielectric region extending along a longitudinal length of the second trench and forming a core dielectric region of the second trench, the core dielectric region being at least partially surrounded by the alternating plurality of layers of the second group; and a first metal contact and a second metal contact are formed on a first longitudinal end of the first metal contact and the second metal contact is formed on a first longitudinal end of the second metal electrode.

[0171] In some embodiments, the semiconductor device further includes: a metallization layer circuit electrically connecting the first metal contact of the first trench and the first metal contact of the second trench, and electrically connecting the second metal contact of the first trench and the second metal contact of the second trench.

[0172] Some embodiments of this disclosure provide a method of manufacturing a semiconductor device, comprising: forming a first deep trench capacitor structure in a first semiconductor substrate, the first deep trench capacitor structure including a plurality of planarized metal contacts electrically connected to a plurality of electrodes within a trench formed in the first semiconductor substrate, and the plurality of planarized metal contacts extending into an intermetallic region formed on the first semiconductor substrate; and forming a second deep trench capacitor structure in a second semiconductor substrate, the second deep trench capacitor structure including a plurality of planarized metal contacts electrically connected to a plurality of electrodes within a trench formed in the second semiconductor substrate, and the plurality of planarized metal contacts extending into an intermetallic region formed on the first semiconductor substrate; and forming a second deep trench capacitor structure in a second semiconductor substrate, the second deep trench capacitor structure including a plurality of planarized metal contacts electrically connected to a plurality of electrodes within a trench formed in the second semiconductor substrate, and the plurality of planarized metal contacts extending into an intermetallic region formed in the first semiconductor substrate. Metal contacts extend into an intermetallic region formed on the second semiconductor substrate; the first deep trench capacitor structure is bonded to the second deep trench capacitor structure by bonding each of the plurality of planarized metal contacts of the first deep trench capacitor structure to a corresponding one of the plurality of planarized metal contacts of the second deep trench capacitor structure, thereby electrically connecting the first deep trench capacitor structure and the second deep trench capacitor structure; and a first integrated circuit interconnect structure is formed, the first integrated circuit interconnect structure including a plurality of metal contacts electrically connected to the plurality of electrodes within the first deep trench capacitor structure to provide an integrated circuit (IC) including a stacked deep trench capacitor (DTC) structure.

[0173] In some embodiments, the method of manufacturing a semiconductor device further includes: forming a thin-film transistor structure on a first longitudinal end of a first metal electrode layer of the first deep trench capacitor structure, the thin-film transistor structure including a gate region, a dielectric region and a semiconductor region, the semiconductor region being operatively connected to the first metal electrode layer, the thin-film transistor structure being configured to control a conductivity from the gate region of the thin-film transistor structure to the first metal electrode layer, by applying a gate voltage to switch on and off a capacitance provided by a first capacitor provided by alternating plurality of electrode layers and plurality of dielectric layers in the first deep trench capacitor structure.

[0174] The foregoing outlines several features of various embodiments to enable those skilled in the art to better understand the multiple variations of this disclosure. Those skilled in the art will understand that they can readily use this disclosure as a basis for the design or modification of other processes and structures to achieve the same objectives and / or advantages as the embodiments described herein. Those skilled in the art will also understand that equivalent constructions do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and modifications can be made without departing from the spirit and scope of this disclosure.

[0175] 1001A: Implementation Method (Structure, Implementation Method 1A) 1001B: Implementation Method 1B 1001C: Implementation Method 1C 102:Substrate 104A, 104B, 104C, 104D, 104E: Etching stop layers 106A: Intermetallic dielectric region (intermetallic dielectric layer, intermetallic dielectric material, dielectric material, region) 106B: Intermetallic dielectric region (intermetallic dielectric layer, intermetallic dielectric, intermetallic dielectric material, dielectric material, region) 106C: Intermetallic dielectric region (intermetallic dielectric materials) 106D: Intermetallic dielectric region 106E: Intermetallic dielectric region 110A, 110B, 110C: Trench 120: Padding (Padding layer, padding material) 126: Filled dielectric (filled dielectric material, dielectric filler material, filled dielectric material) 130B: Back-end process transistor (adjustable device, transistor) 130C: Back-end process transistor (transistor) 131B: Gate Region 131C: Gate Region 132B: Gate dielectric region 132C: Gate dielectric region 133B: Active Semiconductor Region 133C: Active semiconductor region 140A1, 140A2, 140A3, 140A4, 140B1, 140B2, 140B3, 140B4, 140C1, 140C2, 140C3, 140C4: Contact holes, contacts 151: Metal layer M1 (metal layer) 152: Metal layer M2 (Metal layer M2(2 to N)) 160: Guide hole V1 180: Passivation layer 2: Low voltage potential connection / source (low voltage) 2001A: Implementation Method 2A 2001B: Structure 202AB: Substrate (First Substrate) 202C:Substrate 204A: Etching Stop Layer 204A(1): Etching stop layer 204A(2): Etching stop layer 204B, 204C, 204D, 204E: Etching stop layers 206AB: Intermetallic dielectric region (intermetallic dielectric layer, intermetallic dielectric material) 206AB1: Intermetallic dielectric region 206AB2: Intermetallic dielectric region 206C1: Intermetallic dielectric region 206C2: Intermetallic dielectric region 206C3: Intermetallic dielectric region (intermetallic dielectric material) 210A: Trench 210A1: First trench (groove) 210A2: Second trench (groove) 210B, 210B1, 210B2, 210C, 210C1, 210C2: Trench 240A1, 240A2, 240A3, 240B1, 240B2, 240B3, 240C1, 240C2, 240C3, 240C4, 240C5, 240C6: Contact holes (contacts) 251: Metal layer M1 (circuit) 252: Metallization layer circuit M2 3001A: Implementation Method 3A (Structure) 3001B: Implementation Method 3B (Structure) 3001C: Implementation Method 3C (Structure) 302A: First substrate (substrate) 302B: Second substrate (substrate) 304A, 304B, 304C, 304D, 304E, 304F: Etching stop layers 306A1, 306A2, 306A3, 306B1, 306B2, 306B3: Intermetallic dielectric region 310A1: Trench 310A2: Trench 310B1: Trench 310B2: Trench 340A: Contact hole 340A1, 340A2, 340A3, 340A4, 340A5, 340A6: Contact holes (contacts) 340B, 340B1, 340B2, 340B3, 340B, 340B5, 340B6: Contact holes (contacts) 360: Guide Hole V1 4: High-voltage potential connection / source (high voltage) 401: Interconnect structure (electrode contact interface structure, electrode contact interface) 402: Electrode contact interface structure (electrode contact interface, electrode interface) BB: Joint boundary C1, C2, C3, C4, C5, C6, C7, C8, C9, C10, C11, C12: Contact holes (contacts) CA1: Capacitor CA2: Capacitor CA3: Capacitor CapA1, CapA2, CapA3, CapA3(1), CapA3(2), CapB1, CapB2, CapB3, CapB3(1), CapB3(2), CapC1, CapC2: Deep trench capacitor structure (deep trench capacitor) DTC(W / D)1: Wafer (Grain) DTC(W / D)2: Wafer (Grain) E1, E1A, E1B, E1C, E2, E2A, E2B, E2C, E3, E3A, E3B, E3C, E4, E4A, E4B, E4C, E5, E6, E7, E8, E9, E10, E11, E12: Electrode materials (electrodes, electrode layers) Hi-Volt: High Voltage HK1A, HK1B, HK1C, HK2A, HK2B, HK2C, HK3A, HK3B, HK3C, HK4A, HK4B, HK4C: High dielectric constant dielectric materials (high dielectric constant dielectric layer, high dielectric constant layer, region) IMD: Intermetallic Dielectric Lo-Volt: Low voltage M1: Metal layer M2: Metal layer M2(2~N): Metal layer TDA, TDA1, TDA2: Trench depth (depth) TDA / B: Depth TDB, TDB1, TDB2: Trench depth (depth) TDC, TDC1, TDC2: Trench depth (depth) V1: Guide hole X, Y, Z: Direction

[0176] Domestic storage information (please note in order of storage institution, date, and number) none Overseas storage information (please note in the order of storage country, institution, date, and number) none

Claims

1. A method of manufacturing a semiconductor device, comprising: forming a first trench in a substrate, the first trench including a first trench bottom and a plurality of first trench sides; forming a first group of alternating layers in the first trench including alternating layers of electrodes and dielectric layers, the first group of alternating layers covering the first trench bottom and the plurality of first trench sides, and the first group of alternating layers including a first metal electrode layer, a second metal electrode layer, and a first dielectric layer disposed between the first metal electrode layer and the second metal electrode layer to form a first capacitor, each of the first metal electrode layer and the second metal electrode layer including a first longitudinal end and a second longitudinal end; forming a filled dielectric region in a central region of the first trench, the filled dielectric region extending along a longitudinal length of the first trench, and the filled dielectric region forming a core dielectric region of the first trench, the core dielectric region being at least partially surrounded by the first group of alternating layers; A thin-film transistor structure is formed on the first longitudinal end of the first metal electrode layer. The thin-film transistor structure includes a gate region, a dielectric region, and a semiconductor region. The semiconductor region is operatively connected to the first metal electrode layer. The thin-film transistor structure is configured to control the conductivity from the gate region of the thin-film transistor structure to the first metal electrode layer by applying a gate voltage to switch on and off a capacitance provided by the first capacitor. A first metal contact is formed on the gate region of the thin-film transistor structure, and a second metal contact is formed on the first longitudinal end of the second metal electrode.

2. The method of manufacturing a semiconductor device as claimed in claim 1, wherein forming the alternating plurality of layers of the first group in the first trench further comprises: forming a second dielectric layer and a third metal electrode, the second dielectric layer being disposed between the second metal electrode layer and the third metal electrode layer to form a second capacitor having a capacitance greater than that of the first capacitor, the third metal electrode layer including a first longitudinal end and a second longitudinal end; and forming a third metal contact on the first longitudinal end of the third metal electrode.

3. The method of manufacturing a semiconductor device as claimed in claim 1, further comprising: operably connecting the first metal contact and the second metal contact to an integrated circuit (IC) voltage output, the IC voltage output including a first voltage operably applied to the first metal contact and a second voltage operably applied to the second metal contact, the first voltage being greater than the second voltage.

4. The method of manufacturing a semiconductor device as claimed in claim 1, further comprising: forming a pad layer in the first trench before forming the alternating plurality of layers of the first group in the first trench.

5. A semiconductor device comprising: a semiconductor substrate; a first trench formed in the semiconductor substrate, the first trench including a first trench bottom and a plurality of first trench sides; a first group of alternating layers including alternating electrode layers and a plurality of dielectric layers formed in the first trench, the first group of alternating layers covering the first trench bottom and the plurality of first trench sides, and the first group of alternating layers including a first metal electrode layer, a second metal electrode layer, and a first dielectric layer disposed between the first metal electrode layer and the second metal electrode layer to form a first capacitor, each of the first metal electrode layer and the second metal electrode layer including a first longitudinal end and a second longitudinal end; A filled dielectric region is formed in a central region of the first trench, the filled dielectric region extending along a longitudinal length of the first trench and forming a core dielectric region of the first trench, the core dielectric region being at least partially surrounded by alternating layers of the first group; and a thin-film transistor structure is formed on the first longitudinal end of the first metal electrode layer, the thin-film transistor structure including a gate region, a dielectric region, and a semiconductor region operatively connected to the first metal electrode layer, the thin-film transistor structure being configured to control the conductivity from the gate region of the thin-film transistor structure to the first metal electrode layer by applying a gate voltage to switch on and off a capacitance provided by the first capacitor.

6. The semiconductor device of claim 5, further comprising: a second trench formed in the semiconductor substrate, the second trench including a second trench bottom and a plurality of second trench sides, and the second trench being separated from the first trench via the semiconductor substrate; a second group of alternating layers including alternating electrode layers and dielectric layers formed in the second trench, the second group of alternating layers covering the second trench bottom and the plurality of second trench sides, and the second group of alternating layers including a first metal electrode layer, a second metal electrode layer, and a first dielectric layer disposed between the first metal electrode layer and the second metal electrode layer to form a first capacitor, each of the first metal electrode layer and the second metal electrode layer including a first longitudinal end and a second longitudinal end; A filled dielectric region is formed in a central region of the second trench, the filled dielectric region extending along a longitudinal length of the second trench and forming a core dielectric region of the second trench, the core dielectric region being at least partially surrounded by alternating layers of the second group; and a first metal contact and a second metal contact, the first metal contact being formed at a first longitudinal end of the first metal contact and the second metal contact being formed at a first longitudinal end of the second metal electrode.

7. The semiconductor device as claimed in claim 6 further includes: a metallization layer circuit electrically connecting the first metal contact of the first trench and the first metal contact of the second trench, and electrically connecting the second metal contact of the first trench and the second metal contact of the second trench.

8. The semiconductor device as described in claim 7, wherein, The first trench has a first trench depth, and the second trench has a second trench depth, the first trench depth being different from the second trench depth.

9. A method of manufacturing a semiconductor device, comprising: forming a first deep trench capacitor structure in a first semiconductor substrate, the first deep trench capacitor structure including a plurality of planarized metal contacts electrically connected to a plurality of electrodes within a trench formed in the first semiconductor substrate, and the plurality of planarized metal contacts extending into an intermetallic region formed on the first semiconductor substrate; and forming a second deep trench capacitor structure in a second semiconductor substrate, the second deep trench capacitor structure including a plurality of planarized metal contacts electrically connected to a plurality of electrodes within a trench formed in the second semiconductor substrate, and the plurality of planarized metal contacts extending into an intermetallic region formed on the second semiconductor substrate; The first deep trench capacitor structure is joined to the second deep trench capacitor structure by joining each of the plurality of planarized metal contacts of the first deep trench capacitor structure to a corresponding one of the plurality of planarized metal contacts of the second deep trench capacitor structure, thereby electrically connecting the first deep trench capacitor structure and the second deep trench capacitor structure; and a first integrated circuit interconnect structure is formed, the first integrated circuit interconnect structure including a plurality of metal contacts electrically connected to the plurality of electrodes within the first deep trench capacitor structure to provide an integrated circuit (IC) including a stacked deep trench capacitor (DTC) structure.

10. The method of manufacturing a semiconductor device as claimed in claim 9, further comprising: forming a first metallization layer circuit that provides multiple electrical connections to a plurality of other deep trench capacitor structures operatively connected to the first integrated circuit interconnect structure.

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