Semiconductor device and methods of formation
TW202636964APending Publication Date: 2026-09-01TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
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Patent Information
- Application Number
- TW114128091
- Authority / Receiving Office
- TW · TW
- Patent Type
- Applications
- Current Assignee / Owner
- Priority Date
- 2025-05-29
- Filing Date
- 2025-07-24
- Publication Date
- 2026-09-01
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Abstract
A slope in the surface of a semiconductor wafer at an edge region of the semiconductor wafer is filled in prior to bonding the semiconductor wafer with another semiconductor wafer to minimize or prevent the likelihood of a gap forming between the edges of the semiconductor wafers. To fill in the slope in the surface of the semiconductor wafer, one or more bonding dielectric layers are formed over the surface of the semiconductor wafer such that a top surface of the top-most bonding dielectric layer in the edge region is at a greater vertical height than a bottom surface of the bottom-most bonding dielectric layer in a non-edge region of the semiconductor wafer. The bonding dielectric layer(s) may then be etched and / or planarized to remove excess material.
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