Semiconductor device

Abstract

A semiconductor device includes a substrate, a channel structure, a shielding structure, and external terminals. The substrate includes a ground area and a signal area. The substrate has a top surface, a bottom surface and a plurality of side surfaces connecting the top surface and the bottom surface. The ground area has a ground pad, and the signal area has a signal pad. The channel structure is electrically connected to the signal pad. The shielding structure is electrically connected to the ground pad and is electrically isolated from the channel structure. The shielding structure has an inner shielding part and an outer shielding part. The inner shielding part is disposed between the channel structure and the top surface, and the outer shielding part is disposed on the bottom surface and the side surfaces. The external terminals are disposed on the channel structure and electrically connected thereto.

Description

Technical Field

[0001] This invention relates to a semiconductor device. Prior Technology

[0002] To prevent electromagnetic interference (EMI) from affecting the stability of integrated circuit chips during use, current packaging technologies often involve first forming a standardized package structure, and then adding an EMI shielding structure (such as a metal casing) outside the package to reduce the EMI experienced by the chip. However, the aforementioned EMI shielding structure has poor shielding effectiveness and poor space utilization. Summary of the Invention

[0003] This invention provides a semiconductor device that maintains good electrical transmission capabilities while having excellent electromagnetic shielding and space utilization.

[0004] A semiconductor device according to the present invention includes a substrate, a channel structure, a shielding structure, and external terminals. The substrate includes a grounding region and a signal region. The substrate has a top surface, a bottom surface, and a plurality of side surfaces connecting the top surface and the bottom surface. The grounding region has a grounding pad, and the signal region has a signal pad. The channel structure is electrically connected to the signal pad. The shielding structure is electrically connected to the grounding pad and electrically isolated from the channel structure. The shielding structure has an inner shielding portion and an outer shielding portion. The inner shielding portion is disposed between the channel structure and the top surface, and the outer shielding portion is disposed on the bottom surface and the plurality of side surfaces. External terminals are disposed on and electrically connected to the channel structure.

[0005] In one embodiment of the present invention, the channel structure described above does not directly contact the grounding pad, and the shielding structure does not directly contact the signal pad.

[0006] In one embodiment of the present invention, the inner shielding portion extends to connect with the outer shielding portion to form an annular structure surrounding the substrate.

[0007] In one embodiment of the present invention, the semiconductor device further includes a first insulating layer and a second insulating layer. In the ground region, the first insulating layer and the second insulating layer cover the inner shielding portion, and in the signal region, the channel structure penetrates the second insulating layer.

[0008] In one embodiment of the present invention, the semiconductor device further includes an outer spherical bottom metal layer disposed between the external terminal and the channel structure.

[0009] In one embodiment of the present invention, the channel structure described above includes an inner spherical bottom metal layer. The inner spherical bottom metal layer is laterally aligned with the inner shielding portion.

[0010] In one embodiment of the present invention, the material of the inner spherical bottom metal layer is the same as that of the inner shielding portion.

[0011] In one embodiment of the present invention, the first edge of the substrate is flush with the second edge of the inner shielding portion.

[0012] In one embodiment of the present invention, the outer shielding portion directly contacts the first edge and the second edge.

[0013] In one embodiment of the present invention, the inner shielding portion between the signal area and the grounding area is sheet-like or grid-like.

[0014] Based on the above, in addition to providing a multi-layered shielding structure design, the semiconductor device of the present invention also has a channel structure that can serve as a signal transmission path. In this way, it can maintain good electrical transmission capability while having excellent electromagnetic shielding effect and space utilization.

[0015] To make the above features and advantages of the present invention more apparent and understandable, specific embodiments are described below in conjunction with the accompanying drawings for detailed explanation. Simple Explanation of the Diagram

[0016] Figure 1A is a top view schematic diagram of a semiconductor device according to an embodiment of the present invention. Figure 1B is a cross-sectional view along line A-A' in Figure 1A. Figure 1C is a cross-sectional view along line B-B' in Figure 1A. Figure 1D is a cross-sectional view along line C-C' in Figure 1A. Figures 1E and 1F are schematic cross-sectional views of semiconductor devices according to some embodiments of the present invention. Figures 2 to 13 are partial top views and partial cross-sectional views of a semiconductor device at different stages of manufacturing according to an embodiment of the present invention, wherein Figure 4 is a cross-sectional view along line A-A' of Figure 3, Figure 5 is a cross-sectional view along line B-B' of Figure 3, Figure 8 is a cross-sectional view along line A-A' of Figure 7, and Figure 9 is a cross-sectional view along line B-B' of Figure 7. Figure 14 is a top view of a semiconductor device according to an embodiment of the present invention, wherein, for clarity, components such as the channel structure, the outer spherical bottom metal layer, and the external terminals are omitted in Figure 14. Implementation

[0017] In the following detailed description, exemplary embodiments disclosing specific details are set forth for illustrative purposes and not for limitation, to provide a thorough understanding of the various principles of the invention. However, it will be apparent to those skilled in the art that the invention can be practiced in other embodiments departing from the specific details disclosed herein, thanks to this disclosure. Furthermore, descriptions of well-known apparatus, methods, and materials may be omitted to avoid obscuring the description of the various principles of the invention.

[0018] The invention is described more fully with reference to the drawings of this embodiment. However, the invention may be embodied in various different forms and should not be limited to the embodiments described herein. The thickness, dimensions, or size of layers or regions in the drawings are enlarged for clarity. The same or similar reference numerals denote the same or similar elements, which will not be described again in the following paragraphs.

[0019] Referring to Figures 1A to 1D, in this embodiment, the semiconductor device 100 includes a substrate 110, a shielding structure 120, a channel structure 130, and an external terminal 140. In the semiconductor device 100, the shielding structure 120 has an inner shielding portion 121 and an outer shielding portion 122. The inner shielding portion 121 is disposed between the channel structure 130 and the top surface 110t of the substrate 110, and the outer shielding portion 122 is disposed on the bottom surface 110b of the substrate 110 and a plurality of side surfaces 110s. The external terminal 140 is disposed on the channel structure 130, wherein the plurality of side surfaces 110s connect the top surface 110t and the bottom surface 110b. With this configuration, the shielding structure 120 is electrically connected to the grounding pad 111 of the grounding area G of the substrate 110 (as shown in FIG1B), the channel structure 130 is electrically connected to the signal pad 112 of the signal area S of the substrate 110, the external terminal 140 is electrically connected to the channel structure 130, and the shielding structure 120 is electrically isolated from the channel structure 130 (as shown in FIG1C).

[0020] Accordingly, the shielding structure 120 can be grounded through the grounding pad 111, and its inner shielding portion 121 effectively utilizes the space inside the semiconductor device 100. On the other hand, the channel structure 130 can transmit the signal received by the signal pad 112 of the substrate 110 to the external terminal 140. In this way, the semiconductor device 100 of this embodiment, through the design of the multi-coverage (such as six-coverage) shielding structure 120 and the channel structure 130 that can serve as a signal transmission path, can maintain good electrical transmission capability while having excellent electromagnetic shielding effect (such as shielding external radiation waves) and space utilization.

[0021] In this embodiment, the semiconductor device 100 further includes a first insulating layer 101 and a second insulating layer 102. As shown in FIG1B, in the grounding area G, the first insulating layer 101 and the second insulating layer 102 cover the inner shielding portion 121 to achieve electrical isolation. As shown in FIG1C, in the signal area S, the channel structure 130 penetrates the second insulating layer 102, so that it can reliably form electrical contact with the signal pad 112, and the second insulating layer 102 can also ensure that the shielding structure 120 and the channel structure 130 are completely separated. It should be noted that the semiconductor device 100 may also have other suitable insulating film layers according to actual product requirements. For example, in order to improve electrical performance, a passivation layer 10 may be further provided on the top surface 110t of the substrate 110, and a third insulating layer 103 may be further provided on the channel structure 130, but the present invention is not limited thereto.

[0022] In some embodiments, the current paths in the semiconductor device 100 are independent to reduce the probability of circuit failure. That is, the channel structure 130 does not directly contact the grounding pad 111, and the shielding structure 120 does not directly contact the signal pad 112, but the present invention is not limited thereto.

[0023] In some embodiments, as shown in FIG1A, the inner shielding portion 121 extends to connect with the outer shielding portion 122 to form an annular structure around the substrate 110, for example, covering a plurality of side surfaces 110s of the substrate 110. In this way, the electromagnetic shielding effect can be further improved, but the present invention is not limited thereto.

[0024] In this embodiment, as shown in FIG1C, the semiconductor device 100 further includes an outer spherical bottom metal layer 150 disposed between the external terminal 140 and the channel structure 130 to provide better electrical performance. On the other hand, as shown in FIG1E, to further improve electrical performance, as in the alternative embodiment of the semiconductor device 100A, an inner spherical bottom metal layer 131 laterally aligned with the inner shield 121 can be included in the channel structure 130. The material of the inner spherical bottom metal layer 131 can be the same as that of the inner shield 121 (e.g., formed in the same process) to simplify the process. However, the present invention is not limited thereto, and the material of the inner spherical bottom metal layer 131 can also be different from that of the inner shield 121. Furthermore, both the outer spherical bottom metal layer 150 and the inner spherical bottom metal layer 131 can be selectively provided. For example, as shown in FIG1F, in another alternative embodiment of the semiconductor device 100B, the outer spherical bottom metal layer and the inner spherical bottom metal layer may not be included. Alternatively, in an embodiment not shown, only the inner spherical bottom metal layer may be formed without forming the outer spherical bottom metal layer.

[0025] The manufacturing process of the semiconductor device 100 described above will be illustrated below. However, it should be noted that the semiconductor device 100 of the present invention is not limited to being manufactured in this manner. Any semiconductor device having a synergistic design of channel structure and shielding structure as described in the present invention is within the scope of protection of the present invention.

[0026] Please refer to Figures 2 to 5. A substrate 110 is provided, comprising multiple wafer units 110a. For clarity, Figures 3 to 12 before the dicing process are enlarged versions of region R (corresponding to the dashed box area) in Figure 2. It is understood that each of the multiple wafer units 110a can have a configuration similar to that in Figures 3 to 12, and the corresponding film layers can extend between adjacent wafer units 110a. Furthermore, the substrate 110 includes a grounding pad 111 and a signal pad 112 located near the top surface 110t. The grounding pad 111 and the signal pad 112 can be made of aluminum, copper, or other suitable conductive materials, such as nickel-gold. In addition, the substrate 110 can be made of silicon wafers or the like, and other suitable semiconductor elements (not shown) can be disposed in the substrate 110 according to the requirements of the wafer type.

[0027] Next, a passivation layer 10, a first insulating layer 101, and an inner shielding portion 121 are sequentially formed on the substrate 110. As shown in FIG3, the inner shielding portion 121 between the signal area S and the ground area G is sheet-like, that is, the internal space 113 surrounded by the ground pad 111 and the signal pad 112 is completely covered by the first insulating layer 101. However, the present invention is not limited to this. For example, as shown in FIG14, the inner shielding portion 121 between the signal area S and the ground area G of the semiconductor device 100C in this alternative embodiment is grid-like, that is, the first insulating layer 101 and the inner shielding portion 121 are arranged in a grid-like alternating pattern in the internal space 113 surrounded by the ground pad 111 and the signal pad 112.

[0028] Referring again to Figures 4 and 5, the grounding area G and signal area S of the substrate 110 can have different configurations. For example, in the grounding area G of Figure 4, the opening 10a of the passivation layer 10 is filled by the first insulating layer 101 and the inner shielding portion 121, and the top surface 111t of the grounding pad 111 is not exposed. In the signal area S of Figure 5, the inner shielding portion 121 has an opening 121a, the first insulating layer 101 has an opening 101a, and the passivation layer 10 has another opening 10b, so that the top surface 112t of the signal pad 112 is exposed. The width of the opening 121a is greater than the width of the opening 101a, and the width of the opening 101a is greater than the width of the opening 10b.

[0029] Please refer to Figure 6. A second insulating layer 102 is formed on the inner shielding portion 121. In this stage, only a portion of the signal pads 112 are exposed within the edge of the second insulating layer 102, while outside the edge of the second insulating layer 102, a portion of the inner shielding portion 121 extends outward on the top surface 110t of the substrate 110.

[0030] Referring to Figures 7 to 9, a channel structure 130 is formed on the second insulating layer 102, wherein the channel structure 130 can be configured differently on the contact area G and the signal area S of the substrate 110. For example, no channel structure 130 is formed on the contact area G in Figure 8, while on the signal area S in Figure 9, the channel structure 130 can be formed on and in direct contact with the signal pad 112 exposed in Figure 6, thereby achieving the desired electrical connection effect.

[0031] Referring to Figure 10, a third insulating layer 103 is formed on the channel structure 130. During this stage, only a portion of the channel structure 130 is exposed within the edge of the third insulating layer 103, allowing signals from the substrate 110 to be transmitted solely through the channel structure 130. It should be noted that the first insulating layer 101, inner shield 121, second insulating layer 102, channel structure 130, and third insulating layer 103 described above can be formed using suitable materials and processes for forming redistribution lines (RDLs), and will not be elaborated further here.

[0032] Referring to Figure 11, an outer spherical bottom metal layer 150 is formed on the third insulating layer 103. The outer spherical bottom metal layer 150 can be disposed corresponding to the exposed channel structure 130 in Figure 10, that is, the outer spherical bottom metal layer 150 completely covers the exposed channel structure 130 in Figure 10. On the other hand, the outer spherical bottom metal layer 150 can further extend to and directly contact the top surface of the third insulating layer 103, but does not extend above the grounding pad 111. In some embodiments, the material of the outer spherical bottom metal layer 150 includes titanium, copper, tungsten, gold, silver, palladium, platinum or combinations thereof, and the outer spherical bottom metal layer 150 is formed, for example, by a sputtering process.

[0033] Referring to Figure 12, an external terminal 140 is formed on the outer spherical bottom metal layer 150, wherein the external terminal 140 is formed only on the outer spherical bottom metal layer 150 and does not contact the third insulating layer 103, but the present invention is not limited thereto. In some embodiments, the external terminal 140 is formed, for example, by means of solder ball printing, ball dropping, or tin-silver electroplating.

[0034] Referring to Figure 13, the structure of Figure 12 is subjected to a dicing process (such as dicing along the dicing path in Figure 2 (not shown)) to form a discrete semiconductor device (the discrete state is represented by a solid outline). After the dicing process, the first edge of the substrate 110 (e.g., the side surface 110s) is aligned with the second edge 121s of the inner shielding portion 121. Next, an outer shielding portion 122 is formed around the aforementioned structure by means of evaporation, sputtering, or spraying, so that the outer shielding portion 122 directly contacts the aforementioned first edge (e.g., the side surface 110s) and the second edge 121s, thus substantially completing the fabrication of the semiconductor device 100 of Figure 1A. Therefore, the semiconductor device 100 of this embodiment is a wafer-level structure, but the present invention is not limited thereto. Here, the dicing process includes, for example, dicing with a rotating blade or a laser beam. Furthermore, the material of the outer shielding part 122 may be the same as or different from that of the inner shielding part 121. In other words, the present invention does not limit the materials of the outer shielding part 122 and the inner shielding part 122. As long as the connection between the two can achieve the grounding function, they are within the protection scope of the present invention.

[0035] In summary, in addition to providing a multi-layered shielding structure design, the semiconductor device of the present invention also has a channel structure that can serve as a signal transmission path. In this way, it can maintain good electrical transmission capabilities while having excellent electromagnetic shielding effect and space utilization.

[0036] Although the present invention has been disclosed above by way of embodiments, it is not intended to limit the present invention. Anyone skilled in the art can make some modifications and refinements without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be determined by the appended claims.

[0037] 10: Passivation layer 10a, 10b, 101a, 121a: Opening 100, 100A, 100B, 100C: Semiconductor devices 101: First insulating layer 102: Second insulating layer 103: Third Insulation Layer 110:Substrate 110a: Chip unit 111: Grounding pad 112: Signal pad 113: Interior Space 110t, 111t, 112t: Top surface 110b: Bottom surface 110s: Side surface (first edge) 120: Shielding structure 121: Inner shielding section 121s: Second Edge 122: External shielding part 130: Channel Structure 131: Inner spherical bottom metal layer 140:External terminal 150: Outer sphere bottom metal layer G: Connecting regions R: Region S: Signal Area

Claims

1. A semiconductor device, comprising: A substrate includes a grounding area and a signal area, wherein the substrate has a top surface, a bottom surface, and a plurality of side surfaces connecting the top surface and the bottom surface, and the grounding area has a grounding pad, and the signal area has a signal pad; a channel structure is electrically connected to the signal pad; A shielding structure electrically connected to the grounding pad and electrically isolated from the channel structure, wherein the shielding structure has an inner shielding portion and an outer shielding portion, the inner shielding portion being disposed between the channel structure and the top surface, the outer shielding portion being disposed on the bottom surface and the plurality of side surfaces, and the inner shielding portion extending to connect with the outer shielding portion to form an annular structure surrounding the substrate; and an external terminal disposed on and electrically connected to the channel structure.

2. The semiconductor device of claim 1, wherein the channel structure does not directly contact the ground pad, and the shielding structure does not directly contact the signal pad.

3. The semiconductor device as claimed in claim 1, further comprising a first insulating layer and a second insulating layer, wherein: In the contact area, the first insulating layer and the second insulating layer cover the inner shielding portion; and in the signal area, the channel structure penetrates the second insulating layer.

4. The semiconductor device as claimed in claim 1, further comprising an outer ball-shaped metal layer disposed between the external terminal and the channel structure.

5. The semiconductor device of claim 1, wherein the channel structure includes an inner spherical bottom metal layer, wherein the inner spherical bottom metal layer is laterally aligned with the inner shield.

6. The semiconductor device as claimed in claim 5, wherein the material of the inner spherical bottom metal layer is the same as that of the inner shield.

7. The semiconductor device of claim 1, wherein a first edge of the substrate is flush with a second edge of the inner shield.

8. The semiconductor device of claim 7, wherein the outer shielding portion directly contacts the first edge and the second edge.

9. The semiconductor device of claim 1, wherein the inner shield between the signal region and the grounding region is sheet-like or grid-like.

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