Substrate structure

Abstract

The present invention provides a substrate structure, which includes a substrate body, a patterned metal layer and an insulating protective layer. The substrate body has a circuit layer and defines a chip placement area and the patterned metal layer is provided on the substrate body. The insulating protective layer has an opening corresponding to the chip placement area and exposing part of the circuit layer and part of the patterned metal layer, and by reducing the area of the patterned metal layer exposing the opening of the insulating protective layer, the problem of delamination is improved.

Description

Technical Field

[0001] This invention relates to a semiconductor structure, and more particularly to a substrate structure for carrying electronic components. Prior Technology

[0002] With the development of the electronics industry, today's electronic products are trending towards thinner, smaller, and more functional designs, and semiconductor packaging technology has also developed different packaging types accordingly. To meet the requirements of high integration and miniaturization of semiconductor devices, the industry mostly adopts flip-chip packaging structures.

[0003] Figures 1A and 1B are a cross-sectional view and a partial top view of a conventional flip-chip package 1, respectively. As shown in Figure 1A, a package substrate 10 has a circuit layer 100 composed of copper wires, an insulating protective layer 101, and an opening 102 for exposing the circuit layer 100. A die placement area D is defined on the package substrate 10. A semiconductor wafer 11 is bonded to the circuit layer 100 in the die placement area D of the package substrate 10 by a plurality of solder bumps 12. Then, an adhesive 13 is formed between the semiconductor wafer 11 and the package substrate 10 to cover the plurality of solder bumps 12. The circuit layer 100 includes electrical contacts (pads) electrically connected to the semiconductor wafer and a large-area metal layer (copper layer) providing power / ground functions.

[0004] However, the adhesive 13 and the circuit layer 100 in the die placement area D have poor adhesion due to the large contact area, which easily leads to delamination problems, and the adhesive 13 and the packaging substrate 10 are also easy to separate.

[0005] Therefore, overcoming the various problems of the aforementioned conventional technologies has become an urgent issue for the industry. Summary of the Invention

[0006] The present invention provides a substrate structure, including a substrate body, a circuit layer disposed on one surface thereon, and a crystal placement region defined on the surface thereon; a patterned metal layer disposed on the surface thereon; and an insulating protective layer disposed on the surface thereon, having an opening corresponding to the crystal placement region and exposing a portion of the circuit layer and a portion of the patterned metal layer, wherein the area of ​​the circuit layer and the patterned metal layer exposed by the opening accounts for 45% to 55% of the area of ​​the opening.

[0007] As described above, the substrate body is either a substrate with a core layer or a substrate without a core layer.

[0008] As described above, the circuit layer includes a plurality of electrical contact pads and a plurality of conductive traces connecting the plurality of electrical contact pads.

[0009] As described above in the substrate structure, the patterned metal layer is used to provide power / grounding.

[0010] As described above, the patterned metal layer includes a plurality of metal blocks and a plurality of metal lines connecting at least two of the plurality of metal blocks.

[0011] As described above, the patterned metal layer includes a large area of ​​metal layer and a plurality of slots formed on the large area of ​​metal layer, thereby exposing the plurality of slots outside the substrate body. The slots can be square, circular, elliptical or irregular in shape.

[0012] As described in the aforementioned substrate structure, the patterned metal layer includes grid-like metal lines. Furthermore, the patterned metal layer also includes metal blocks connecting the grid-like metal lines.

[0013] As described above regarding the substrate structure, the insulating protective layer is reinforced with a plurality of insulating blocks comprising a crystal placement region located within the opening. These plurality of insulating blocks are spaced apart from each other and are circular, square, or irregular in shape.

[0014] In summary, the substrate structure of the present invention mainly reduces the area of ​​the patterned metal layer exposed by the opening of the insulating protective layer in the crystal placement area on the surface of the substrate body (for example, the patterned metal layer is presented in the form of fine metal lines, slots, grids, or multiple insulating blocks are added in the opening), so that the area of ​​the circuit layer and the patterned metal layer exposed by the opening accounts for about 45%-55% of the area of ​​the opening, thereby effectively reducing the ratio of exposed copper (circuit layer and patterned metal layer), thereby reducing the contact area between the adhesive and the copper, and improving the delamination problem. Simple Explanation of the Diagram

[0015] Figure 1A and Figure 1B are respectively a cross-sectional view and a partial top view of a conventional flip-chip packaging structure.

[0016] Figures 2A to 2C are top views of the first embodiment of the substrate structure of the present invention.

[0017] Figure 3 is a top view schematic diagram of the second embodiment of the substrate structure of the present invention. Implementation

[0018] The following specific embodiments illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification.

[0019] It should be understood that the structures, proportions, sizes, etc., illustrated in the accompanying drawings of this specification are only for the purpose of assisting those skilled in the art in understanding and reading the content disclosed herein, and are not intended to limit the conditions under which the invention can be implemented. Therefore, they have no substantial technical significance. Any modifications to the structure, changes in the proportional relationships, or adjustments to the size, without affecting the effects and objectives that the invention can produce, should still fall within the scope of the technical content disclosed in this invention. Furthermore, the terms such as "above" and "a" used in this specification are only for clarity of description and are not intended to limit the scope of the invention. Changes or adjustments to their relative relationships, without substantially altering the technical content, should also be considered within the scope of the invention's implementation.

[0020] Please refer to Figures 2A to 2C, which are top views of the first embodiment of the substrate structure 2 of the present invention.

[0021] The substrate structure 2 of the present invention is, for example, a packaging substrate for carrying a semiconductor wafer, which includes a substrate body 20, a patterned metal layer 21 and an insulating protective layer 22.

[0022] The substrate body 20 is, for example, a substrate with a core layer or a coreless substrate. The substrate body 20 has a circuit layer 201 disposed on its surface 200 and a crystal placement region D defined on the surface 200.

[0023] In this embodiment, the substrate body 20 includes an insulating layer and a wiring layer (not shown) formed on the insulating layer. This wiring layer can be, for example, a fan-out redistribution layer (RDL), with the outermost wiring layer serving as the circuit layer 201. The circuit layer 201 includes a plurality of electrical contact pads 201a and a plurality of conductive traces 201b connecting the plurality of electrical contact pads 201a. A die-placement region D is used to mount electronic components, such as semiconductor wafers or passive components, thereon. For example, electronic components are mounted on the electrical contact pads 201a via conductive bumps to form an electronic package.

[0024] Furthermore, the material forming the wiring layer is copper, and the insulating layer is a dielectric material such as polybenzoxazole (PBO), polyimide (PI), or prepreg (PP).

[0025] A patterned metal layer 21 is disposed on the surface 200 of the substrate body 20 and adjacent to the circuit layer 201, wherein the patterned metal layer 21 is designed to provide power / grounding.

[0026] In one embodiment, as shown in FIG2A, the patterned metal layer 21 includes a plurality of metal blocks 211 and a plurality of metal lines (fine lines) 212 connecting at least two of the plurality of metal blocks 211.

[0027] In another embodiment, as shown in FIG2B, the patterned metal layer 21 includes a large-area metal layer 213 and a plurality of slots 214 formed on the large-area metal layer 213, thereby exposing the plurality of slots 214 on the substrate body 20. The shape of each slot 214 can be square, circular or elliptical as shown in the figure, or a suitable shape (e.g., irregular shape) can be designed according to the actual situation.

[0028] In another embodiment, as shown in FIG2C, the patterned metal layer 21 includes grid-like metal lines 215. The patterned metal layer further includes metal blocks 216 connecting the grid-like metal lines 215.

[0029] The insulating protective layer 22 is disposed on the surface 200 of the substrate body 20 and has at least one opening 220. In this embodiment, the opening 220 corresponds to the die-placement area D and exposes a portion of the circuit layer 201 and a portion of the patterned metal layer 21. A portion of the opening 220 is located within the die-placement area D, while the remainder is located outside the die-placement area D. The opening 220 located outside the die-placement area D allows the primer to effectively flow between the electronic components and the substrate body 20. Furthermore, the material of the insulating protective layer 22 can be, for example, a solder resist such as green paint or ink.

[0030] In this embodiment, the substrate structure 2 mainly reduces the area of ​​the patterned metal layer 21 exposed in the opening 220 (full-window type) of the insulating protective layer 22, so that the area of ​​the circuit layer 201 and the patterned metal layer 21 exposed in the opening 220 (metal material area) accounts for about 45%-55% of the area of ​​the opening 220. This solves the problem that when a large area of ​​metal layer (copper layer) is exposed in the conventional substrate structure with a full-window, the adhesion between the adhesive and the copper becomes worse due to the larger the exposed copper area.

[0031] Figure 3 is a top view schematic diagram of the second embodiment of the substrate structure 2 of the present invention.

[0032] The substrate structure 2 in this embodiment is largely the same as that in the previous embodiment, including a substrate body 20, a patterned metal layer 21 and an insulating protective layer 22. The main difference is that the insulating protective layer 22 is formed with a plurality of insulating blocks 221 of the crystal placement area D located in the opening 220.

[0033] The plurality of insulating blocks 221 partially cover the patterned metal layer 21 to reduce the area of ​​the patterned metal layer 21 exposed in the opening 220. Furthermore, the plurality of insulating blocks 221 are spaced apart from each other, and their shape can be circular, square or irregular, and the present invention is not limited thereto.

[0034] In summary, the substrate structure of the present invention mainly reduces the area of ​​the patterned metal layer exposed by the opening of the insulating protective layer in the crystal placement area on the surface of the substrate body (for example, the patterned metal layer is presented in the form of fine metal lines, slots, grids, or multiple insulating blocks are added in the opening), so that the area of ​​the circuit layer and the patterned metal layer exposed by the opening accounts for about 45%-55% of the area of ​​the opening, thereby effectively reducing the ratio of exposed copper (circuit layer and patterned metal layer), thereby reducing the contact area between the adhesive and the copper, and improving the delamination problem.

[0035] The above embodiments are illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify the above embodiments without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention should be as set forth in the following patent claims.

[0036]

[0037] 1: Flip-chip package

[0038] 10: Packaging substrate

[0039] 100: Line Layer

[0040] 101: Insulation protective layer

[0041] 102: Opening

[0042] 11: Semiconductor wafers

[0043] 12: Solder bumps

[0044] 13: Base rubber

[0045] 2: Substrate Structure

[0046] 20:Substrate body

[0047] 200: Surface

[0048] 201: Line Layer

[0049] 201a: Electrical contact pad

[0050] 201b: Conductive traces

[0051] 21: Patterned metal layer

[0052] 211: Metal Block

[0053] 212: Metal wire

[0054] 213: Large-scale metal layer

[0055] 214: Grooving

[0056] 215: Grille-style metal wire

[0057] 216: Metal Block

[0058] 22: Insulation protective layer

[0059] 220: Opening

[0060] 221: Insulating Block

[0061] D: Crystal placement area

Claims

1. A substrate structure, comprising: The substrate body has a circuit layer disposed on one surface and a crystal placement area defined on the surface. A patterned metal layer is disposed on the surface, wherein the patterned metal layer includes a plurality of metal blocks and a plurality of metal lines connecting at least two of the plurality of metal blocks; and an insulating protective layer is disposed on the surface and has an opening corresponding to the crystal region and exposing a portion of the circuit layer and a portion of the patterned metal layer, wherein the area of ​​the circuit layer and the patterned metal layer exposed by the opening accounts for 45% to 55% of the area of ​​the opening.

2. The substrate structure as described in claim 1, wherein, The substrate body can be a substrate with a core layer or a substrate without a core layer.

3. The substrate structure as described in claim 1, wherein, The circuit layer includes a plurality of electrical contact pads and a plurality of conductive traces connecting the plurality of electrical contact pads.

4. The substrate structure as described in claim 1, wherein, This patterned metal layer is used to provide power / grounding.

5. A substrate structure, comprising: The substrate body has a circuit layer disposed on one surface and a crystal placement area defined on the surface. A patterned metal layer is disposed on the surface, wherein the patterned metal layer includes a large-area metal layer and a plurality of slots formed on the large-area metal layer to expose the plurality of slots outside the substrate body; and an insulating protective layer is disposed on the surface and has an opening corresponding to the crystal placement region and exposing a portion of the circuit layer and a portion of the patterned metal layer, wherein the area of ​​the circuit layer and the patterned metal layer exposed by the opening accounts for 45% to 55% of the area of ​​the opening.

6. The substrate structure as described in claim 5, wherein, The slot shape can be square, round, oval, or irregular.

7. A substrate structure, comprising: The substrate body has a circuit layer disposed on one surface and a crystal placement area defined on the surface. A patterned metal layer is disposed on the surface, wherein the patterned metal layer includes grid-like metal lines; and an insulating protective layer is disposed on the surface and has an opening corresponding to the crystal region and exposing a portion of the circuit layer and a portion of the patterned metal layer, wherein the area of ​​the circuit layer and the patterned metal layer exposed by the opening accounts for 45% to 55% of the area of ​​the opening.

8. The substrate structure as described in claim 7, wherein, The patterned metal layer also includes metal blocks that connect the grid-like metal lines.

9. A substrate structure, comprising: The substrate body has a circuit layer disposed on one surface and a crystal placement area defined on the surface. A patterned metal layer is disposed on the surface; An insulating protective layer is disposed on the surface and has an opening corresponding to the crystal placement area and exposing a portion of the circuit layer and a portion of the patterned metal layer, wherein the area of ​​the circuit layer and the patterned metal layer exposed by the opening accounts for 45% to 55% of the area of ​​the opening, and the insulating protective layer is compounded to have a plurality of insulating blocks of the crystal placement area located within the opening.

10. The substrate structure as described in claim 9, wherein, The plurality of insulating blocks are spaced apart from each other and are circular, square or irregular in shape.

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