Package substrate and fabricating method thereof

Abstract

A packaging substrate is made by embedding a wiring component in a circuit structure to increase trace density so that the packaging substrate can meet the requirements of fine lines / fine pitches.

Description

Technical Field

[0001] This disclosure relates to a semiconductor packaging technology, and more particularly to a packaging substrate for embedded wiring elements and its manufacturing method. Prior Technology

[0002] Currently, technologies used in the field of chip packaging include packaging modules such as Chip Scale Package (CSP), Direct Chip Attached (DCA), and Multi-Chip Module (MCM). Typically, semiconductor chips are mounted on a packaging substrate.

[0003] However, conventional packaging substrates use a build-up process to fabricate circuit layers, which is limited by the need for miniaturization and makes it difficult to increase wiring density, resulting in conventional packaging substrates being unable to meet the requirements for fine lines / fine pitch.

[0004] Therefore, how to overcome the problems of the aforementioned conventional technologies has become an urgent issue that needs to be addressed. Summary of the Invention

[0005] In view of the various deficiencies of the prior art, this disclosure provides a packaging substrate comprising: a core board having a core layer defining a first side and a second side opposite to each other, and at least one conductive post connecting the first side and the second side, wherein a first circuit structure is formed on the first side and the second side respectively, wherein the first circuit structure has at least one first dielectric layer and a first circuit layer bonded to the first dielectric layer and electrically connected to the conductive post; a wiring element disposed on the first circuit structure on the first side of the core board; and a second circuit structure disposed on the first circuit structure on the first side of the core board and covering the wiring element, such that the wiring element is embedded in the second circuit structure, and the second circuit structure electrically connects the wiring element and the first circuit layer.

[0006] This disclosure also provides a method for manufacturing a packaging substrate, comprising: providing a core board having a core layer defining opposing first and second sides, and at least one conductive post connecting the first and second sides, wherein a first circuit structure is formed on the first and second sides respectively, wherein the first circuit structure has at least one first dielectric layer and a first circuit layer bonded to the first dielectric layer and electrically connected to the conductive post; disposing a wiring element on the first circuit structure on the first side of the core board; and forming a second circuit structure on the first circuit structure on the first side of the core board, such that the second circuit structure covers the wiring element, thereby embedding the wiring element in the second circuit structure, and the second circuit structure electrically connecting the wiring element and the first circuit layer.

[0007] In a specific embodiment of the aforementioned packaging substrate and its manufacturing method, an internal circuit layer electrically connected to the conductive pillar is respectively arranged on the first and second sides of the core layer.

[0008] In a specific embodiment of the aforementioned packaging substrate and its manufacturing method, the conductive pillar is a hollow conductive pillar with both ends flush with the first and second sides of the core layer, and the hollow conductive pillar is filled with a hole-sealing material.

[0009] In a specific embodiment of the aforementioned packaging substrate and its manufacturing method, the wiring element is attached to the first circuit structure by means of an adhesive layer.

[0010] In a specific embodiment of the aforementioned packaging substrate and its manufacturing method, the adhesive layer is formed on the entire surface of the first circuit structure.

[0011] In a specific embodiment of the aforementioned packaging substrate and its manufacturing method, the second circuit structure is superimposed on the first circuit structure on the second side of the core board.

[0012] In a specific embodiment of the aforementioned packaging substrate and its manufacturing method, the core layer has a plurality of through holes penetrating the first side and the second side, and the first dielectric layer is filled in the plurality of through holes.

[0013] In a specific embodiment of the aforementioned packaging substrate and its manufacturing method, the conductive pillars are formed in the through hole and extend to the surfaces of the first dielectric layers on the first and second sides.

[0014] As can be seen from the above, in the packaging substrate and its manufacturing method disclosed herein, the wiring element is embedded in the second line structure to increase the wiring density, so that the packaging substrate can meet the requirements of fine lines / fine pitch.

[0015] Furthermore, by attaching the wiring element to the first circuit structure, the wiring element can be replaced when it malfunctions, without scrapping the core board, thus significantly reducing the manufacturing cost of the packaging substrate.

[0016] Furthermore, by using glass, for example, as the core layer, the risk of warping or deformation of the core plate during processing can be reduced due to its stable rigidity (high toughness), low coefficient of thermal expansion, and stable dimensional change.

[0017] Furthermore, since glass has stable rigidity (high toughness), low coefficient of thermal expansion, and stable dimensional change, a thinner glass can be used as the core layer to reduce the total thickness of the packaging substrate. Simple Explanation of the Diagram

[0018] Figures 1A to 1G are cross-sectional schematic diagrams of the manufacturing method of the first embodiment of the packaging substrate disclosed herein.

[0019] Figure 1H is a cross-sectional schematic diagram of the subsequent process of Figure 1G.

[0020] Figures 2A to 2C are cross-sectional schematic diagrams of the manufacturing method of the second embodiment of the packaging substrate disclosed herein. Implementation

[0021] The following specific embodiments illustrate the implementation of this disclosure. Those skilled in the art can easily understand the other advantages and effects of this disclosure from the content disclosed in this specification.

[0022] It should be understood that the structures, proportions, sizes, etc., illustrated in the accompanying diagrams of this specification are merely for the purpose of assisting those skilled in the art in understanding and reading the content disclosed herein, and are not intended to limit the conditions under which this disclosure can be implemented. Therefore, they have no substantial technical significance. Any modifications to the structure, changes in the proportional relationships, or adjustments to the size, without affecting the effectiveness and purpose of this disclosure, should still fall within the scope of the technical content disclosed herein. Furthermore, the terms such as "above," "first," "second," and "one" used in this specification are merely for clarity of description and are not intended to limit the scope of this disclosure. Changes or adjustments to their relative relationships, without substantially altering the technical content, should also be considered within the scope of this disclosure's implementation.

[0023] Figures 1A to 1H are cross-sectional schematic diagrams of the manufacturing method of the first embodiment of the packaging substrate 1 disclosed herein.

[0024] As shown in Figure 1A, a support member 8 is provided, and a wiring block 1a is formed on each of the opposite sides of the support member 8.

[0025] In this embodiment, the support member 8 is a temporary carrier plate, which can be a plate with metal layers on opposite sides, such as a copper foil substrate. The surface of the plate 80 has a copper foil 81, and a metal layer 82, such as a copper layer, is formed on the copper foil 81 so that the wiring block 1a is formed on the metal layer 82.

[0026] Furthermore, the wiring block 1a adopts a coreless wiring specification, in which a wiring layer 141 is formed in the dielectric 140. For example, the dielectric 140 is an Ajinomoto build-up film (ABF), polybenzoxazole (PBO), polyimide (PI), glass fiber prepreg (PP), or other dielectric materials.

[0027] Furthermore, the wiring layer 141 is fabricated using a build-up process, employing electroplated metal (such as copper) or other methods. For example, the wiring layer 141 is made of copper and uses a redistribution layer (RDL) specification, giving it a very small line width / spacing (L / S), such as L / S 5 / 5um. Understandably, by using the layer-addition method, the required number of wiring layers 141 can be fabricated as needed.

[0028] As shown in Figure 1B, the copper foil 81 is used to separate the plate 80 of the carrier 8 from the wiring block 1a, and then the metal layer 82 is removed.

[0029] In this embodiment, the copper foil 81 is removed by peeling or other means to separate the board 80 from the metal layer 82, and then the metal layer 82 on the wiring block 1a is removed by etching.

[0030] As shown in Figure 1C, a single-cutting process is performed along the cutting path S shown in Figure 1B to obtain a plurality of wiring elements 14. The wiring layer 141 on one side surface of the obtained wiring element 14 is embedded in the dielectric 140 and is flush with the surface of the wiring element 14, that is, the side surface that contacts the metal layer 82 of the dielectric 140, while the wiring layer 141 on the other side surface of the wiring element 14 is formed on the surface of the dielectric 140.

[0031] As shown in Figures 1D to 1E, the wiring element 14 is disposed on a core board 1b. The core board 1b includes a core layer 10, wherein the core layer 10 defines a first side 10a and a second side 10b opposite to each other, and an inner circuit layer 101 made of copper is respectively disposed on the first side 10a and the second side 10b of the core layer 10. The core layer 10 has a plurality of conductive pillars 100 connecting the first side 10a and the second side 10b, so that the conductive pillars 100 are electrically connected to the inner circuit layers 101.

[0032] In this embodiment, the core layer 10 is made of a high-hardness dielectric material, such as glass, ceramic, SiC, AlO2, or a high-rigidity composite material with a modulus of 50 to 100 GPa. For example, a plurality of cylindrical perforations are formed by laser penetration through the first side 10a and the second side 10b of the core layer 10. Conductive material is then formed on the wall of the perforations to serve as hollow conductive pillars 100, and the hollow spaces can be filled with a plugging material 102. The plugging material 102 can be of various types, such as conductive adhesive or ink, and is not particularly limited. The formation of the conductive material may include a barrier layer formed on the wall of the perforations and a seed layer formed on the barrier layer. In addition, a barrier layer and a seed layer can also be formed on the surfaces of the first side 10a and the second side 10b of the core layer 10, and then these internal circuit layers 101 are formed in conjunction with copper plating and patterning processes. The conductive pillar 100 in this embodiment is formed as described above, consisting of a barrier layer formed on the wall of the via and a seed layer formed on the barrier layer. The barrier layer can be a dielectric barrier layer or a conductive barrier layer. Materials forming the dielectric barrier layer include silicon nitride, silicon oxynitride, silicon carbonitride, or diamond-like carbon (DLC), but are not limited thereto. Materials forming the conductive barrier layer include metal nitrides (e.g., Ta, TiN, TaN, or WN), but are not limited thereto. Materials forming the seed layer include copper, manganese-doped copper, or ruthenium, but are not limited thereto. Furthermore, in this embodiment, the conductive pillar 100 is a hollow conductive pillar 100 with both ends flush with the first side 10a and the second side 10b of the core layer 10, and the hollow conductive pillar 100 is filled with a via-plugging material 102.

[0033] It should be understood that in other embodiments, the conductive post 100 may also be a solid metal post without the need to fill the hole with plugging material 102.

[0034] Furthermore, the core plate 1b has first circuit structures 11 formed on the first side 10a and the second side 10b of the core layer 10, and the first circuit structures 11 are electrically connected to the inner circuit layer 101. For example, the first circuit structure 11 can be formed by using a build-up process to form at least one first dielectric layer 110 on the first side 10a and the second side 10b of the core layer 10, and a first circuit layer 111 formed on the first dielectric layer 110 and extending into the first dielectric layer 110 to electrically connect to the inner circuit layer 101. The portion of the first circuit layer 111 extending into the first dielectric layer 110 to electrically connect to the inner circuit layer 101 is a conductive blind via.

[0035] Furthermore, the first dielectric layer 110 can be made of dielectric materials such as Ajinomoto build-up film (ABF), polybenzoxazole (PBO), polyimide (PI), prepreg (PP), or others. The first circuit layer 111 can be formed by electroplating metal (such as copper) or other methods, such as a redistribution layer (RDL). It should be understood that the number of layers in the first circuit layer 111 can be designed according to requirements and is not particularly limited.

[0036] Additionally, the wiring element 14 can be bonded to the first circuit structure 11 on the first side 10a (and / or the second side 10b) via an adhesive layer 13. For example, an adhesive layer 13 covering the first circuit layer 111 can be formed on the entire surface of the first circuit structure 11, and then the wiring element 14 can be adhered to the adhesive layer 13. It should be understood that the number of wiring elements 14 can be configured as needed and is not particularly limited.

[0037] As shown in Figure 1F, a second circuit structure 12 is formed on the adhesive layer 13 on the first side 10a and the first circuit structure 11 on the second side 10b of the core board 1b, respectively, and the second circuit structure 12 covers the wiring element 14 so that the wiring element 14 is embedded in the second circuit structure 12, and the second circuit structure 12 electrically connects the wiring element 14 and the first circuit structure 11.

[0038] In this embodiment, the second circuit structure 12 can be formed on the first circuit structure 11 by a build-up process, forming at least one second dielectric layer 120 and a second circuit layer 121 (including conductive blind vias and circuits on the second dielectric layer 120) on the second dielectric layer 120 and extending into the second dielectric layer 120 to electrically connect the wiring layer 141 and the first circuit layer 111. For example, the second dielectric layer 120 is an Ajinomoto build-up film (ABF), polybenzoxazole (PBO), polyimide (PI), prepreg (PP), or other dielectric materials, and the second circuit layer 121 can be formed by electroplating metal (such as copper) or other methods, such as a redistribution layer (RDL) specification. It should be understood that the number of layers in the second line layer 121 can be designed according to requirements and there are no particular restrictions.

[0039] Furthermore, the materials used to form the dielectric 140, the first dielectric layer 110, and the second dielectric layer 120 may be the same or different.

[0040] As shown in Figure 1G, a solder resist layer 17 is formed on each of the second circuit structures 12 to obtain the packaging substrate 1.

[0041] In this embodiment, the second circuit layer 121 is exposed on the solder mask layer 17. For example, the solder mask layer 17 is formed with a plurality of openings 170 so that a portion of the surface of the second circuit layer 121 is exposed on the openings 170 for use as an electrical contact pad 122.

[0042] In subsequent processes, as shown in Figure 1H, at least one electronic component 30 can be bonded to the electrical contact pads 122 by a plurality of conductive bumps 19, such as solder material, copper bumps or others.

[0043] The electronic component 30 is, for example, an active component, a passive component, a package structure, or a combination thereof, wherein the active component is, for example, a semiconductor wafer, and the passive component is, for example, a resistor, a capacitor, and an inductor.

[0044] In this embodiment, the electronic component 30 is a semiconductor chip, which can be disposed on the electrical contact pads 122 of the second circuit structure 12 on the first side 10a (and / or the second side 10b) of the core plate 1b via a plurality of conductive bumps 19 in a flip-chip manner and electrically connected to the second circuit layer 121; or, the electronic component 30 can be electrically connected to the second circuit layer 121 via a plurality of bonding wires (not shown); or, the electronic component 30 can directly contact the second circuit layer 121. It should be understood that there are many ways in which the electronic component 30 is electrically connected to the second circuit structure 12, and it is not limited to the above.

[0045] Therefore, the manufacturing method of this embodiment is to improve the wiring density by embedding the wiring element 14 in the second dielectric layer 120, so that the packaging substrate 1 meets the requirements of fine line / fine pitch (Fine L / S).

[0046] Furthermore, by attaching the wiring element 14 to the first circuit structure 11, the wiring element 14 can be replaced when it is faulty, without scrapping the core board 1b, thus significantly reducing the manufacturing cost of the packaging substrate 1.

[0047] Furthermore, by using glass, for example, as the core layer 10, the risk of warping or deformation of the core plate 1b during processing can be reduced due to its stable rigidity (high toughness), low coefficient of thermal expansion (CTE), and stable dimensional changes.

[0048] Furthermore, since glass has stable rigidity (high toughness), low coefficient of thermal expansion (CTE), and stable dimensional changes, a thinner glass can be used as the core layer 10 to reduce the total thickness of the encapsulation substrate 1.

[0049] Figures 2A to 2C are cross-sectional schematic diagrams illustrating the manufacturing method of the second embodiment of the packaging substrate 2 disclosed herein. The main difference between this embodiment and the first embodiment lies in the design of the core board 2b; other processes are largely the same, so the similarities will not be repeated below.

[0050] As shown in Figure 2A, a core layer 20 with a plurality of vias 200 is provided, and there are no internal circuit layers 101 on the first side 20a and the second side 20b of the core layer 20.

[0051] In this embodiment, a plurality of cylindrical perforations 200 are formed by laser penetration through the first side 20a and the second side 20b of the core layer 20.

[0052] As shown in Figure 2B, a first circuit structure 21 is formed on the first side 20a and the second side 20b of the core layer 20 to form a core plate 2b.

[0053] In this embodiment, the first circuit structure 21 is formed by a build-up process on the first side 20a and the second side 20b of the core layer 20, respectively forming at least one first dielectric layer 110 and a first circuit layer 211 bonded to the surface of the first dielectric layer 110. The first dielectric layer 110 is filled into the plurality of vias 200, and at least one conductive post 201 is formed in the first dielectric layer 110, penetrating the vias 200 and extending to the surface of each of the first dielectric layers 110 on the first side 20a and the second side 20b, to electrically connect to each of the first circuit layers 211.

[0054] The first dielectric layer 110 can be formed by lamination on the first side 20a and the second side 20b of the core layer 20 and in the plurality of through holes 200. Furthermore, the conductive pillar 201 is funnel-shaped or X-shaped. For example, the manufacturing process of the conductive pillar 201 can involve laser two-stage opening, followed by a plating process to form a first conical pillar 201a extending into the through hole 200 in the first dielectric layer 110 on the first side 20a of the core layer 20, and a second conical pillar 201b extending into the through hole 200 in the first dielectric layer 110 on the second side 20b of the core layer 20, such that the apex of the first conical pillar 201a connects to the apex of the second conical pillar 201b. It should be understood that the shape and manufacturing method of the conductive pillar 201 are numerous and not limited to the above. The first circuit layer 211 can also be formed by electroplating and patterning processes. For example, by laminating a composite material having a first dielectric layer and a metal layer (not shown), at least one first dielectric layer 110 is formed on the first side 20a and the second side 20b of the core layer 20, and the core plate body 2b has metal layers on both sides. Then, the first circuit layer 211 is formed by electroplating and patterning processes.

[0055] As shown in Figure 2C, at least one wiring element 14 is disposed on the first circuit structure 21 on the first side 20a of the core board 2b by means of an adhesive layer 13. Then, a second circuit structure 22 is formed on the adhesive layer 13 and the wiring element 14 on the first circuit structure 21 on the first side 20a of the core board 2b. Subsequently, a solder resist layer 17 is formed on the first circuit structure 21 on the second side 20b of the core board 2b and the second circuit structure 22 on the first side 20a of the core board 2b, respectively, to obtain the packaging substrate 2.

[0056] In this embodiment, the first circuit layer 211 of the first circuit structure 21 on the second side 20b of the core board 2b is exposed to the solder mask 17. For example, the solder mask 17 has a plurality of openings 170, so that a portion of the surface of the first circuit layer 211 is exposed to the openings 170 for use as electrical contact pads 212. It should be understood that, referring to step 1F, at least one second dielectric layer 220 is formed on the first circuit structure 21 using a build-up process, and a second circuit layer 221 (including conductive blind vias in the second dielectric layer 220 and circuits on the second dielectric layer 220) is formed on the second dielectric layer 220 and extends into the second dielectric layer 220 to electrically connect the wiring layer 141 and the first circuit layer 211. Furthermore, the second circuit layer 221 is exposed to the openings 170 of the solder mask 17 for use as electrical contact pads 222.

[0057] Therefore, in this embodiment, the second circuit structure 22 is not formed on the first circuit structure 21 of the second side 20b of the core board 2b, so the total thickness of the packaging substrate 2 can be greatly reduced. Therefore, the total thickness of the packaging substrate 2 in the second embodiment is less than the total thickness of the packaging substrate 1 in the first embodiment.

[0058] Furthermore, in this embodiment, the conductive pillar 201 is fabricated at the same time as the first circuit structure 21, so the fabrication of the inner circuit layer 101 and the via material 102 can be omitted. Also, since the fabrication of the second circuit structure 12 on the second side 20b of the core board 2b is also omitted, the number of process steps can be greatly reduced, thereby effectively reducing the manufacturing cost.

[0059] This disclosure also provides a packaging substrate 1,2, which includes: a core board 1b,2b, at least one wiring element 14, and a second circuit structure 12,22.

[0060] The core plates 1b and 2b have a core layer 10 and 20, which defines a first side 10a and 20a and a second side 10b and 20b, and at least one conductive post 100 and 201 connecting the first side 10a and 20a and the second side 10b and 20b. A first circuit structure 11 and 21 is formed on the first side 10a and 20a and the second side 10b and 20b, respectively. The first circuit structure 11 and 21 has at least one first dielectric layer 110 and a first circuit layer 111 and 211 that are combined with the first dielectric layer 110 and electrically connected to the conductive post 100 and 201.

[0061] The wiring element 14 is disposed on the first line structure 11, 21 of the first side 10a, 20a of the core board 1b, 2b.

[0062] The second circuit structure 12, 22 is disposed on the first circuit structure 11, 21 on the first side 10a, 20a of the core board 1b, 2b and covers the wiring element 14, so that the wiring element 14 is embedded in the second circuit structure 12, 22, and the second circuit structure 12, 22 electrically connects the wiring element 14 to the first circuit layer 111, 211.

[0063] In one embodiment, a circuit layer 101 electrically connected to the conductive pillar 100 is respectively arranged on the first side 10a and the second side 10b of the core layer 10.

[0064] In one embodiment, the conductive post 100 is a hollow conductive post 100 with both ends flush with the first side 10a and the second side 10b of the core layer 10, and the hollow conductive post 100 is filled with a pore-sealing material 102.

[0065] In one embodiment, the wiring element 14 is attached to the first wiring structure 11, 21 by means of an adhesive layer 13.

[0066] In one embodiment, the adhesive layer 13 is formed on the entire surface of the first circuit structure 11, 21.

[0067] In one embodiment, the second circuit structure 12 is superimposed on the first circuit structure 11 on the second side 10b of the core plate 1b.

[0068] In one embodiment, the core layer 20 has a plurality of through holes 200 penetrating the first side 20a and the second side 20b, and the first dielectric layer 110 is filled in the plurality of through holes 200.

[0069] In one embodiment, the conductive post 201 is formed in the through hole 200 and extends to the surface of the first dielectric layer 110 on the first side 20a and the second side 20b.

[0070] In summary, the packaging substrates 1 and 2 disclosed herein and their manufacturing method improve the wiring density by embedding the wiring element 14 in the second line structure 12 and 22, so that the packaging substrates 1 and 2 meet the requirements of fine lines / fine pitch.

[0071] Furthermore, by attaching the wiring element 14 to the first circuit structure 11, 21, when the wiring element 14 is faulty, it can be replaced without scrapping the core board 1b, 2b, thus significantly reducing the manufacturing cost of the packaging substrate 1, 2.

[0072] Furthermore, by using glass as the core layer 10, 20, the risk of warping or deformation of the core plate 1b, 2b during processing can be reduced due to its stable rigidity (high toughness), low coefficient of thermal expansion, and stable dimensional change.

[0073] Furthermore, since glass has stable rigidity (high toughness), low coefficient of thermal expansion, and stable dimensional change, thinner glass can be used as the core layer 10, 20 to reduce the total thickness of the encapsulation substrate 1, 2.

[0074] The above embodiments are illustrative of the principles and effects of this disclosure and are not intended to limit this disclosure. Any person skilled in the art can modify the above embodiments without departing from the spirit and scope of this disclosure. Therefore, the scope of protection of this disclosure should be as set forth in the following patent application claims.

[0075]

[0076] 1,2: Packaging substrate

[0077] 1a: Wiring block

[0078] 1b, 2b: Core plate

[0079] 10,20: Core Layer

[0080] 10a, 20a: First side

[0081] 10b, 20b: Second side

[0082] 100, 201: Conductive pillars

[0083] 101: Internal Circuit Layer

[0084] 102: Hole plugging material

[0085] 11,21: First line structure

[0086] 110: First dielectric layer

[0087] 111,211: First line layer

[0088] 12,22: Second line structure

[0089] 120,220: Second dielectric layer

[0090] 121,221: Second line layer

[0091] 122,212,222: Electrical contact pads

[0092] 13: Adhesive layer

[0093] 14: Wiring components

[0094] 140: Dielectric

[0095] 141: Wiring Layer

[0096] 17: Solder resist layer

[0097] 170: Opening

[0098] 19: Conductive bumps

[0099] 200: Perforation

[0100] 201a: First conical column

[0101] 201b: Second conical column

[0102] 30: Electronic components

[0103] 8: Support components

[0104] 80:Plate body

[0105] 81: Copper Foil

[0106] 82: Metal layer

[0107] S: Cutting path

Claims

1. A packaging substrate, comprising: The core plate has a core layer, which defines a first side and a second side opposite to each other and has a plurality of through holes penetrating the first side and the second side, and at least one conductive post formed in the through holes to connect the first side and the second side. A first circuit structure is formed on the first side and the second side respectively. The first circuit structure has at least one first dielectric layer and a first circuit layer that is bonded to the first dielectric layer and electrically connected to the conductive post. The first dielectric layer is filled in the plurality of through holes, and a first cone-shaped post and a second cone-shaped post extending into the through holes are formed in the first dielectric layer on the first side and the second side respectively. The cone apex of the first cone-shaped post is connected to the cone apex of the second cone-shaped post to form the conductive post extending from the surface of the first dielectric layer on the first side to the surface of the first dielectric layer on the second side. A wiring element is disposed on a first circuit structure on a first side of the core board; and a second circuit structure is disposed on the first circuit structure on the first side of the core board and covers the wiring element, so that the wiring element is embedded in the second circuit structure, and the second circuit structure electrically connects the wiring element and the first circuit layer.

2. The packaging substrate as described in claim 1, wherein, The wiring element is attached to the first wiring structure by means of an adhesive layer.

3. The packaging substrate as described in claim 2, wherein, The adhesive layer is formed on the entire surface of the first circuit structure.

4. The packaging substrate as described in claim 1, wherein, The second circuit structure is replicated on the first circuit structure on the second side of the core plate.

5. A method for manufacturing a packaging substrate, comprising: A core plate is provided, having a core layer defining a first side and a second side opposite to each other and having a plurality of through holes penetrating the first side and the second side, and at least one conductive post formed in the through holes to connect the first side and the second side. A first circuit structure is formed on the first side and the second side respectively. The first circuit structure has at least one first dielectric layer and a first circuit layer that is bonded to the first dielectric layer and electrically connected to the conductive post. The first dielectric layer is filled in the plurality of through holes, and a first cone-shaped post and a second cone-shaped post extending into the through holes are formed in the first dielectric layer on the first side and the second side respectively. The cone apex of the first cone-shaped post is connected to the cone apex of the second cone-shaped post to form the conductive post extending from the surface of the first dielectric layer on the first side to the surface of the first dielectric layer on the second side. A wiring element is disposed on a first circuit structure on a first side of the core board; and a second circuit structure is formed on the first circuit structure on the first side of the core board, such that the second circuit structure covers the wiring element, so that the wiring element is embedded in the second circuit structure, and the second circuit structure electrically connects the wiring element to the first circuit layer.

6. The method for manufacturing the packaging substrate as described in claim 5, wherein, The wiring element is attached to the first wiring structure by means of an adhesive layer.

7. The method for manufacturing the packaging substrate as described in claim 6, wherein, The adhesive layer is formed on the entire surface of the first circuit structure.

8. The method for manufacturing the packaging substrate as described in claim 5, wherein, The second circuit structure is replicated on the first circuit structure on the second side of the core plate.

Images