Carrier tape for loading chips

TW202637795APending Publication Date: 2026-09-163M INNOVATIVE PROPERTIES CO
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Patent Information

Application Number
TW114150096
Authority / Receiving Office
TW · TW
Patent Type
Applications
Current Assignee / Owner
Priority Date
2024-12-20
Filing Date
2025-12-19
Publication Date
2026-09-16

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    Figure TWG2TA001076841_003
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Abstract

Provided in the present invention is a carrier tape for loading chips, including: a first structural unit layer, including a first substrate, a first adhesive layer, and a releasable adhesive layer stacked in sequence; a second structural unit layer, including a plurality of through holes; and a third structural unit layer, including a second substrate and a second adhesive layer stacked in sequence, wherein: the first structural unit layer, the through holes, and the third structural unit layer form a plurality of spaces; and the size of the releasable adhesive layer in a width direction of the first structural unit layer is smaller than the size of the first adhesive layer in the width direction of the first structural unit layer, so that two ends of the first adhesive layer in the width direction of the first structural unit layer adhere to the second structural unit layer. According to the technical solution of the present invention, chips are adhesively affixed by means of providing a releasable adhesive layer, so that the chips can be conveniently removed from the carrier tape while preventing damage to the chips, especially to micro-bumps thereof, during transportation and handling, thereby simplifying a chip mounting process.
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