Thin film resistor and method of forming the same

Abstract

A thin film resistor and a method of forming the same are provided. The method includes forming an insulated oxide film on an upper surface of a substrate; forming a pair of first inner electrode on two ends of the insulated oxide film; performing a DC multi-target hybrid sputtering operation to deposit a resistor layer on a portion of the insulated oxide film and a portion of the pair of first inner electrode; performing a RF-DC hybrid sputtering operation to deposit a doping layer over the resistor layer; performing an annealing operation so as to oxidize the doping layer to an oxidized doping film; and forming a passivation layer on the oxidized doping film. Therefore, resistance and resistivity of the thin film resistor can be controlled.

Description

Thin film resistors and their manufacturing methods This invention relates to a thin-film resistor and a method for manufacturing the same, and more particularly to a thin-film resistor and a method for manufacturing the same by forming a resistive layer using a DC multi-target hybrid sputtering operation. In conventional thin-film resistors, the resistive layer is formed by sputtering a single alloy target; therefore, the material composition of the target determines most of the resistance characteristics. The temperature-dependent resistivity of the sputtered resistive layer can be adjusted using high-temperature annealing. However, the resistivity of the resistive layer is limited by the target material; therefore, to increase the resistance value, the thin film pattern must be adjusted. The pattern adjustment is limited by the adjustable area; therefore, to achieve a higher resistance value in a conventional thin-film resistor, the target material must be changed. If the target material does not have a higher resistivity, the thin-film resistor cannot achieve a higher resistance value. In view of this, there is an urgent need to provide a thin-film resistor and its manufacturing method to adjust the resistance value of the thin-film resistor. One aspect of the present invention is to provide a method for manufacturing a thin-film resistor, which utilizes a DC multi-target hybrid sputtering operation to deposit a resistive layer containing different metals, thereby achieving the effect of controlling the resistance value of the thin-film resistor. Another aspect of the present invention is to provide a thin-film resistor, which is prepared using the above method. According to one aspect of the present invention, a method for manufacturing a thin-film resistor is provided. This method includes forming an insulating oxide film on an upper surface of a substrate; forming a first inner electrode pair on both ends of the insulating oxide film; performing a DC multi-target hybrid sputtering operation to deposit a resistive layer on portions of the insulating oxide film and the first inner electrode pair, wherein the DC multi-target hybrid sputtering operation includes sputtering a nickel-chromium alloy, tantalum metal, and molybdenum metal; performing a radio frequency-DC hybrid sputtering operation to deposit a doped layer on the resistive layer, wherein the radio frequency-DC hybrid sputtering operation includes radio frequency sputtering of silicon and DC sputtering of aluminum; performing an annealing operation to form an oxide-doped thin film; and forming a passivation layer on the oxide-doped thin film. According to one embodiment of the present invention, the operation of forming the insulating oxide film includes: forming a sputtered layer on a substrate, wherein the sputtered layer comprises tantalum or silicon; and sintering the sputtered layer to form an insulating oxide film, wherein the insulating oxide film comprises tantalum oxide or silicon oxide. According to one embodiment of the present invention, in the above-mentioned DC multi-target hybrid sputtering operation, the sputtering power of tantalum metal is 60% to 100% of the sputtering power of nickel-chromium alloy, and the sputtering power of molybdenum metal is 5% to 30% of the sputtering power of nickel-chromium alloy. According to one embodiment of the present invention, in the above-described RF-DC hybrid sputtering operation, the sputtering power of aluminum is 20% to 50% of the sputtering power of silicon. According to one embodiment of the present invention, based on a resistive layer weight of 100 wt%, the resistive layer comprises 45 wt% to 75 wt% of a nickel-chromium alloy; 20 wt% to 40 wt% of tantalum; and 5 wt% to 15 wt% of molybdenum. According to one embodiment of the present invention, the weight ratio of aluminum to silicon in the doped layer is 1:1 to 1:5. According to one embodiment of the present invention, the method further includes forming a first insulating protective layer on a passivation layer; and forming a second inner electrode pair on both ends of an insulating oxide film, covering a portion of the first inner electrode pair and the first insulating protective layer. According to one embodiment of the present invention, the method further includes forming a second insulating protective layer on the exposed portion of the first insulating protective layer and on the portion of the second inner electrode pair. According to one embodiment of the present invention, the method further includes forming a back electrode pair at both ends on the lower surface of the substrate; and forming an outer electrode pair extending from the second insulating protective layer along both sides of the substrate to connect the back electrode pair. According to another aspect of the present invention, a thin-film resistor is provided, which is prepared by the above method. The thin-film resistor and its manufacturing method of the present invention are used to deposit a resistor layer containing different metals by means of DC multi-target hybrid sputtering operation, and to deposit a doped layer on the resistor layer by means of radio frequency-DC hybrid sputtering operation, so as to achieve the effect of controlling the resistance value and resistivity of the thin-film resistor. The following disclosure provides numerous different embodiments or illustrations to implement various features of the invention. The specific examples of components and configurations described below are for the purpose of simplifying this disclosure. These are, of course, merely illustrative and are not intended to be limiting. For example, a description of a first feature formed on or above a second feature includes embodiments where the first and second features are in direct contact, as well as embodiments where other features are formed between the first and second features such that the first and second features are not in direct contact. Furthermore, element symbols and / or letters are repeated in various specific examples in this disclosure. This repetition is intended to simplify and clarify the description and does not imply a relationship between the various discussed embodiments and / or configurations. Furthermore, spatially relative terms, such as "beneath," "below," "lower," "above," and "upper," are used to easily describe the relationship between a part or feature depicted in the drawings and other parts or features. In addition to the directions depicted in the drawings, spatially relative terms also include different orientations of the elements during use or operation. The device can be oriented in other ways (rotated 90 degrees or in other orientations), and the spatially relative descriptions used in this disclosure can also be interpreted in this way. The manufacture and use of embodiments of the present invention are discussed in detail below. However, it will be understood that the embodiments provide many applicable inventive concepts that can be implemented in a wide variety of specific contexts. The specific embodiments discussed are for illustrative purposes only and are not intended to limit the scope of the invention. As used in this invention, "around," "about," "approximately," or "substantially" generally mean within 20 percent, 10 percent, or 5 percent of the stated value or range. As described above, the present invention provides a thin film resistor and its manufacturing method, which utilizes a DC multi-target hybrid sputtering operation to deposit a resistor layer containing different metals, and uses an RF-DC hybrid sputtering operation to deposit a doped layer on the resistor layer, thereby achieving the effect of controlling the resistance value and resistivity of the thin film resistor. Please refer to Figure 1, which is a cross-sectional view illustrating a thin-film resistor 100 according to some embodiments of the present invention. The thin-film resistor 100 includes a substrate 105. In some embodiments, the material of the substrate 105 may include aluminum oxide (Al₂O₃). 2O 3) Ceramic materials such as aluminum nitride (AlN), beryllium oxide (BeO), magnesium oxide (MgO), and alumina-doped zirconium (ZTA) or combinations thereof. The thin-film resistor 100 includes an insulating oxide film 110 disposed on the upper surface 105A of the substrate 105. In some specific examples, the insulating oxide film 110 includes tantalum oxide (Ta). 2O 5) or silicon oxide (SiO2) 2). The insulating oxide film 110 completely covers the upper surface 105A of the substrate 105 to reduce the surface roughness of the substrate 105, thereby increasing the adhesion between the substrate 105 and the resistive layer 130. The thin-film resistor 100 includes a first inner electrode pair 120, a resistive layer 130, an oxide-doped thin film 135, a passivation layer 140, a first insulating protective layer 150, a second inner electrode pair 160, and a second insulating protective layer 170 disposed on an insulating oxide film 110. The first inner electrode pair 120 is disposed at both ends of the insulating oxide film 110. In some embodiments, the material of the first inner electrode pair 120 includes glass, silver, or an electrode paste of silver and palladium, or a combination thereof. The resistive layer 130 is disposed on the portion of the insulating oxide film 110 not covered by the first inner electrode pair 120 and on the portion of the first inner electrode pair 120. In some embodiments, based on the resistive layer 130 being 100 wt%, the resistive layer 130 comprises approximately 45 wt% to approximately 75 wt% of a nickel-chromium alloy, approximately 20 wt% to approximately 40 wt% of tantalum, and approximately 5 wt% to approximately 15 wt% of molybdenum. The nickel-chromium alloy is the main component of the resistive layer 130; therefore, the nickel-chromium alloy content within the aforementioned range allows the resistive layer 130 to have a suitable resistance value; the inclusion of tantalum within the aforementioned range allows the resistive layer 130 to have water-resistant properties; and the inclusion of molybdenum within the aforementioned range allows the resistance value of the resistive layer 130 to be adjusted. In some embodiments, the thickness of the resistive layer 130 is approximately 0.02 μm to approximately 0.5 μm. This thickness range allows the resistive layer 130 to have a suitable resistivity. An oxide-doped thin film 135 is disposed on the resistive layer 130. In some embodiments, the oxide-doped thin film 135 comprises silicon oxide and aluminum oxide. Some of the silicon oxide and aluminum oxide in the oxide-doped thin film 135 also diffuse into the resistive layer 130, thereby adjusting the temperature coefficient of resistance (TCR) and resistivity of the resistive layer 130. The passivation layer 140 is configured to completely cover the resistive layer 130. In some embodiments, the passivation layer 140 comprises an insulating material, such as silicon oxide, tantalum oxide, silicon nitride, or a combination thereof. The first insulating protective layer 150 is disposed on the passivation layer 140 and on a portion of the first inner electrode pair 120. In some embodiments, the material of the first insulating protective layer 150 comprises resin, epoxy resin, epoxy resin containing inorganic fillers, or a combination thereof. The second inner electrode pair 160 is disposed on both ends of the insulating oxide film 110 and covers a portion of the first inner electrode pair 120 and the first insulating protective layer 150. The second inner electrode pair 160 protects the first inner electrode pair 120 from the intrusion of sulfur-containing gases. In some embodiments, the material of the second inner electrode pair 160 comprises epoxy resin and silver. The second insulating protective layer 170 is disposed on the portion of the first insulating protective layer 150 not covered by the second inner electrode pair 160 and on the portion of the second inner electrode pair 160. In some embodiments, the material of the second insulating protective layer 170 includes resin, epoxy resin, epoxy resin containing inorganic fillers, or a combination thereof. The thin-film resistor 100 further includes a back electrode pair 180 disposed on the lower surface 105B of the substrate 105. In some embodiments, the back electrode pair 180 is disposed at both ends of the lower surface 105B of the substrate 105. In some embodiments, the material of the back electrode pair 180 includes epoxy resin and silver. The thin-film resistor 100 further includes a bonding layer 185 and an external electrode pair 190. The bonding layer 185 is disposed on a side 105C of the substrate 105, and the external electrode pair 190 extends from the second insulating protective layer 170 along the bonding layer 185 to cover the back electrode pair 180. In some embodiments, the material of the bonding layer 185 includes a nickel-chromium alloy (NiCr). The external electrode pair 190 includes a nickel layer 190A and a tin layer 190B. Figures 2A to 2I are top views illustrating intermediate stages of the fabrication process of the thin-film resistor 100 according to some embodiments of the present invention, wherein Figures 2A to 2H are top views viewed downwards from the upper surface 105A of the substrate 105 (refer to Figure 1), and Figure 2I is a top view viewed downwards from the lower surface 105B of the substrate 105. The fabrication process of the thin-film resistor 100 will be described below using Figures 2A to 2I. First, referring to Figures 1 and 2A simultaneously, an insulating oxide film 110 is formed on the substrate 105. In some embodiments, the formation of the insulating oxide film 110 includes first forming a sputtered layer on the substrate 105, and then sintering the sputtered layer to form the insulating oxide film 110. In the foregoing embodiments, the thickness of the sputtered layer is about 0.02 μm to about 0.1 μm, which ensures complete oxidation after sintering. In some specific examples, the sputtered layer contains tantalum (Ta) or silicon (Si), so the insulating oxide film 110 contains tantalum oxide (Ta). 2O 5) or silicon oxide (SiO2) 2) Tantalum oxide and silicon oxide have a better affinity for the subsequently formed resistive layer 130. Next, first internal electrodes 120A and 120B (collectively referred to as the first internal electrode pair 120) are formed on both ends of the insulating oxide film 110. In some embodiments, the first internal electrode pair 120 is formed by printing and sintering. The substrate 105 has a length L along its long side in the X direction and a width W along its short side in the Y direction, wherein the first internal electrode pair 120 is disposed on both ends of the long side of the substrate 105. The first internal electrodes 120B and 120A each have a length CL along the X direction and a width CW along the Y direction. In some embodiments, the length CL is about 1 / 5 to about 1 / 3 of the length L, and the width CW is about 4 / 5 to about 1 times the width W. Referring to Figure 2B, a masking layer 210A is formed on the periphery of the insulating oxide film 110 and a portion of the first inner electrode pair 120, exposing the area to be plated 210B. In some embodiments, the masking layer 210A is a removable glass ink, and the masking layer 210A can be formed by means of, for example, printing, coating, or lamination. In some embodiments, the length RL of the area to be plated 210B in the X direction is about 1 / 4 to about 3 / 4 times the length L, and the width RW in the Y direction is about 2 / 5 to about 4 / 5 times the width W. Next, a DC multi-target hybrid sputtering operation is performed on the surface shown in FIG. 2B to deposit a resistive layer 130. In some embodiments, the DC multi-target hybrid sputtering operation includes sputtering a nickel-chromium alloy (NiCr). 44 The gas used in the DC multi-target hybrid sputtering operation is argon, and the pressure in the sputtering chamber is approximately 5 × 10⁻⁶. -3 torr to approximately 8×10 -2 In some embodiments, the sputtering power of tantalum metal is about 60% to about 100% of the sputtering power of nickel-chromium alloy, and the sputtering power of molybdenum metal is about 5% to about 30% of the sputtering power of nickel-chromium alloy. With the aforementioned sputtering power, the resulting resistive layer 130 can contain about 45 wt% to about 75 wt% of nickel-chromium alloy, about 20 wt% to about 40 wt% of tantalum, and about 5 wt% to about 15 wt% of molybdenum. As described above, this specific content range allows the resistive layer 130 to have suitable resistivity and water resistance properties. In some specific examples, the sputtering power of the nickel-chromium alloy is 0.6 kW, the sputtering power of the tantalum metal is 0.6 kW, and the sputtering power of the molybdenum metal is 0.15 kW; thus, the resulting resistive layer 130 comprises approximately 55 wt% nickel-chromium alloy, 37 wt% tantalum and 8 wt% molybdenum. Then, a radio frequency (RF)-direct current (DC) hybrid sputtering operation is performed to deposit a doped layer on the resistive layer 130. The RF-DC hybrid sputtering operation requires first heating the substrate 105 in a cavity to approximately 150°C to approximately 250°C, a temperature lower than the curing temperature of the glass ink in the mask layer 210A. Next, the RF target and DC target are turned on for sputtering. In some embodiments, the RF-DC hybrid sputtering operation includes RF sputtering of a silicon target and DC sputtering of an aluminum target, wherein the power of the aluminum target is approximately 20% to approximately 50% of the power of the silicon target. In this embodiment, the weight ratio of aluminum to silicon in the doped layer is approximately 1:1 to approximately 1:5. The aforementioned power range and weight ratio of aluminum and silicon contribute to the formation of a doped film with a suitable thickness. In some embodiments, the average thickness of the doped film is approximately 0.005 μm to approximately 0.05 μm, which provides a better doping effect. After the doped layer is formed, the masking layer 210A is removed using a chemical solvent or deionized water to expose a portion of the first internal electrode pair 120. Referring to Figure 2C, the doped layer is annealed in an atmospheric high-temperature furnace at a temperature of approximately 300°C to approximately 600°C and held at that temperature for approximately 2 hours to approximately 6 hours. This annealing process allows some of the silicon and aluminum in the doped layer to diffuse into the resistive layer 130, forming silicon oxide (SiO₂). 2) with aluminum oxide (Al) 2O 3) An oxide-doped thin film 135 is also formed on the resistive layer 130. Forming the oxide-doped thin film 135 through annealing helps to adjust the temperature resistivity and resistivity of the thin film resistor 100. As shown in Figure 300, different annealing temperatures yield different temperature resistivityes. In some specific examples, when the annealing temperature is 450°C and the holding time is 3 hours, the temperature resistivity of the thin film resistor 100 is less than 50 ppm, and the resistivity is 1383 μΩ-cm. Next, a resistance adjustment step is performed on the resistive layer 130 and the oxide-doped thin film 135 above it, which can be done by laser or physical processing to adjust the resistance value. After the resistance adjustment step, atmospheric pressure low-temperature heat treatment can be performed to eliminate the thermal effects of physical processing and micro-oxidation at the cross-section of the resistor processing. In some embodiments, the atmospheric pressure low-temperature heat treatment is performed at a temperature of about 200°C to about 350°C and held at that temperature for about 0.5 hours to about 3 hours. In one specific example, after the resistance adjustment step is performed by laser, a heat treatment is performed at a temperature of 270°C for 1.5 hours. Referring to Figure 2D, a mask layer 220A is formed on the periphery of the insulating oxide film 110 and a portion of the first inner electrode pair 120, exposing the passivation region 220B. In some embodiments, the mask layer 220A is a removable ink or photoresist, which can be formed by means of, for example, printing, coating, or lamination. The size of the passivation region 220B must be such that the subsequently formed passivation layer 140 completely covers the resistive layer 130 (and the oxide-doped film 135). In some embodiments, the length PL of the passivation region 220B in the X direction is about 3 / 4 to about 4 / 5 times the length L, and the width PW in the Y direction is about 4 / 5 to about 1 times the width W. Next, a passivation layer 140 is formed on the oxide-doped thin film 135 and the mask layer 220A. In some embodiments, the passivation layer 140 may be formed by sputtering or chemical vapor deposition. Then, the mask layer 220A is removed using a chemical solvent or deionized water to form the passivation layer 140 on a portion of the oxide-doped thin film 135 and the first internal electrode pair 120, as shown in FIG2E. Referring to Figure 2F, a first insulating protective layer 150 is formed to cover the passivation layer 140. The first insulating protective layer 150 is used to protect the passivation layer 140 and the first inner electrode pair 120. In some embodiments, the first insulating protective layer 150 is formed by printing or photolithography. In some embodiments, the length G1L of the first insulating protective layer 150 in the X direction is from (length L-250) μm to (length L-100) μm, and the width G1W in the Y direction is from about 4 / 5 to about 1 times the width W. Referring to Figure 2G, second inner electrodes 160A and 160B (collectively referred to as the second inner electrode pair 160) are formed on both ends of the insulating oxide film 110, covering portions of the first inner electrode pair 120 and the first insulating protective layer 150. In some embodiments, the second inner electrode pair 160 may be formed by printing. The second inner electrodes 160A and 160B each have a length C2L along the X direction and a width C2W along the Y direction. In some embodiments, the length C2L is about 1 / 4 to about 1 / 3 of the length L, and the width C2W is about 4 / 5 to about 1 times the width W. Referring to Figure 2H, a second insulating protective layer 170 is formed on the first insulating protective layer 150 and the second inner electrode pair 160. The second insulating protective layer 170 is used to protect a portion of the first insulating protective layer 150 and the second inner electrode pair 160. In some embodiments, the first insulating protective layer 150 is formed by printing or photolithography. In some embodiments, the length G2L of the second insulating protective layer 170 in the X direction is about 1 / 3 to about 2 / 3 times the length L, and the width G2W in the Y direction is about 4 / 5 to about 1 times the width W. Referring to FIG2I, back electrodes 180A and 180B (collectively referred to as back electrode pair 180) are formed on both ends of the lower surface 105B of the substrate 105. In some embodiments, back electrodes 180A and 180B are formed by printing. Back electrodes 180A and 180B each have a length BCL along the X direction and a width BCW along the Y direction. In some embodiments, the length BCL is about 1 / 4 to about 1 / 3 of the length L, and the width BCW is about 4 / 5 to about 1 times the width W. Please refer back to Figure 1. After the processes shown in Figures 2H and 2I are completed, an interconnect layer 185 is formed on the side 105C of the substrate 105. In some embodiments, the interconnect layer 185 is formed by sputtering. Next, a nickel layer 190A and a tin layer 190B (i.e., the external electrode pair 190) are sequentially formed, extending from the second insulating protective layer 170 along the interconnect layer 185 to cover the back electrode pair 180. In some embodiments, the external electrode pair 190 is formed by electroplating. Based on the above, the present invention provides a thin film resistor and a method for manufacturing the same, which utilizes a DC multi-target hybrid sputtering operation to deposit a resistor layer containing different metals, and uses an RF-DC hybrid sputtering operation to deposit a doped layer on the resistor layer, thereby achieving the effect of controlling the resistance value and resistivity of the thin film resistor. Although the present invention has been disclosed above with reference to several embodiments, it is not intended to limit the present invention. Anyone with ordinary knowledge in the technical field to which this invention pertains may make various modifications and refinements without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be determined by the appended claims. 100: Thin film resistor; 105: Substrate; 105A: Upper surface; 105B: Lower surface; 105C: Side portion; 110: Insulating oxide film; 120: First inner electrode pair; 120A, 120B: First inner electrode; 130: Resistive layer; 135: Oxide-doped thin film; 140: Passivation layer; 150: First insulating protective layer; 160: Second inner electrode pair; 160A, 160B: Second inner electrode; 170: Second insulating protective layer; 180: Back electrode. For 180A, 180B: Back electrode; 185: Connector layer; 190: External electrode; 190A: Nickel layer; 190B: Tin layer; 210A: Mask layer; 210B: Area to be plated; 220A: Mask layer; 220B: Area to be passivated; 300: Relationship diagram; L, CL, RL, PL, G1L, C2L, G2L, BCL: Length; W, CW, RW, PW, G1W, C2W, G2W, BCW: Width; X, Y: Direction. A better understanding of the present disclosure will be achieved by reading the following detailed description in conjunction with the accompanying drawings. It should be noted that, as is standard practice in the industry, many features are not drawn to scale. In fact, the dimensions of many features can be arbitrarily scaled for clarity of discussion. Figure 1 is a cross-sectional view illustrating a thin-film resistor according to some embodiments of the present invention. Figures 2A to 2I are top views illustrating intermediate stages in the manufacturing process of a thin-film resistor according to some embodiments of the present invention. Figure 3 is a graph showing the relationship between the temperature resistivity and annealing temperature of a thin-film resistor according to some embodiments of the present invention. Domestic storage information (please note in order of storage institution, date, and number): None. International storage information (please note in order of storage country, institution, date, and number): None. 100: Thin film resistor 105:Substrate 105A: Top surface 105B: Lower surface 105C: Side 110: Insulating oxide film 120: First internal electrode pair 130: Resistive layer 135: Oxide-doped thin films 140: Passivation layer 150: First insulating protective layer 160: Second internal electrode pair 170: Second insulating protective layer 180: Back electrode pair 185: Connector Layer 190: External electrode pair 190A: Nickel layer 190B: Tin layer

Claims

1. A method for manufacturing a thin-film resistor includes: forming an insulating oxide film on an upper surface of a substrate; forming a first internal electrode pair at both ends of the insulating oxide film; performing a DC multi-target hybrid sputtering operation to deposit a resistive layer on a portion of the insulating oxide film and a portion of the first internal electrode pair, wherein the DC multi-target hybrid sputtering operation includes sputtering a nickel-chromium alloy, tantalum metal, and molybdenum metal; performing a radio frequency-DC hybrid sputtering operation to deposit a doped layer on the resistive layer, wherein the radio frequency-DC hybrid sputtering operation includes radio frequency sputtering of silicon and DC sputtering of aluminum; performing an annealing operation to form an oxide-doped thin film; and forming a passivation layer on the oxide-doped thin film. The method for manufacturing a thin-film resistor as described in claim 1, wherein the operation of forming the insulating oxide film comprises: forming a sputtered layer on the substrate, wherein the sputtered layer comprises tantalum or silicon; and sintering the sputtered layer to form the insulating oxide film, wherein the insulating oxide film comprises tantalum oxide or silicon oxide. The method for manufacturing a thin-film resistor as claimed in claim 1, wherein in the DC multi-target hybrid sputtering operation, the sputtering power of one of the tantalum metals is 60% to 100% of the sputtering power of one of the nickel-chromium alloys, and the sputtering power of one of the molybdenum metals is 5% to 30% of the sputtering power of the nickel-chromium alloy. The method for manufacturing a thin-film resistor as described in claim 1, wherein in the RF-DC hybrid sputtering operation, the sputtering power of the aluminum is 20% to 50% of the sputtering power of the silicon. The method of manufacturing a thin-film resistor as described in claim 1, wherein the resistive layer comprises, based on a weight of 100 wt%, 45 wt% to 75 wt% of a nickel-chromium alloy; 20 wt% to 40 wt% of tantalum; and 5 wt% to 15 wt% of molybdenum. The method for manufacturing a thin-film resistor as described in claim 1, wherein the weight ratio of aluminum to silicon in the doped layer is 1:1 to 1:

5. The method for manufacturing a thin-film resistor as described in claim 1 further includes: forming a first insulating protective layer on the passivation layer; and forming a second inner electrode pair on both ends of the insulating oxide film, covering the first inner electrode pair and a portion of the first insulating protective layer. The method of manufacturing a thin-film resistor as described in claim 7 further includes: forming a second insulating protective layer on an exposed portion of the first insulating protective layer and a portion of the second inner electrode pair. The method of manufacturing a thin-film resistor as described in claim 8 further includes: forming a back electrode pair at both ends of a lower surface of the substrate; and forming an outer electrode pair extending from the second insulating protective layer along both sides of the substrate to connect the back electrode pair. A thin-film resistor, which is produced by any one of claims 1 to 9.

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