Detection circuit and detection method

Abstract

A detection circuit for a driving circuit is provided. The detection circuit includes a comparison circuit and a logic circuit. The comparison circuit is coupled to an output pin of the driving circuit. The comparison circuit is configured to receive an output from the output pin, compare the output signal with a first reference signal level to generate a first comparison result, and compare the output signal with a second reference signal level to generate a second comparison result The first reference signal level is different from the second reference signal level. The logic circuit is configured to generate a detection result according to the first comparison result and second comparison result in order to indicate whether a short circuit condition occurs between the output pin and an adjacent output pin of the driving circuit.

Description

Technical Field

[0001] This invention relates to a detection circuit and a detection method, and more particularly to a detection circuit and a detection method capable of detecting short circuit conditions. Prior Technology

[0002] To ensure the quality and functionality of electronic products with display functions, manufacturers typically perform multiple standard functional tests on the products during or after manufacturing to verify their proper operation. One of the most common problems encountered during electronic product troubleshooting is short circuit failure. Furthermore, display devices such as Liquid Crystal Displays (LCDs) are now widely used in various electronic products. Please refer to Figure 1, which is a schematic diagram of a conventional display device 1. The driving circuit 102 of the display device 1 can be used to drive the display panel 104 to display image data. The driving circuit 102 includes multiple output pins CGOUT for outputting corresponding output drive signals. Each output pin CGOUT is electrically connected to the display panel 104 via a Chip On Film (COF) package element 106 mounted on a thin film. In this way, the output signal can be transmitted from the output pin CGOUT of the driving circuit 102 to the display panel 104 via the COF package element 106. However, if the thin-film flip-chip package element 106 is damaged or broken, it will cause an unexpected electrical connection between two adjacent output pins, resulting in a short circuit between the two adjacent output pins, which in turn will cause circuit damage and malfunction or overheating of the display device 1. Therefore, how to provide a better fault detection solution for the display device has become one of the important issues in this technical field. Summary of the Invention

[0003] To address the aforementioned problems, the present invention provides a detection circuit and detection method capable of detecting short circuit conditions.

[0004] This invention provides a detection circuit for a driving circuit, comprising: a comparison circuit coupled to an output pin of the driving circuit, receiving an output signal from the output pin of the driving circuit, comparing the output signal with a first reference signal level to generate a first comparison result, and comparing the output signal with a second reference signal level to generate a second comparison result, wherein the first reference signal level is different from the second reference signal level; and a logic circuit coupled to the comparison circuit, used to generate a detection result based on the first comparison result and the second comparison result, to indicate whether a short circuit has occurred between the output pin of the driving circuit and an adjacent output pin.

[0005] This invention also provides a detection method for a driving circuit, comprising: receiving an output signal from an output pin of the driving circuit; comparing the output signal with a first reference signal level to generate a first comparison result; comparing the output signal with a second reference signal level to generate a second comparison result, wherein the first reference signal level is different from the second reference signal level; and generating a detection result based on the first comparison result and the second comparison result to indicate whether a short circuit has occurred between the output pin and an adjacent output pin in the driving circuit. Simple Explanation of the Diagram

[0006] Figure 1 is a schematic diagram of an existing display device. Figure 2 is a schematic diagram of a display device according to an embodiment of the present invention. Figure 3 is a schematic diagram of an embodiment of the detection circuit of the display device in Figure 2. Figure 4 is a schematic diagram of the output signal of the output pin in normal state and when a short circuit occurs according to an embodiment of the present invention. Figure 5 is a schematic diagram of the operation of the surge cancellation circuit of the detection circuit in an embodiment of the present invention. Figure 6 is a schematic diagram of the operation of the counting circuit of the detection circuit in an embodiment of the present invention. Figure 7 is a schematic diagram of an embodiment of the configuration and arrangement of the detection circuit in the display device of the present invention. Figure 8 is a schematic diagram of another embodiment of the detection circuit of the display device in Figure 2. Implementation

[0007] Certain terms are used in this specification and subsequent claims to refer to specific components. It will be understood by those skilled in the art that hardware manufacturers may use different names to refer to the same component. This specification and subsequent claims do not distinguish components by differences in name, but by differences in function. The term "comprising" throughout this specification and subsequent claims is an open-ended term and should be interpreted as "including but not limited to." Furthermore, the term "coupled" here includes any direct and indirect electrical connection means. Therefore, if a first device is described as coupled to a second device, it means that the first device can be directly electrically connected to the second device, or indirectly electrically connected to the second device through other devices or connection means.

[0008] Please refer to Figure 2, which is a schematic diagram of a display device 2 according to an embodiment of the present invention. The display device 2 can be applied to electronic products, such as smartphones, laptops, tablets, televisions, etc., but is not limited thereto. The display device 2 includes a driving circuit 20, a display panel 30, and a detection circuit 40. Depending on the design requirements, the display panel 30 can be any type of display panel, such as a liquid crystal display (LCD) panel, an organic light-emitting diode (OLED) display panel, a mini-LED display panel, or a micro-LED display panel, but is not limited thereto. The display panel 30 may include multiple pixels arranged in a matrix.

[0009] The driving circuit 20 may include output pins CGOUT[0] to CGOUT[n]. The driving circuit 20 is configured to generate output signals and outputs these signals via the output pins CGOUT[0] to CGOUT[n] to drive the display panel 30 for display operation. For example, the output pins CGOUT[0] to CGOUT[n] may be electrically connected to different gate lines (or scan lines) of the display panel 30. Each output signal can be output to the display panel 30 via the corresponding output pin. The output signals may include gate drive signals, gate driver on array (GOA) signals, scan signals, control signals, and / or any other drive or control signals capable of driving or controlling the pixels of the display panel 30. The driving circuit 20 may be implemented in an integrated circuit (IC) to become a display driver IC (DDIC). The driving circuit 20 may be a gate driver on array circuit or a gate in panel (GIP) circuit. Depending on the design requirements, the drive circuit 20 may include a gate driver, an array gate drive circuit, a source driver, a timing control circuit, and / or other drive circuits.

[0010] Detection circuit 40 can be coupled to drive circuit 20, and detection circuit 40 can determine which output pin of drive circuit 20 is short-circuited with its adjacent output pin based on the output signal output from the output pin of drive circuit 20. More specifically, detection circuit 40 can be coupled to any one of the output pins CGOUT[0] to CGOUT[n] of drive circuit 20, and receive the output signal from the coupled output pin. Detection circuit 40 is configured to determine whether a short circuit has occurred between the coupled output pin and its adjacent output pin based on the output signal from the coupled output pin. As shown in Figure 2, detection circuit 40 includes a comparator circuit 402, a logic circuit 404, a deglitch circuit 406, and a counting circuit 408. Comparator circuit 402 is coupled to an output pin of drive circuit 20 and is configured to receive an output signal from the coupled output pin. Comparison circuit 402 is configured to compare the output signal with a first reference signal level to produce a first comparison result and to compare the output signal with a second reference signal level to produce a second comparison result. The first reference signal level may be different from the second reference signal level. The signal level of the output signal may be a voltage level or a current level. The first reference signal level may be a first reference voltage or a first reference current, and the second reference signal level may be a second reference voltage or a second reference current.

[0011] Logic circuit 404 is coupled to comparator circuit 402 and configured to generate a detection result based on a first comparison result and a second comparison result, thereby indicating whether a short circuit has occurred at the output pin. Logic circuit 404 may be an XOR gate circuit or an OR gate circuit, but is not limited thereto. For example, the first reference signal level may be greater than the second reference signal level. When the first comparison result indicates that the output signal level is less than the first reference signal level, and the second comparison result indicates that the output signal level is greater than the second reference signal level, this means that the output signal level falls within the range between the first and second reference signal levels. Logic circuit 404 generates a detection result to indicate that a short circuit has occurred between the output pin of drive circuit 20 and its adjacent output pin.

[0012] In another embodiment, when the first comparison result indicates that the signal level of the output signal is greater than or equal to the first reference signal level, and the second comparison result indicates that the signal level of the output signal is greater than the second reference signal level, the logic circuit 404 generates a detection result to indicate that there is no short circuit between the output pin of the drive circuit 20 and its adjacent output pins. In another embodiment, when the first comparison result indicates that the signal level of the output signal is less than the first reference signal level, and the second comparison result indicates that the signal level of the output signal is less than or equal to the second reference signal level, the logic circuit 404 generates a detection result to indicate that there is no short circuit between the output pin of the drive circuit 20 and its adjacent output pins.

[0013] Please refer to Figure 3, which is a schematic diagram of an embodiment of the detection circuit 40 of the display device 2 in Figure 2. As shown in Figure 3, the comparison circuit 402 includes comparators 4022 and 4024. The comparison circuit and 4024 can be voltage comparators. In one embodiment, the first reference signal level can be a first reference voltage VRA, and the second reference signal level can be a second reference voltage VRB. The first reference voltage VRA can be different from the second reference voltage VRB. For example, the first reference voltage VRA can be greater than the second reference voltage VRB. For example, the first reference voltage VRA can be less than or equal to a gate high voltage VGH. For example, the first reference voltage VRA can be set between 0 volts and the gate high voltage VGH. For example, the second reference voltage VRB can be greater than or equal to a gate low voltage VGL. For example, the second reference voltage VRB can be set between 0 volts and the gate low voltage. During normal operation, the output signal SG can switch between the gate high voltage VGH and the gate low voltage VGL.

[0014] For ease of explanation, assume that the detection circuit 40 is coupled to an output pin (e.g., output pin CGOUT[1]) of the drive circuit 20 to detect whether a short circuit occurs between the output pin CGOUT[1] and its adjacent pin. A non-inverting input of the comparator 4022 is coupled to an output pin (e.g., output pin CGOUT[1]) of the drive circuit 20 to receive an output signal SG from the output pin CGOUT[1] of the drive circuit 20. An inverting input of the comparator 4022 is used to receive a first reference voltage VRA. The comparator 4022 is configured to compare a voltage VG from the output signal SG from the output pin CGOUT[1] with the first reference voltage VRA to generate a comparison result CT1, and output the comparison result CT1 to the logic circuit 404 via the output of the comparator 4022. A non-inverting input of comparator 4024 is coupled to an output pin (e.g., output pin CGOUT[1]) of driver circuit 20 to receive the output signal SG from output pin CGOUT[1]. An inverting input of comparator 4024 is used to receive a second reference voltage VRB. Comparator 4024 is configured to compare the voltage VG of the output signal SG with the second reference voltage VRB to generate a comparison result CT2, and the comparison result CT2 is output to logic circuit 404 via the output of comparator 4024.

[0015] For example, as shown in the upper half of Figure 4, during normal operation, the drive circuit 20 operates in a normal state, and the output signal SG of the output pins CGOUT[0]~CGOUT[3] can be switched between the gate high voltage VGH and the gate low voltage VGL. If the first reference voltage VRA is greater than the second reference voltage VRB, and the comparison result CT1 of comparator 4022 indicates that the voltage VG of the output signal SG is greater than or equal to the first reference voltage VRA, and the comparison result CT2 of comparator 4024 indicates that the voltage VG of the output signal SG is greater than the second reference voltage VRB, this means that the voltage VG of the output signal SG falls outside the range between the first reference voltage VRA and the second reference voltage VRB. In this way, the logic circuit 404 generates a detection result DT to indicate that there is no short circuit between the output pin CGOUT[1] of the drive circuit 20 and its adjacent output pin. When the comparison result CT1 of comparator 4022 indicates that the voltage VG of the output signal SG is less than the first reference voltage VRA, and the comparison result CT2 of comparator 4024 indicates that the voltage VG of the output signal SG is less than or equal to the second reference voltage VRB, this means that the voltage VG of the output signal SG falls outside the range between the first reference voltage VRA and the second reference voltage VRB. The logic circuit 404 generates a detection result DT to indicate that there is no short circuit between the output pin CGOUT[1] of the drive circuit 20 and its adjacent output pin.

[0016] For example, taking the output signal SG of the output pin CGOUT[1] as an example, assuming that the normal operating voltage of the gate high voltage VGH is 10 volts, the normal operating voltage of the gate low voltage VGL is -10 volts, the first reference voltage VRA can be set to 8 volts, and the second reference voltage VRB can be set to -8 volts. The logic circuit 404 includes a mutex OR gate circuit. In one embodiment, if the voltage VG of the detected output signal SG is 10 volts, the comparator 4022 outputs a comparison result CT1 of logic "1" to indicate that the voltage VG (e.g., 10 volts) is greater than the first reference voltage VRA (e.g., 8 volts). And, the comparator 4024 outputs a comparison result CT2 of logic "1" to indicate that the voltage VG (e.g., 10 volts) is greater than the second reference voltage VRB (e.g., -8 volts). Therefore, the logic circuit 404 generates a detection result DT of logic "0" to indicate that there is no short circuit between the output pin CGOUT[1] and its adjacent pins. In one embodiment, if the detected voltage VG of the output signal SG is -10 volts, comparator 4022 outputs a comparison result CT1 with logic "0" to indicate that the voltage VG (e.g., -10 volts) is less than the first reference voltage VRA (e.g., 8 volts), and comparator 4024 outputs a comparison result CT2 with logic "0" to indicate that the voltage VG (e.g., -10 volts) is less than the second reference voltage VRB (e.g., -8 volts). Therefore, logic circuit 404 generates a detection result DT with logic "0" to indicate that there is no short circuit between the output pin CGOUT[1] and its adjacent pins.

[0017] For example, as shown in the lower half of Figure 4, a short circuit occurs at output pin CGOUT[1], where output pin CGOUT[1] and output pin CGOUT[2] are short-circuited, resulting in a short circuit fault between output pin CGOUT[1] and output pin CGOUT[2]. The output voltage or signal amplitude of the output signals of both output pins CGOUT[1] and CGOUT[2] will be pulled to an unexpected intermediate value. The output signals SG of output pins CGOUT[0] and CGOUT[3] will switch between gate high voltage VGH and gate low voltage VGL. If the first reference voltage VRA is greater than the second reference voltage VRB, and the comparison result CT1 of comparator 4022 indicates that the voltage VG of the output signal SG is less than the first reference voltage VRA, and the comparison result CT2 of comparator 4024 indicates that the voltage VG of the output signal SG is greater than the second reference voltage VRB, this means that the voltage VG of the output signal SG falls within the range between the first reference voltage VRA and the second reference voltage VRB. In this way, the logic circuit 404 generates a detection result DT to indicate that a short circuit has occurred between the output pin CGOUT[1] of the drive circuit 20 and its adjacent output pin.

[0018] For example, if the detected voltage VG of the output signal SG is 5 volts, then comparator 4022 outputs a comparison result CT1 with logic "0" to indicate that the voltage VG (e.g., 5 volts) is less than the first reference voltage VRA (e.g., 8 volts). Comparator 4024 outputs a comparison result CT2 with logic "1" to indicate that the voltage VG (e.g., 5 volts) is greater than the second reference voltage VRB (e.g., -8 volts). Therefore, logic circuit 404 generates a detection result DT with logic "1" to indicate that a short circuit has occurred between the output pin CGOUT[1] and its adjacent pin. For example, if the detected voltage VG of the output signal SG is -5 volts, then comparator 4022 outputs a comparison result CT1 with logic "0" to indicate that the voltage VG (e.g., -5 volts) is less than the first reference voltage VRA (e.g., 8 volts), and comparator 4024 outputs a comparison result CT2 with logic "1" to indicate that the voltage VG (e.g., -5 volts) is less than the second reference voltage VRB (e.g., -8 volts). Therefore, logic circuit 404 generates a detection result DT of logic "1" to indicate that a short circuit has occurred between the output pin CGOUT[1] and its adjacent pin. When the voltage of the output signal is within the range between the first reference voltage VRA and the second reference voltage VRB, logic circuit 404 generates a detection result DT to indicate that a short circuit has occurred between the output pin CGOUT[1] and its adjacent pin.

[0019] In other words, due to the change in impedance between two adjacent output pins, a short circuit occurs between the two pins, causing the output voltage or signal amplitude of the output pin to be pulled to an unexpected intermediate value. This embodiment of the invention provides a comparison circuit 402 and a logic circuit 404 in the detection circuit 40 to determine whether a short circuit abnormality exists by detecting whether the output signal of the output pin falls within an unexpected intermediate range, thereby ensuring the functionality and reliability of the display device and improving maintenance efficiency.

[0020] Furthermore, during normal operation, the output signal SG can switch between gate high voltage VGH and gate low voltage VGL. If the rise time of the output signal's rising edge or the fall time of its falling edge is too long, the voltage level of the output signal's rising or falling edge may fall within the range between the first reference voltage VRA and the second reference voltage VRB. In this case, the rising or falling edge of the output signal may be misinterpreted as a short circuit. That is, during transient switching (e.g., the rising or falling edge of the output signal), incorrect detection results may be obtained due to waveform delay or interference. Referring again to Figures 2 and 3, the surge cancellation circuit 406 is coupled to the logic circuit 404 and configured to receive the detection result DT. The surge cancellation circuit 406 can generate a surge-cancelled detection result DDT based on the detection result DT. The surge cancellation circuit 406 can remove any detection result in the detection result DT that is determined based on the rising or falling edge of the output signal to generate a surge-cancelled detection result DDT.

[0021] For example, please refer to Figure 5, which is a schematic diagram of the operation of the surge cancellation circuit in the detection circuit of the present invention. As shown in Figure 5, the detection result DT generated by the logic circuit 404 includes detection results DT1 and DT2. Detection results DT1 and DT2 indicate that a short circuit has occurred between the output pin CGOUT[1] and its adjacent pin. Since the voltage level of the output signal at the rise time T1 (rising edge) is within the range between the first reference voltage VRA and the second reference voltage VRB, in this case, the logic circuit 404 may generate detection result DT1 to indicate that a short circuit has occurred based on the voltage level of the output signal at the rise time T1 (rising edge), thus causing a detection error. Similarly, when the voltage level of the output signal at the fall time T2 (falling edge) is within the range between the first reference voltage VRA and the second reference voltage VRB, the logic circuit 404 may generate detection result DT2 to indicate that a short circuit has occurred based on the voltage level of the output signal at the fall time T2 (falling edge).

[0022] As shown in Figure 5, the surge cancellation circuit 406 can remove the detection results DT1 and DT2 determined based on the rising edge during the rise time T1 and / or the falling edge during the fall time T2 of the output signal from the detection result DT, thereby generating the surge-cancelled detection result DDT. In this way, the surge-cancelled detection result DDT will not include erroneous detection results DT1 and DT2; erroneous detection results will be filtered out from the detection result DT, resulting in the surge-cancelled detection result DDT. That is, detection results caused by waveform delay or interference under transient conditions will be ignored and removed. Therefore, the surge cancellation circuit 406 of this embodiment can eliminate and correct detection errors caused during transient switching (rising edge or falling edge), thereby greatly improving the accuracy of short-circuit detection.

[0023] To ensure the accuracy of short-circuit detection and avoid unnecessary detection errors, in some embodiments, a counting circuit 408 can be used to determine whether a short circuit actually occurs on the detected output pin. Referring to Figures 2 and 3, the counting circuit 408 is coupled to the surge cancellation circuit 406 and configured to receive the surge cancellation detection result DDT. The counting circuit 408 can generate an advanced detection result based on the surge cancellation detection result DDT. The counting circuit 408 can determine whether a short circuit has occurred on the output pin CGOUT[1] within a predetermined number of consecutive frame periods based on the surge cancellation detection result DDT. The counting circuit 408 can determine whether a short circuit has occurred on the output pin CGOUT[1] within each frame period based on the surge cancellation detection result DDT. When the counting circuit 408 determines that a short circuit has occurred at the output pin CGOUT[1] within a predetermined number of consecutive frame periods, the counting circuit 408 can generate an advanced detection result to indicate that the short circuit has indeed occurred at the output pin CGOUT[1]. In this way, the counting circuit 408 can report the advanced detection result to the display device 2 for subsequent operation. When the counting circuit 408 determines that a short circuit has not occurred at the output pin CGOUT[1] within a predetermined number of consecutive frame periods, the counting circuit 408 can generate an advanced detection result to indicate that a short circuit has not occurred at the output pin CGOUT[1]. The counter circuit 408 may choose not to report the advanced detection result to the display device 2.

[0024] In another embodiment, the counting circuit 408 can be coupled to the logic circuit 404 to receive the detection result DT and generate an advanced detection result based on the detection result DT. The counting circuit 408 can determine whether a short circuit has occurred in the output pin CGOUT[1] within a predetermined number of consecutive frame periods based on the detection result DT.

[0025] Please refer to Figure 6, which is a schematic diagram of the operation of the counting circuit in the detection circuit of the present invention. For example, a predetermined number of consecutive frame periods can be set to three consecutive frame periods. As shown in part (a) of Figure 6, the detection result DDT (or detection result DT) after surge elimination indicates that a short circuit has occurred in the output pin CGOUT[1] during frame periods F1, F2 and F3. Therefore, the counting circuit 408 can determine that a short circuit has occurred in the output pin CGOUT[1] during three consecutive frame periods (e.g., frame periods F1 to F3) based on the detection result DDT or detection result DT after surge elimination. This indicates that a short circuit has been detected in the output pin CGOUT[1] during at least three consecutive frame periods. The counting circuit 408 can generate an advanced detection result to indicate that a short circuit has indeed occurred in the output pin CGOUT[1].

[0026] As shown in part (b) of Figure 6, the surge-cleared detection result DDT (or detection result DT) indicates that the output pin CGOUT[1] was short-circuited during frame periods F1 and F2 (i.e., two consecutive frame periods (less than three consecutive frame periods)). The surge-cleared detection result DDT (or detection result DT) indicates that the output pin CGOUT[1] was not short-circuited during frame periods F3 and F4. Therefore, the counting circuit 408 can determine from the surge-cleared detection result DDT or detection result DT that the output pin CGOUT[1] was not short-circuited within three consecutive frame periods, which indicates that there is a detection error. The counting circuit 408 can generate an advanced detection result to indicate that the output pin CGOUT[1] was not short-circuited.

[0027] It should be noted that setting the predetermined number of consecutive frame periods to three consecutive frame periods, as shown in Figure 6, is only one of many implementations of this invention. In another embodiment, the predetermined number can be any number greater than or equal to two, and the predetermined number can be preset. The predetermined number can also be set according to various design requirements and / or execution requirements.

[0028] Therefore, embodiments of the present invention can determine whether a short circuit has occurred based on the output signal of the output pin, according to the operation of the comparison circuit 402 and the logic circuit 404. Furthermore, embodiments of the present invention utilize a surge cancellation circuit 406 and / or a counting circuit 408 to provide a more accurate way to verify the short circuit detection results. In some embodiments, embodiments of the present invention can provide a surge cancellation circuit 406 to eliminate detection errors caused by transient switching cycles, thereby effectively improving the accuracy of short circuit detection. Embodiments of the present invention can also provide a counting circuit 408 to confirm whether the short circuit detection results are correct to ensure the accuracy of short circuit detection.

[0029] The detection circuit of this embodiment can be used to detect whether a short circuit occurs between any two adjacent output pins. When half of the output pins in the drive circuit 20 are equipped with corresponding detection circuits, it is possible to accurately determine which output pin in the drive circuit 20 has a short circuit. For example, the detection circuit can be set on the odd-numbered output pins of the drive circuit 20 or on the even-numbered output pins. For example, please refer to Figure 7. Figure 7 is a schematic diagram of an embodiment of the configuration of the detection circuit in the display device 2 of this embodiment. The detection circuits 40_1 to 40_3 can be coupled to the odd-numbered output pins CGOUT[1], CGOUT[3] and CGOUT[5] of the drive circuit 20 respectively (or coupled to the even-numbered output pins) to determine which output pin of the drive circuit 20 has a short circuit with its adjacent output pins based on the output signal of the output pin. Traditional detection methods can only determine that a short circuit has occurred among these output pins of the drive circuit, but cannot accurately determine which output pin has a short circuit. In contrast, the detection circuit of this embodiment can accurately determine which output pin of the drive circuit 20 is short-circuited.

[0030] Please refer to Figure 8. Figure 8 is a schematic diagram of another embodiment of the detection circuit 40 of the display device 2 in Figure 2. It is worth noting that since the detection circuit 40 in Figure 8 and the detection circuit 40 in Figure 3 have similar operation and function, for the sake of brevity, detailed descriptions are omitted here. The connection relationship of these components is shown in Figure 8 and will not be repeated here. For ease of explanation, assume that the detection circuit 40 is coupled to an output pin (e.g., output pin CGOUT[1]) of the drive circuit 20 and detects whether a short circuit occurs between the output pin CGOUT[1] and its adjacent pin. The first reference signal may be a first reference current IR1, and the second reference signal may be a second reference current IR2. As shown in Figure 8. The comparison circuit 402 includes voltage-to-current converters 802, 806, 808 and a current comparator 804. Voltage-to-current converter 802 is coupled to the output pin CGOUT[1] of the drive circuit 20 to receive the output signal SG from the output pin CGOUT[1] of the drive circuit 20 and converts a voltage VG of the output signal SG into a current IG. Voltage-to-current converter 806 is used to receive a first reference voltage VRA and convert the first reference voltage VRA into a first reference current IR1. Voltage-to-current converter 808 is used to receive a second reference voltage VRB that is different from the first reference voltage VRA and convert the second reference voltage VRB into a second reference current IR2. For example, the first reference voltage VRA may be greater than the second reference voltage VRB. The first reference current IR1 may be greater than the second reference current IR2. During normal operation, the output signal SG can switch between a gate high voltage VGH and a gate low voltage VGL. In addition, current comparator 804 is coupled to voltage-to-current converters 802, 806 and 808. Current comparator 804 is configured to compare the current IG in the output signal SG with a first reference current IR1 to generate a comparison result CT1, and output the comparison result CT1 to logic circuit 404. Current comparator 804 is configured to compare the current IG in the output signal SG with a second reference current IR2 to generate a comparison result CT2, and output the comparison result CT2 to logic circuit 404.

[0031] In one embodiment, the voltage-to-current converter 802 may include an operational amplifier 8022 and resistors R1 and R2. The first end of resistor R1 is coupled to the output pin CGOUT[1] of the driver circuit 20 to receive the output signal SG from the output pin CGOUT[1]. The second end of resistor R1 is coupled to the inverting input of the operational amplifier 8022. Resistor R2 is coupled between the inverting input and the output of the operational amplifier 8022. The non-inverting input of the operational amplifier 8022 is coupled to ground, and the output of the operational amplifier 8022 is used to output current IG to the current comparator 804. In one embodiment, voltage-to-current converters 802, 806, and 808 may be implemented using the same circuit architecture.

[0032] In one embodiment, the first reference current IR1 is greater than the second reference current IR2. When the comparison result CT1 of the current comparator 804 indicates that the current IG of the output signal SG is greater than or equal to the first reference current IR1, and the second comparison result CT2 of the current comparator 804 indicates that the current IG of the output signal SG is greater than the second reference current IR2, this indicates that the current IG of the output signal SG falls outside the range between the first reference current IR1 and the second reference current IR2. Based on this, the logic circuit 404 generates a detection result DT to indicate that there is no short circuit between the output pin CGOUT[1] and its adjacent pin. In another embodiment, when the comparison result CT1 of the current comparator 804 indicates that the current IG of the output signal SG is less than the first reference current IR1, and the second comparison result CT2 of the current comparator 804 indicates that the current IG of the output signal SG is less than or equal to the second reference current IR2, this indicates that the current IG of the output signal SG falls outside the range between the first reference current IR1 and the second reference current IR2. Therefore, logic circuit 404 generates detection result DT to indicate that there is no short circuit between output pin CGOUT[1] and its adjacent pin. In another embodiment, the first reference current IR1 is greater than the second reference current IR2. When the comparison result CT1 of current comparator 804 indicates that the current IG of output signal SG is less than the first reference current IR1, and the second comparison result CT2 of current comparator 804 indicates that the current IG of output signal SG is greater than the second reference current IR2, it means that the current IG of output signal SG falls within the range between the first reference current IR1 and the second reference current IR2. Therefore, logic circuit 404 generates detection result DT to indicate that there is a short circuit between output pin CGOUT[1] and its adjacent pin.

[0033] In summary, a change in impedance between two adjacent output pins can cause a short circuit, pulling the output voltage or signal amplitude to an unexpected intermediate value. Therefore, this embodiment of the invention provides a comparator circuit 402 and a logic circuit 404 to determine if a short circuit exists by detecting whether the output signal of the output pin falls within an unexpected intermediate range, thus ensuring the functionality and reliability of the display device and improving maintenance efficiency. More importantly, this embodiment of the invention utilizes surge cancellation circuitry and counting circuitry to more accurately detect short circuits, ensuring detection accuracy and avoiding unnecessary detection errors. The above description is only a preferred embodiment of the present invention. All equivalent changes and modifications made in accordance with the claims of the present invention shall be covered by the present invention.

[0034] 1,2: Display device 102,20: Drive circuit 106: Thin-film flip-chip packaged components 104,30: Display panel 106: Thin-film flip-chip packaged components 40, 40_1~40_3: Detection circuit 402: Comparator Circuit 4022, 4024: Comparators 404: Logic Circuit 406: Surge cancellation circuit 408: Counting Circuit 802, 806, 808: Voltage-to-current converters 8022: Operational Amplifier 804: Current Comparator CGOUT,CGOUT[0]~CGOUT[6],CGOUT[n-1],CGOUT[n]: Output pins CT1, CT2: Comparison Results DDT: Detection results after surge cancellation DT, DT1, DT2: Detection Results IG: Current IR1: First reference current IR2: Second reference current F1~F4: Frames R1, R2: Resistors SG: Output signal T1: Rise Time T2: Descent time VG: Voltage VGH: Gate High Voltage VGL: Gate Low Voltage VRA: First reference voltage VRB: Second Reference Voltage

Claims

1. A detection circuit for a drive circuit, comprising: A comparator circuit, coupled to an output pin of the driver circuit, receives an output signal from the output pin of the driver circuit, compares the output signal with a first reference signal level to generate a first comparison result, and compares the output signal with a second reference signal level to generate a second comparison result, wherein the first reference signal level is different from the second reference signal level; and a logic circuit, coupled to the comparator circuit, generates a detection result based on the first comparison result and the second comparison result to indicate whether a short circuit has occurred between the output pin of the driver circuit and an adjacent output pin.

2. The detection circuit as claimed in claim 1, wherein the first reference signal level is greater than the second reference signal level, wherein when the first comparison result shows that a signal level of the output signal is less than the first reference signal level, and the second comparison result shows that the signal level of the output signal is greater than the second reference signal level, the logic circuit generates the detection result to indicate that a short circuit has occurred between the output pin and the adjacent output pin in the drive circuit.

3. The detection circuit as claimed in claim 1, wherein the first reference signal level is a first reference voltage and the second reference signal level is a second reference voltage, wherein the comparison circuit includes: A first comparator, coupled to the output pin of the driving circuit, is used to receive the output signal and compare a voltage of the output signal with the first reference voltage to generate the first comparison result; and a second comparator, coupled to the output pin of the driving circuit, is used to receive the output signal and compare the voltage of the output signal with the second reference voltage to generate the second comparison result, wherein the first reference voltage is different from the second reference voltage.

4. The detection circuit as claimed in claim 3, wherein the first reference voltage is greater than the second reference voltage, wherein when the first comparison result shows that the voltage of the output signal is less than the first reference voltage and the second comparison result shows that the voltage of the output signal is greater than the second reference voltage, the logic circuit generates the detection result to indicate that a short circuit has occurred between the output pin and the adjacent output pin in the drive circuit.

5. The detection circuit as claimed in claim 3, wherein the first reference voltage is less than a gate high voltage and the second reference voltage is greater than a gate low voltage.

6. The detection circuit of claim 1, wherein the first reference signal level is a first reference current, the second reference signal level is a second reference current, the first reference current is different from the second reference current, wherein the comparison circuit includes: A first voltage-to-current converter, coupled to the output pin of the drive circuit, is used to receive the output signal and convert a voltage of the output signal into a current of the output signal; a second voltage-to-current converter is used to receive a first reference voltage and convert the first reference voltage into the first reference current; a third voltage-to-current converter is used to receive a second reference voltage and convert the second reference voltage into the second reference current; and a current comparator, coupled to the first voltage-to-current converter, the second voltage-to-current converter, and the third voltage-to-current converter, is used to compare the current of the output signal with the first reference current to generate the first comparison result, and to compare the current of the output signal with the second reference current to generate the second comparison result.

7. The detection circuit as claimed in claim 6, wherein the first reference current is greater than the second reference current, wherein when the first comparison result shows that the current of the output signal is less than the first reference current and the second comparison result shows that the current of the output signal is greater than the second reference current, the logic circuit generates the detection result to indicate that a short circuit has occurred between the output pin and the adjacent output pin in the drive circuit.

8. The detection circuit as claimed in claim 1, wherein the logic circuit includes: A mutual exclusion gate circuit, coupled to the comparator circuit, is used to generate the detection result based on the first comparison result and the second comparison result.

9. The detection circuit as claimed in claim 1, further comprising: A surge cancellation circuit, coupled to the logic circuit, is used to generate a surge-canceled detection result based on the detection result generated by the logic circuit. The surge cancellation circuit generates the surge-canceled detection result by removing the detection result determined based on a rising edge or a falling edge of the output signal from the detection result generated by the logic circuit.

10. The detection circuit as claimed in claim 1, further comprising: A counting circuit is used to determine whether a short circuit has occurred at the output pin within a predetermined number of consecutive frame periods based on the detection result or a detection result after surge suppression, and to generate an advanced detection result accordingly.

11. A detection method for a driving circuit, comprising: The driver circuit receives an output signal from an output pin; compares the output signal with a first reference signal level to generate a first comparison result; compares the output signal with a second reference signal level to generate a second comparison result, wherein the first reference signal level is different from the second reference signal level; and generates a detection result based on the first comparison result and the second comparison result to indicate whether a short circuit has occurred between the output pin and an adjacent output pin in the driver circuit.

12. The detection method as claimed in claim 11, wherein the first reference signal level is greater than the second reference signal level, wherein the detection method further comprises: When the first comparison result shows that a signal level of the output signal is less than the first reference signal level, and the second comparison result shows that the signal level of the output signal is greater than the second reference signal level, the detection result is generated to indicate that a short circuit has occurred between the output pin and the adjacent output pin in the drive circuit.

13. The detection method as claimed in claim 11, wherein the first reference signal level is a first reference voltage and the second reference signal level is a second reference voltage, wherein the detection method further comprises: The voltage of the output signal is compared with the first reference voltage to generate the first comparison result; And compare the voltage of the output signal with the second reference voltage to generate the second comparison result, wherein the first reference voltage is different from the second reference voltage.

14. The detection method as claimed in claim 13, wherein the first reference voltage is greater than the second reference voltage, wherein the detection method further comprises: When the first comparison result shows that the voltage of the output signal is less than the first reference voltage, and the second comparison result shows that the voltage of the output signal is greater than the second reference voltage, the detection result is generated to indicate that a short circuit has occurred between the output pin and the adjacent output pin in the drive circuit.

15. The detection method as claimed in claim 13, wherein the first reference voltage is less than a gate high voltage and the second reference voltage is greater than a gate low voltage.

16. The detection method as claimed in claim 11, wherein the first reference signal level is a first reference current, the second reference signal level is a second reference current, the first reference current being different from the second reference current, wherein the detection method further comprises: Convert the voltage of the output signal into the current of the output signal; Convert a first reference voltage into the first reference current; The second reference voltage is converted into the second reference current; and the current of the output signal is compared with the first reference current to generate the first comparison result, and the current of the output signal is compared with the second reference current to generate the second comparison result.

17. The detection method as claimed in claim 16, wherein the first reference current is greater than the second reference current, wherein the detection method further comprises: When the first comparison result shows that the current of the output signal is less than the first reference current and the second comparison result shows that the current of the output signal is greater than the second reference current, the detection result is generated to indicate that a short circuit has occurred between the output pin and the adjacent output pin in the drive circuit.

18. The detection method as described in claim 11, further comprising: The detection result is generated by a mutual exclusion or gate circuit based on the first comparison result and the second comparison result.

19. The detection method as described in claim 11, further comprising: The detection result is used to generate a surge-free detection result, which includes removing a detection result determined based on a rising edge or a falling edge of the output signal from the detection result generated based on the first comparison result and the second comparison result.

20. The detection method as described in claim 11, further comprising: Based on the detection result or the detection result after the surge has been eliminated, it is determined whether a short circuit has occurred in the output pin within a predetermined number of consecutive frame periods, and an advanced detection result is generated accordingly.

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