Virtualized parallel access architecture for flash memory

Abstract

A memory controller for controlling a flash memory includes a parallel accessing control circuit. The parallel accessing control circuit is coupled to a command and address (CA) bus, a first data bus, and a second data bus that are respectively coupled to a plurality of first memory units and a plurality of second memory units of the flash memory. The parallel accessing control circuit includes a CA sequencer configured to manage control signals and memory addresses that are transmitted over the CA bus; a first data input / output (DQ) sequencer configured to, through the first data bus, transmit / receive a first portion of encoded write / read data to / from one of first memory units; and a second DQ sequencer, configured to, through the second data bus, transmit / receive a second portion of the encoded write / read data to / from one of second memory units.

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