Solid-state storage device and method of dynamic quality-of-service management thereof

Abstract

A solid-state storage device is provided, which is electrically connectable to a host. The solid-state storage device includes a controller, a non-volatile memory, and a volatile memory. The volatile memory includes a submission queue and a wait queue. The controller is configured to fetch a plurality of access commands from the host, and record the access commands in the submission queue. The access commands include a plurality of write commands and a plurality of read commands. When the controller fetches a first write command of the write commands from the submission queue, the controller determines whether a read count of the read commands and a wait time from receiving the first write command meet a target condition. When the read count and the wait time meet the target condition, the controller performs the first write command. When the read count and the wait time fail to meet the target condition, the controller holds the first write command in the wait queue.

Description

Technical Field

[0001] This invention relates to solid-state storage devices, and more particularly to a solid-state storage device and a method for managing the dynamic quality of service of the same. Prior Technology

[0002] Solid-state storage (SSDs) use non-volatile memory (NDRAM) to store data, and with technological advancements, they have become widely used in various computer systems. However, due to the characteristics of NDRAM, the number of read and write operations on it is closely related to its lifespan. Furthermore, the ratio of read to write commands sent from the host to the SSD often varies significantly, indicating that the SSD needs to handle different system workloads. Traditional SSDs are often designed for specific system workloads, and when the system workload changes drastically, their performance often drops significantly, thus affecting their service quality. Summary of the Invention

[0003] Therefore, the present invention provides a solid-state storage device and a dynamic service quality management method thereof to solve the above problems.

[0004] In one embodiment, the present invention provides a solid-state storage device electrically connected to a host computer. The solid-state storage device includes a controller, non-volatile memory, and volatile memory. The volatile memory includes a commit queue and a wait queue. The controller obtains a plurality of access instructions from the host computer and records the access instructions in the commit queue, wherein the access instructions include a plurality of write instructions and a plurality of read instructions. When the controller obtains a first write instruction from the commit queue, the controller determines whether the read count value of the read instructions and the waiting time since receiving the first write instruction meet the target conditions. If the read count value and the waiting time meet the target conditions, the controller is configured to execute the first write instruction. If the read count value and the waiting time do not meet the target conditions, the controller retains the first write instruction in the wait queue.

[0005] In another embodiment, the present invention further provides a dynamic quality of service management method for a solid-state storage device electrically connected to a host, the solid-state storage device including a controller, a volatile memory and a non-volatile memory, the method comprising the following steps: obtaining a plurality of access instructions from the host using the controller, and recording the access instructions in a commit queue of the volatile memory, wherein the access instructions include a plurality of write instructions and a plurality of read instructions; when the controller obtains a first write instruction from the commit queue, determining whether a read count value of the read instructions and a waiting time from the receipt of the first write instruction meet a target condition; when the read count value and the waiting time meet the target condition, executing the first write instruction using the controller; and when the read count value and the waiting time do not meet the target condition, retaining the first write instruction in a wait queue of the volatile memory using the controller. Simple Explanation of the Diagram

[0006] Figure 1 is a block diagram of a computer system according to an embodiment of the present invention. Figure 2 is a schematic diagram showing that the programming program of the write instruction according to an embodiment of the present invention is interrupted by multiple read instructions. Figure 3 is a flowchart of a dynamic quality of service management method for solid-state storage devices according to an embodiment of the present invention. Figure 4 is a flowchart of the firmware executed by the controller according to an embodiment of the present invention. Figure 5 is a flowchart of the instruction control module according to the embodiment of Figure 4 of the present invention. Figure 6 is a flowchart of the reading quota control module according to the embodiment of Figure 4 of the present invention. Figure 7 is a flowchart of the instruction equalizer module according to the embodiment of Figure 4 of the present invention. Figures 8A and 8B are schematic diagrams illustrating how the controller adjusts the reference value REF and the reading limit under different conditions according to an embodiment of the present invention. Implementation

[0007] The following description is a preferred embodiment of the invention and is intended to describe the basic spirit of the invention, but is not intended to limit the invention. The actual scope of the invention must be understood by referring to the claims below.

[0008] It must be understood that the terms "comprising" and "including" used in this specification are used to indicate the presence of specific technical features, values, method steps, work processes, elements and / or components, but do not preclude the addition of more technical features, values, method steps, work processes, elements, components, or any combination thereof.

[0009] The use of terms such as "first," "second," and "third" in the scope of a patent application is to modify elements within the scope of the patent application. It is not intended to indicate a priority order, a prior relationship, or that one element precedes another, or the chronological order of the execution of method steps. It is only used to distinguish elements with the same name.

[0010] The term "Configured To" can describe or claim that various units, circuits, or other components are "configured to" perform one or more tasks. In such a context, the term "configured to" is used to imply a structure by indicating that such units / circuits / components include a structure (e.g., a circuit system) that performs one or more tasks during operation. Thus, even when the specified unit / circuit / component is not currently operational (e.g., not switched on), it can still be said that the unit / circuit / component is configured to perform the task. Such units / circuits / components used with the term "configured to" include hardware—e.g., circuits, memory (which stores executable program instructions to perform operations), etc. In addition, "configured to" can include generic structures (e.g., generic circuit systems) that are manipulated by software and / or firmware (e.g., FPGAs or general-purpose processors executing software) to perform one or more tasks to be performed. "Configured to" may also include adapting a manufacturing process (e.g., a semiconductor manufacturing equipment) to manufacture a device (e.g., an integrated circuit) adapted to perform or carry out one or more tasks.

[0011] Figure 1 is a block diagram showing a computer system according to an embodiment of the present invention.

[0012] As shown in Figure 1, the computer system 1 includes a solid-state storage device 10 and a host 20. The solid-state storage device 10 is electrically connected to the host 20 via a bus 11 for instruction and data transmission. In some embodiments, the bus 11 may be a Universal Serial Bus (USB), a Serial Advanced Technology Attachment (SATA) bus, a PCI Express (PCIe) bus, etc., but the present invention is not limited thereto.

[0013] Solid-state storage device 10 includes a controller 102, cache memory 104, volatile memory 106, non-volatile memory 108, and non-volatile memory 110. The controller 102, volatile memory 106, non-volatile memory 108, and non-volatile memory 110 are electrically connected to each other via an internal bus 101. The controller 102 is used to control data access to the cache memory 104, volatile memory 106, and non-volatile memory 108. In some embodiments, the controller 102 may be, for example, a general-purpose processor, a microcontroller, an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), etc., but the present invention is not limited thereto. Furthermore, the controller 102 is electrically connected to the non-volatile memory 108 through a data transmission interface 111. The data transmission interface 111 may be, for example, an Open NAND Flash Interface (ONFI), a Toggle Mode Interface, an embedded MultiMediaCard (eMMC), or a Universal Flash Storage (UFS) interface, but the present invention is not limited thereto.

[0014] Cache memory 104 includes, for example, static random access memory (SRAM), but the invention is not limited thereto. Volatile memory 106 includes, for example, dynamic random access memory (DRAM), but the invention is not limited thereto. In some embodiments, cache memory 104 and volatile memory 106 may be disposed outside the controller 102. In other embodiments, cache memory 104 and volatile memory 106 may be integrated into the controller 102.

[0015] The non-volatile memory 110 is, for example, a read-only memory used to record the firmware modules executed by the controller 102, such as the instruction control module 112, the read limit control module 114, and the instruction equalizer module 116, the functions of which will be described in detail later.

[0016] The host 20 includes, for example, a processor 202 and system memory 204, with the processor 202 electrically connected to the system memory 204. In some embodiments, the processor 202 may include, for example, a central processing unit (CPU), a general-purpose processor, a microprocessor, etc., but the invention is not limited thereto. Furthermore, the processor 202 includes a controller (not shown) for controlling data access to the system memory 204. The system memory 204 may include, for example, dynamic random access memory (DRAM), but the invention is not limited thereto.

[0017] In some embodiments, the host 20 may support, for example, the Non-Volatile Memory Communication Protocol (NVM Express, NVME), and the system memory 204 is configured with a submission queue 2041, a completion queue 2042, and a data register 2043. The submission queue 2041 is used to record access commands issued by the processor 202, and the completion queue 2042 is used to record the status of the solid-state storage device 10 in response to completed access commands. The data register 2043 is used to store data that the host 20 intends to write to the solid-state storage device 10 and to store data that the host 20 reads from the solid-state storage device 10.

[0018] In some embodiments, the solid-state storage device 10 may support, for example, the Non-volatile Memory Communication Protocol (NVM Express, NVME), and the controller 102 may retrieve access instructions, such as write instructions and read instructions, from the submission queue 2041 of the host 20. The volatile memory 106 is configured with a submission queue 1061, a completion queue 1062, and a wait queue 1063. The submission queue 1061 records access instructions retrieved from the host 20, and the completion queue 1062 records the status of access instructions completed by the solid-state storage device 10. The wait queue 1063 records one or more access instructions pushed from the submission queue 1061.

[0019] The non-volatile memory 108 may be flash memory, such as NAND flash memory, or it may be a next-generation memory product type such as ferroelectric random access memory (FeRAM), phase change memory (PCM), magnetoresistive random access memory (MRAM), and resistive random access memory (ReRAM). The non-volatile memory 108 is used to store write data provided by the host 20, and may be composed of a plurality of dies 1081. In some embodiments, the non-volatile memory 108 may include multiple channels, and each channel may include one or more dies 1081. Furthermore, each channel is equipped with a corresponding submit queue 1061, complete queue 1062, and wait queue 1063. Additionally, the controller 102 may distribute access commands from the host 20 to the corresponding submit queue 1061, complete queue 1062, and wait queue 1063 of each channel. In some embodiments, the corresponding wait queues 1063 of each channel can form an instruction scheduling layer (not shown in FIG1). The non-volatile memory 108 includes a plurality of blocks, and each block includes a plurality of pages. In some embodiments, for ease of illustration, each die 1081 of the non-volatile memory 108 includes 1024 blocks, and each block includes 64 pages. Assuming the capacity of each page is 16 KB, the capacity of each block is 1 MB. The above data is for illustrative purposes only, and the manufacturer of the non-volatile memory 108 may determine the number of pages in each block and the capacity of each page.

[0020] In some embodiments, when the host 20 wants to store write data to the solid-state storage device 10, the processor 202 stores the write data corresponding to a write instruction in the data register 2043 of the system memory 204, and writes the write instruction to the commit queue 2041. For example, the content of the write instruction includes the logical address of the write data, such as 0x2000, and the size of the write data, such as 16K bytes.

[0021] In some embodiments, the controller 102 of the solid-state storage device 10 may periodically check whether there are new access commands in the commit queue 2041. The controller 102 of the solid-state storage device 10 may fetch write commands from the commit queue 2041 and record the fetched write commands in the commit queue 1061 of the volatile memory 106.

[0022] It should be noted that for the solid-state storage device 10, the write command from the host 20 can have a longer response time compared to the read command. Therefore, in this embodiment of the invention, after the controller 102 retrieves the write command from the submission queue 2041, it can execute the write command to program one of the chips 1081 in the non-volatile memory 108. At this time, the write command will be in a pending status and will be kept recorded in the submission queue 1061, while the corresponding write data will be kept stored in the data buffer 2043 on the host 20.

[0023] During the programming of the write instruction, the controller 102 retrieves a read instruction from the commit queue 2041 of the host 20. The controller 102 then determines whether the target condition is met to decide whether to prioritize the execution of the write instruction or interrupt the write instruction to execute the read instruction. When the controller 102 determines that the target condition is met, the controller 102 prioritizes the execution of the write instruction. After the programming of the write instruction is completed (i.e., the controller 102 temporarily stores the write data from the data register 2043 of the host 20 to the volatile memory 106 and programs the write data to the non-volatile memory 108), the controller 102 transmits the corresponding first command completion information to the completion queue 1062 and writes the first command completion information in the completion queue 1062 to the completion queue 2042 of the host 20. Specifically, the controller 102 writes the first command completion information corresponding to the write instruction to the completion queue 1062 and deletes the write instruction from the commit queue 1061. The controller 102 then writes the first instruction completion information corresponding to the write instruction to the completion queue 2042 of the host 20, and deletes the item corresponding to the write instruction from the submission queue 2041 of the host 20.

[0024] In some embodiments, the controller 102 may set the phase tag corresponding to the first instruction completion information in the completion queue 2042 to 1, and send an interrupt signal to the processor 202 to notify the processor 202 that new instruction completion information has been submitted to the completion queue 2042. When the processor 202 receives the interrupt signal, the processor 202 can use the set phase tag to view the new item in the completion queue 2042. When the new item reports that the instruction was executed successfully, the processor 202 will terminate the related events of the write instruction and record that the write data of the write instruction has been successfully written to the solid-state storage device 10.

[0025] When the controller 102 determines that the target condition is not met, it interrupts the write instruction to execute the read instruction. After the read instruction is completed (i.e., the read data corresponding to the read instruction is successfully written to the data register 2043 of the host 20), it transmits the second instruction completion information corresponding to the read instruction to the completion queue 1062 and writes the second instruction completion information in the completion queue 1062 to the completion queue 2042 of the host 20. Therefore, the processor 202 of the host 20 can know that the read instruction has been successfully executed by means of the second instruction completion information corresponding to the read instruction in the completion queue 2042. When the read instruction has been successfully executed, the controller 102 resumes the programming program for the write instruction and executes the programming program until the write instruction is completed.

[0026] Figure 2 is a schematic diagram showing that the programming program of the write instruction according to an embodiment of the present invention is interrupted by multiple read instructions.

[0027] In some embodiments, the controller 102 may perform the functions of a command sensor, such as retrieving access commands from the submission queue 2041 of the host 20, which includes read and write commands. For ease of explanation, the non-volatile memory 108 has four channels, such as channels 0 to 3, which correspond to dies 0 to 3 respectively. Furthermore, the controller 102 may write the respective read and write commands retrieved from the submission queue 2041 to the wait queue 1063 of the corresponding channel. The wait queues 1063 of each channel may be collectively referred to as the command schedule layer, as shown in FIG2.

[0028] For simplicity, the embodiment in Figure 2 is illustrated using the programming procedure of one of the write instructions for die 0 as an example. When the programming procedure for this write instruction begins, if controller 102 receives the first read instruction from channel 0, controller 102 will pause the programming procedure and wait for the first read instruction to complete before resuming it. Similarly, if controller 102 receives the second read instruction from channel 0, it will pause the programming procedure and wait for the second read instruction to complete before resuming it. Controller 102 may repeatedly execute the process of receiving read instructions and pausing the programming procedure. When the number of read instructions received by controller 102 during the programming procedure for this write instruction is too large, it will affect the response time of controller 102 to host 20, for example, exceeding 200 microseconds (μs), thereby affecting the Quality of Service (QoS) of solid-state storage device 10.

[0029] In detail, computer system 1 is designed to handle application scenarios with a write queue depth of 1 and a write throughput of 80 MiB / s, and a read queue depth of 8 and a read throughput of 600 MiB / s. The write queue depth (Write QD) represents the maximum number of write commands that can be stored in the waiting queue 1063, and the read queue depth (Read QD) represents the maximum number of read commands that can be stored in the waiting queue 1063. However, in certain special application scenarios, the solid-state storage device 10 may execute more write commands than expected, resulting in opposite throughput for write and read commands. Furthermore, the large amount of data written will also increase read latency, thus affecting the performance of read operations. The controller and dynamic quality of service management method proposed in this invention can effectively control and resolve quality of service requirements. For example, it can provide suitable bandwidth based on write queue depth, read queue depth, and the data size of the instruction request to solve the latency problem of quality of service. For instance, the controller 102 of this invention can adjust the settings of the instruction sensor to limit the resources of write instructions, thereby reducing the impact of write instructions on the resources of read instructions.

[0030] Figure 3 is a flowchart of a dynamic quality of service management method for a solid-state storage device according to an embodiment of the present invention. Please refer to Figures 1 and 3 simultaneously.

[0031] In step 302, when the instruction sensor executed by the controller 102 is activated, the controller 102 can control the submission queue 2041 (or submission queue 1061) to push write instructions. In some embodiments, the above action is equivalent to the controller 102 retrieving write instructions from the submission queue 2041, and the controller 102 storing the retrieved write instructions in the submission queue 1061. Furthermore, for ease of explanation, write instructions can be categorized into 4K, 8K, and 16K byte write instructions W1, W2, and W3, depending on their write data size. In some embodiments, when the solid-state storage device 10 is actually operating, the write data size of the write instructions and the read data size of the read instructions range approximately from 4K to 256K bytes, with the maximum value depending on the parameter value of the maximum data transfer size of the solid-state storage device 10.

[0032] In step 304, controller 102 records the write data size, increments the write count (e.g., by 1), and updates the write queue depth. In some embodiments, controller 102 may include associated registers (not shown) to record the write data size, write count, and write queue depth. Furthermore, the write count and write queue depth can be used, for example, to read the quota control module 114 and the instruction equalizer module 116 for relevant determinations.

[0033] In step 306, controller 102 determines whether the read count value and standby time meet the target conditions. When controller 102 determines that the read count value and standby time meet the target conditions, controller 102 controls standby queue 1063 to pop the write command (step 308) and processes the write command (step 310). Processing the write command in step 310 may include searching the logical-to-physical mapping table in cache memory 104 and / or non-volatile memory 108 and configuring the data storage space of cache memory 104 or volatile memory 106 for storing the write data of the data buffer 2043 of host 20. For example, controller 102 executes step 312 to transfer the write data from data buffer 2043 to cache memory 104 (or volatile memory 106). When the controller 102 determines that the read count value and waiting time do not meet the target conditions, it continues to step 302. The controller 102 can control the submission queue 2041 (or submission queue 1061) to push the write command.

[0034] In step 314, when the written data is successfully transferred to cache memory 104 (or volatile memory 106), controller 102 transmits instruction completion information corresponding to the write instruction to completion queue 2042. In some embodiments, after controller 102 transmits instruction completion information corresponding to the write instruction to completion queue 2042, indicating that the write instruction has been successfully executed, controller 102 further reduces the write count value (e.g., decrements by 1), that is, the number of write instructions in waiting queue 1063 is reduced by 1.

[0035] In step 316, when the size of one or more write data stored in cache memory 104 (or volatile memory 106) reaches the size of a word line (e.g., a page of 16K bytes), controller 102 will clear the write data stored in cache memory 104 (or volatile memory 106) to non-volatile memory 108, for example, by programming the page-sized write data to a spare block or a blank page of a data block that is not fully occupied in non-volatile memory 108.

[0036] Figure 4 is a flowchart of the firmware executed by the controller according to an embodiment of the present invention. Figure 5 is a flowchart of the instruction control module according to the embodiment of Figure 4 of the present invention. Figure 6 is a flowchart of the read quota control module according to the embodiment of Figure 4 of the present invention. Figure 7 is a flowchart of the instruction equalizer module according to the embodiment of Figure 4 of the present invention. Please also refer to Figures 1 and Figures 3 to 7.

[0037] In some embodiments, the controller 102 writes write instructions or read instructions retrieved from the commit queue 2041 of the host 20 to the commit queue 1061 in the solid-state storage device 10. The firmware module executed by the controller 102 mainly includes an instruction control module 112, a read quota control module 114, and an instruction equalizer module 116, as shown in FIG4. Furthermore, the instruction control module 112, the read quota control module 114, and the instruction equalizer module 116 operate together.

[0038] Referring to Figure 5, in some embodiments, the command control module 112 is configured to determine whether a read command meets multiple specific conditions, such as the judgment steps in steps 504 and 506. The command control module 112 includes, for example, a command decoder. Whenever the controller 102 retrieves an incoming access command from the submission queue 2041 of the host 20 to the submission queue 1061 of the solid-state storage device 10, the command decoder executed by the controller 102 determines whether the incoming access command is a read command or a write command. When the incoming access command received by the controller 102 is a write command (step 502), the controller 102 records the data size of the write command, increments the write count value, and increments the write queue depth by 1, and places the write command in the wait queue 1063. Next, the controller 102 determines whether the read count value is equal to the read credit (step 504). For example, if the read limit is 20, the controller 102 will execute 1 write instruction only after completing 20 read instructions, and so on. Furthermore, the read limit can be considered as the ratio of the number of read instructions executed by the controller 102 to the number of write instructions executed. The read count value represents the number of read instructions executed by the controller 102 within that read limit.

[0039] When controller 102 determines that the read count value equals the read limit, controller 102 processes the write instruction (step 508). When controller 102 completes the write instruction, controller 102 increments the write completion count value, resets the read count value and the waiting time (step 512), decrements the write queue depth by 1, and writes the instruction completion information corresponding to the write instruction to the completion queue 1062. Controller 102 then writes the instruction completion information corresponding to the write instruction in the completion queue 1062 to the completion queue 2042 of host 20 to notify processor 202 that the write instruction has been completed. For example, controller 102 calculates the waiting time from receiving the write instruction until receiving the next read instruction. If the waiting time exceeds a predetermined time, it means that controller 102 has not received any read instruction within the predetermined time, and controller 102 will directly execute the write instruction. Therefore, the above-mentioned waiting time determination mechanism can prevent write instruction timeout. In some embodiments, the above-mentioned predetermined time is approximately 50 μs, but the present invention is not limited thereto.

[0040] When controller 102 determines that the read count value is not equal to the read limit (i.e., the read count value has not yet reached the read limit), controller 102 further determines whether the standby time of the write instruction has exceeded a predetermined time (step 506). When controller 102 determines that the standby time of the write instruction has exceeded the predetermined time, controller 102 processes the write instruction (step 508). When controller 102 completes the write instruction, controller 102 increments the write completion count value, resets the read count value and the standby time (step 512), decrements the write queue depth by 1, and writes the instruction completion information corresponding to the write instruction to the completion queue 1062. Controller 102 then writes the instruction completion information corresponding to the write instruction in the completion queue 1062 to the completion queue 2042 of host 20, thereby notifying processor 202 that the write instruction has been completed. If the controller 102 determines that the waiting time for the write instruction has not exceeded the predetermined time, the controller 102 will not process the write instruction, but will instead retain the write instruction (step 510), for example, by storing the write instruction in the waiting queue 1063. At this time, the controller 102 will first process the incoming read instruction until the read count value reaches the read limit or the waiting time for the write instruction exceeds the predetermined time, and then retrieve the write instruction from the waiting queue 1063 and execute it.

[0041] In some embodiments, when the incoming access instruction received by the controller 102 is a read instruction, the controller 102 records the data size of the read instruction, increments the read count value, and increments the read queue depth by 1, and then places the read instruction in the wait queue 1063. The controller 102 can then retrieve the read instruction from the wait queue 1063 and execute it. When the controller 102 completes the read instruction, it increments the read completion count value, decrements the read queue depth by 1, and writes the instruction completion information of the read instruction to the completion queue 1062. The controller 102 then writes the instruction completion information corresponding to the read instruction in the completion queue 1062 to the completion queue 2042 of the host 20 to notify the processor 202 that the read instruction has been completed.

[0042] Referring to Figure 6, in some embodiments, the read quota control module 114 is configured to determine whether the solid-state storage device 10 complies with a specified command queue depth, thereby determining whether the read quota needs to be adjusted. In some embodiments, whenever the controller 102 completes a predetermined number of access instructions (step 602), the controller 102 determines whether a predetermined condition is met, such as "the read queue depth (RQD) is greater than the write queue depth (WQD) and the read completed count (RCC) is less than the write completed count (WCC)" (step 604). In some embodiments, the predetermined number is 200, but the present invention is not limited to this, and the predetermined number can be adjusted according to actual conditions. Furthermore, the above access instructions include read instructions and write instructions, and the predetermined number is the sum of the read completed count and the write completed count. In some embodiments, the read completed count and the write completed count can be represented by the number of read input / output operations and the number of write input / output operations, respectively.

[0043] When controller 102 determines that the predetermined condition is met, controller 102 increases the read limit (step 608). When controller 102 determines that the predetermined condition is not met, controller 102 further determines whether the reference value REF is within a predetermined range (step 606), wherein the predetermined range of the reference value REF is, for example, between 0 and 2. When controller 102 determines that the reference value REF is within the predetermined range, controller 102 increases the read limit (step 608). When controller 102 determines that the reference value REF is not within the predetermined range, controller 102 decreases the read limit (step 610). In some embodiments, controller 102 may use the reference value REF to determine whether the solid-state storage device 10 meets a predetermined workload pattern or the current workload pattern.

[0044] It should be noted that whenever the controller 102 completes a predetermined number of access instructions, the increase or decrease in the read quota by the controller 102 is used in the cycle for the next predetermined number of access instructions. For example, in step 504 of Figure 5, the updated read quota is used for judgment. In other words, the controller 102 can dynamically adjust the value periodically (e.g., after each predetermined number of access instructions, such as 200 access instructions) according to the workload of the computer system 1. In addition, the reference value REF can represent the ratio between the "read completion count (RCC) to the write completion count (WCC)" (e.g., the first ratio N1 = RCC / WCC) and the "read command weighted score (RCWS) to the write command weighted score (WCWS)" (e.g., the second ratio N2 = RCWS / WCWS) calculated after the controller 102 executes a predetermined number of access instructions.

[0045] Referring to Figure 7, in some embodiments, the instruction equalizer module 116 is configured to calculate a reference value REF, which serves as an equalizer controlling the read and write data throughput. For example, the controller 102 determines whether a specific condition is met, such as whether a first ratio N1 is greater than a second ratio N2 (step 702). When the controller 102 determines that the specific condition is met, the controller 102 divides the first ratio N1 by the second ratio N2 to obtain the reference value REF, i.e., REF = N1 / N2 (step 704). When the controller 102 determines that the specific condition is not met, the controller 102 divides the second ratio N2 by the first ratio N1 to obtain the reference value REF, i.e., REF = N2 / N1 (step 706).

[0046] In detail, when the controller 102 determines that the specific condition is met, it indicates that the resources of the solid-state storage device 10 used for read instructions need to be managed or adjusted. If the controller 102 uses all the resources of the solid-state storage device 10 to execute read instructions, the resources used for write instructions will become extremely unbalanced and unable to meet the needs of the expected workload.

[0047] In some embodiments, the firmware executed by the controller 102 may assign individual read / write weights to read and write instructions with different read / write data sizes to reflect the impact of each read and write instruction on the read queue and write queue, respectively. For ease of explanation, the write data size and read data size range from 4KB to 256KB, as shown in Table 1. Write data size (byte) Write weight Data size (byte) Read weight 4K 2 4K to 32K 1 8K to 16K 1 33K to 64K 2 16K to 256K 4 65K to 256K 3 Table 1

[0048] It should be noted that the write weights and read weights shown in Table 1 are for illustrative purposes only, and their initial values ​​can be adjusted as needed. For example, the initial values ​​of the write weights and read weights can be stored in the firmware of the controller 102.

[0049] In another embodiment, for simplicity, the description is based on a cycle of 200 access instructions, wherein the write weight and write completion count of the write instruction are shown in Table 2, and the write weight and read completion count of the read instruction are shown in Table 3. Write data size (byte) 4K 8K 16K Write command Weighted score Write weight 12 5 5 17 Write completed count value 1 0 1 Table 2 Data size (byte) 4K 8K 16K Read instructions Weighted score Read weight 4 6 8 34 Read completed count value 2 3 1 Table 3

[0050] For example, for write instructions with data sizes of 4K, 8K, and 16K bytes, their write weights are 12, 5, and 5, respectively, and their write counts are 1, 0, and 1, respectively. For write instructions with read data sizes of 4K, 8K, and 16K bytes, their write weights are 4, 6, and 8, respectively, and their write counts are 2, 3, and 1, respectively. Therefore, controller 102 can calculate the weighted score of write instructions = 12*1 + 5*0 + 5*1 = 17, and the weighted score of read instructions = 4*2 + 6*3 + 8*1 = 34. Therefore, controller 102 can calculate the second ratio N2 = 34 / 17 = 2. For ease of explanation, these 200 access instructions include 160 read instructions and 40 write instructions, indicating a read count of 160 and a write count of 40. Furthermore, controller 102 can also calculate the first ratio N1 = 160 / 40 = 4.

[0051] In this embodiment, since the specific condition is met (i.e., the first ratio N1 > the second ratio N2), the controller 102 divides the first ratio N1 by the second ratio N2 to obtain the reference value REF, meaning REF = N1 / N2 = 4 / 2 = 2. It should be noted that if this specific condition is not met, the controller 102 divides the second ratio N2 by the first ratio N1 to obtain the reference value REF, meaning REF = N2 / N1.

[0052] Figures 8A and 8B are schematic diagrams illustrating the adjustment of the reference value REF and the reading limit by the controller under different conditions according to an embodiment of the present invention.

[0053] In some embodiments, for ease of explanation, assuming the first ratio N1 is greater than the second ratio N2, and the first ratio N1 is a fixed value, the controller 102 can consider four different cases based on the range of the reference value REF, as shown in cases 1 to 4 of FIG8A. When the write weight increases or the read weight decreases, the reference value REF decreases (or moves to the left). When the write weight decreases or the read weight increases, the reference value REF increases (or moves to the right). Simply put, the controller 102 will repeatedly attempt to align the first ratio N1 and the second ratio N2, that is, adjust towards the reference value REF=1, so that the read data throughput and write data throughput of the solid-state storage device 10 can be distributed according to the expected workload ratio.

[0054] Referring to Figure 8A, in Case 1, the reference value REF is between 1 and 2, i.e., 1 < REF ≤ 2. In this case, the controller 102 will either reduce the write weight of various write commands with different write data sizes (e.g., decrement all by 1) or increase the read weight of various read commands with different read data sizes (e.g., increment all by 1). For example, in Table 2, in Case 1, the controller 102 can decrement the corresponding weight values ​​of write commands with write data sizes of 4K, 8K, and 16K bytes by 1, for example, to 11, 4, and 4 respectively. For example, in Table 3, in Case 1, the controller 102 can increment the corresponding weight values ​​of read commands with write data sizes of 4K, 8K, and 16K bytes by 1, for example, to 5, 7, and 9 respectively. Regardless of whether the controller 102 reduces the write weight or increases the read weight, the reference value REF will decrease towards 1, and the read performance of the solid-state storage device 10 will be maintained. Furthermore, please refer to Figure 6. Whenever the controller 102 completes a predetermined number of access instructions, regardless of the judgment result in step 604, in case 1, because the reference value REF is between 1 and 2, the read quota control module 114 executed by the controller 102 will increase the read quota (e.g., add 1).

[0055] In Case 2 of Figure 8A, the reference value REF is between 0 and 1, i.e., 0 < REF < 1. In this case, controller 102 either increases the write weight of various write commands with different write data sizes (e.g., increments all by 1) or decreases the read weight of various read commands with different read data sizes (e.g., decrements all by 1). Regardless of whether controller 102 increases the write weight or decreases the read weight, it can increase the reference value REF towards 1, and the read performance of solid-state storage device 10 will be maintained. For example, in Case 2 (using Table 2), controller 102 can increment the corresponding weight values ​​of write commands with write data sizes of 4K, 8K, and 16K bytes by 1, for example, to 13, 6, and 6 respectively. Similarly, in Case 2 (using Table 3), controller 102 can decrement the corresponding weight values ​​of read commands with write data sizes of 4K, 8K, and 16K bytes by 1, for example, to 3, 5, and 7 respectively. Furthermore, please refer to Figure 6. Whenever the controller 102 completes a predetermined number of access instructions, regardless of the judgment result in step 604, in case 2, because the reference value REF is between 0 and 1, the read quota control module 114 executed by the controller 102 will increase the read quota (e.g., add 1).

[0056] In case 3 of Figure 8A, the reference value REF = 0. In this case, controller 102 increases the write weight of various write commands with different write data sizes (e.g., increments all by 1) or decreases the read weight of various read commands with different read data sizes (e.g., decrements all by 1). Similar to case 2, regardless of whether controller 102 increases the write weight or decreases the read weight, the reference value REF will increase towards 1, and the read performance of solid-state storage device 10 will increase. Furthermore, referring to Figure 6, after controller 102 completes a predetermined number of access commands, regardless of the judgment result in step 604, in case 3, because the reference value REF will be between 0 and 1 after the increase, the read quota control module 114 executed by controller 102 will increase the read quota (e.g., increment by 1).

[0057] In case 4 of Figure 8A, the reference value REF > 2. In this case, controller 102 will either reduce the write weight of various write commands with different write data sizes (e.g., decrease all by 1) or increase the read weight of various read commands with different read data sizes (e.g., increase all by 1). Regardless of whether controller 102 reduces the write weight or increases the read weight, the reference value REF will decrease towards 1, and the read performance of solid-state storage device 10 will increase. Furthermore, referring to Figure 6, whenever controller 102 completes a predetermined number of access commands, if the determination result in step 604 is negative, in case 4, because the reference value REF is greater than 2, the read quota control module 114 executed by controller 102 will reduce the read quota (e.g., decrease by 1).

[0058] In some embodiments, for ease of explanation, assuming the first ratio N1 is less than the second ratio N2 and the first ratio N1 is a fixed value, the controller 102 can consider four different cases based on the range of the reference value REF, as shown in cases 1 to 4 in FIG8B. When the write weight increases or the read weight decreases, the reference value REF decreases (or moves to the left). When the write weight decreases or the read weight increases, the reference value REF increases (or moves to the right). Simply put, the controller 102 will repeatedly attempt to align the first ratio N1 and the second ratio N2, that is, adjust towards the reference value REF=1, so that the read data throughput and write data throughput of the solid-state storage device 10 can be distributed according to the expected workload ratio.

[0059] Referring to Figure 8B, in Case 1, the reference value REF is between 1 and 2, i.e., 1 < REF ≤ 2. In this case, the controller 102 increases the write weight of various write commands with different write data sizes (e.g., increments all by 1) or decreases the read weight of various read commands with different read data sizes (e.g., decrements all by 1). Regardless of whether the controller 102 increases the write weight or decreases the read weight, the reference value REF can be reduced to approach 1, and the read performance of the solid-state storage device 10 will be maintained. Furthermore, referring to Figure 6, whenever the controller 102 completes a predetermined number of access commands, regardless of the judgment result in step 604, in Case 1, because the reference value REF is between 1 and 2, the read quota control module 114 executed by the controller 102 will increase the read quota (e.g., increment by 1).

[0060] In Case 2 of Figure 8B, the reference value REF is between 0 and 1, i.e., 0 < REF < 1. In this case, the controller 102 will either reduce the write weight of various write commands with different write data sizes (e.g., decrease all by 1) or increase the read weight of various read commands with different read data sizes (e.g., increase all by 1). Regardless of whether the controller 102 reduces the write weight or increases the read weight, the reference value REF will increase to approach 1, and the read performance of the solid-state storage device 10 will be maintained. Furthermore, referring to Figure 6, whenever the controller 102 completes a predetermined number of access commands, regardless of the judgment result in step 604, in Case 2, because the reference value REF is between 0 and 1, the read quota control module 114 executed by the controller 102 will increase the read quota (e.g., increase by 1).

[0061] In case 3 of Figure 8B, the reference value REF = 0. In this case, controller 102 will either reduce the write weight of various write commands with different write data sizes (e.g., decrease all by 1) or increase the read weight of various read commands with different read data sizes (e.g., increase all by 1). Regardless of whether controller 102 reduces the write weight or increases the read weight, the reference value REF will increase towards 1, and the read performance of solid-state storage device 10 will be maintained. Furthermore, referring to Figure 6, whenever controller 102 completes a predetermined number of access commands, regardless of the judgment result in step 604, in case 3, because the reference value REF will be between 0 and 1 after increasing, the read quota control module 114 executed by controller 102 will increase the read quota (e.g., increase by 1).

[0062] In case 4 of Figure 8B, the reference value REF > 2. In this case, controller 102 either increases the write weight of various write commands with different write data sizes (e.g., increments all by 1) or decreases the read weight of various read commands with different read data sizes (e.g., decrements all by 1). Regardless of whether controller 102 increases the write weight or decreases the read weight, it can lower the reference value REF to approach 1, and the read performance of solid-state storage device 10 will increase. Furthermore, referring to Figure 6, whenever controller 102 completes a predetermined number of access commands, if the determination result in step 604 is negative, in case 4, because the reference value REF is greater than 2, the read quota control module 114 executed by controller 102 will decrease the read quota (e.g., decrement by 1).

[0063] In one embodiment, the second ratio N2 can be the ratio of the maximum read queue depth (MaxRQD) to the maximum write queue depth (MaxWQD), i.e., N2 = MaxRQD / MaxWQD. For ease of explanation, the controller 102 executes a predetermined number (e.g., 200) of access instructions, including 20 write instructions and 180 read instructions, with a maximum write queue depth of 1 and a maximum read queue depth of 16. In this case, the controller 102 can calculate the first ratio N1 = 180 / 20 = 9 and the second ratio N2 = 16 / 1 = 16. Since the second ratio N2 is greater than the first ratio N1, the controller 102 calculates the reference value REF = N2 / N1 = 16 / 9 = 1.7. Furthermore, the controller 102 can calculate the central read completed count (CRCC) as follows:

[0064] In this case, when the reference value REF calculated by controller 102 is not within the predetermined range (e.g., greater than 2) (i.e., the judgment result of step 606 in Figure 6 is negative), controller 102 will further determine whether the read completion count value is greater than the central read completion count value. If the read completion count value is greater than the central read completion count value, controller 102 will reduce the read quota (e.g., decrement by 1). If the read completion count value is not greater than the central read completion count value, controller 102 will increase the read quota (e.g., increment by 1).

[0065] According to embodiments of the present invention, a solid-state storage device can dynamically adjust the resources of write and read commands to meet the demands of varying system workloads. For example, it can provide suitable write / read data bandwidth based on write data size, write queue depth, read data size, and read queue depth, thereby solving the latency problem of quality of service. Furthermore, embodiments of the present invention can maintain the processing performance of the solid-state storage device 10 under different system workloads and effectively meet the requirements of quality of service (QoS).

[0066] While the present invention has been disclosed above with reference to preferred embodiments, it is not intended to limit the scope of the invention. Anyone skilled in the art can make modifications and refinements without departing from the spirit and scope of the invention. Therefore, the scope of protection of the present invention shall be determined by the appended claims.

[0067] 1: Computer System 10: Solid-state storage devices 11: Busbar 20: Host 101: Internal Bus 102: Controller 104: Cache Memory 106: Volatile Memory 108: Flash Memory 110: Non-volatile memory 111: Data Transfer Interface 112: Command Control Module 114: Read the quota control module 116: Instruction equalizer module 202: Processor 204: System Memory 1061, 2041: Submit queue 1062, 2042: Completed standby 1063: Waiting in line 1081: Grain 2043: Data Temporary Memory 302-316, 402-406, 502-512: Steps 602-610, 702-706: Steps

Claims

1. A solid-state storage device configured to be electrically connected to a host computer, the solid-state storage device comprising: One controller; A non-volatile memory, electrically connected to the controller, is used to store data written by the host. The controller is configured to acquire a plurality of access instructions from the host and record the access instructions in the commit queue, wherein the access instructions include a plurality of write instructions and a plurality of read instructions. When the controller acquires a first write instruction from the commit queue, the controller is configured to determine whether a read count value of the read instructions and a waiting time from the receipt of the first write instruction meet a target condition. If the read count value and the waiting time meet the target condition, the controller is configured to execute the first write instruction. If the read count value and the waiting time do not meet the target condition, the controller is configured to retain the first write instruction in the wait queue.

2. The solid-state storage device as claimed in claim 1, wherein: When the controller receives the first write instruction from the submission queue, the controller is configured to determine whether the read count value of the read instructions is equal to a read limit, the read limit being the ratio of the number of read instructions executed by the controller to the number of write instructions; when the read count value is equal to the read limit, the controller is configured to execute the first write instruction; when the read count value is not equal to the read limit, the controller is configured to determine whether the waiting time since receiving the first write instruction has exceeded a predetermined time; when the waiting time exceeds the predetermined time, the controller is configured to process the first write instruction; and when the waiting time does not exceed the predetermined time, the controller is configured to retain the first write instruction in the waiting queue.

3. The solid-state storage device of claim 2, wherein when the controller successfully programs the write data of the first write instruction to the non-volatile memory, the controller is configured to reset the read count value and the wait time.

4. A solid-state storage device as claimed in claim 2, wherein: Whenever the controller completes a predetermined number of such access instructions, the controller is configured to determine whether the read queue depth of such read instructions is greater than the write queue depth of such write instructions and whether the read completion count value of such read instructions is less than the write completion count value of such write instructions; And when the read queue depth is greater than the write queue depth and the read completion count is less than the write completion count, the controller is configured to increment the read quota by 1.

5. A solid-state storage device as claimed in claim 4, wherein: When the read queue depth is not greater than the write queue depth or the read completion count is not less than the write completion count, the controller is configured to determine whether a reference value is within a predetermined range; when the reference value is within the predetermined range, the controller is configured to increment the read limit by 1; and when the reference value is not within the predetermined range, the controller is configured to decrement the read limit by 1.

6. A solid-state storage device as claimed in claim 5, wherein: The controller is configured to divide the read completion count by the write completion count to obtain a first ratio, and to divide a read instruction weighted score corresponding to each read instruction by a write instruction weighted score of each write instruction to obtain a second ratio; when the first ratio is greater than the second ratio, the controller is configured to divide the first ratio by the second ratio to obtain the reference value; and when the first ratio is not greater than the second ratio, the controller is configured to divide the second ratio by the first ratio to obtain the reference value.

7. A solid-state storage device as claimed in claim 6, wherein: The controller is configured to assign individual read weights to each read instruction based on the read data size of the read instructions, and to assign individual write weights to each write instruction based on the write data size of the write instructions; and the controller is configured to sum the individual read weights of each read instruction to obtain the read instruction weighted score, and to sum the individual write weights of each write instruction to obtain the write instruction weighted score.

8. The solid-state storage device of claim 7, wherein the controller is configured to adjust the individual read weight of each read instruction or the individual write weight of each write instruction so that the reference value approaches a target value within the predetermined range.

9. A solid-state storage device as claimed in claim 8, wherein: When the reference value is within the predetermined range, the controller is configured to increase the read limit; and when the reference value is outside the predetermined range, the controller is configured to decrease the read limit.

10. A dynamic quality of service management method for a solid-state storage device electrically connected to a host, the solid-state storage device including a controller, a volatile memory, and a non-volatile memory, the method comprising: The controller retrieves a plurality of access instructions from the host and records these access instructions in a commit queue of the volatile memory, wherein the access instructions include a plurality of write instructions and a plurality of read instructions; when the controller retrieves a first write instruction from the commit queue, the controller determines whether a read count value of the read instructions and a waiting time from the receipt of the first write instruction meet a target condition; when the read count value and the waiting time meet the target condition, the controller executes the first write instruction; and when the read count value and the waiting time do not meet the target condition, the controller retains the first write instruction in a wait queue of the volatile memory.

11. As in request item 10, the method further includes: When the controller receives the first write instruction from the submission queue, the controller determines whether the read count value of the read instructions is equal to a read limit, wherein the read limit is the ratio of the number of read instructions executed by the controller to the number of write instructions; when the read count value is equal to the read limit, the controller executes the first write instruction; when the read count value is not equal to the read limit, the controller determines whether the waiting time since receiving the first write instruction has exceeded a predetermined time; when the waiting time exceeds the predetermined time, the controller processes the first write instruction; and when the waiting time does not exceed the predetermined time, the controller retains the first write instruction in the waiting queue.

12. The method of request item 11 further includes: When the controller successfully programs the write data of the first write instruction into the non-volatile memory, the controller resets the read count value and the wait time.

13. The method of request item 11 further includes: Whenever the controller completes a predetermined number of such access instructions, the controller determines whether the read queue depth of such read instructions is greater than the write queue depth of such write instructions and whether the read completion count value of such read instructions is less than the write completion count value of such write instructions. And when the read queue depth is greater than the write queue depth and the read completion count is less than the write completion count, the controller increments the read quota by 1.

14. The method of request item 13 further includes: When the read queue depth is not greater than the write queue depth or the read completion count is not less than the write completion count, the controller determines whether a reference value is within a predetermined range; when the reference value is within the predetermined range, the controller increments the read quota by 1; and when the reference value is not within the predetermined range, the controller decrements the read quota by 1.

15. The method of request item 14 further includes: The controller divides the read completion count by the write completion count to obtain a first ratio, and divides the read instruction weighted score of the read instructions by the write instruction weighted score of the write instructions to obtain a second ratio; when the first ratio is greater than the second ratio, the controller divides the first ratio by the second ratio to obtain the reference value; and when the first ratio is not greater than the second ratio, the controller divides the second ratio by the first ratio to obtain the reference value.

16. The method of request item 15 further includes: The controller assigns individual read weights to each read instruction based on the read data size of the read instructions, and assigns individual write weights to each write instruction based on the write data size of the write instructions; and the controller sums the individual read weights of each read instruction to obtain a read instruction weighted score, and sums the individual write weights of each write instruction to obtain a write instruction weighted score.

17. The method of request item 16 further includes: The controller is used to adjust the individual read weight of each read command or the individual write weight of each write command so that the reference value approaches a target value within the predetermined range.

18. The method of request item 17 further includes: When the reference value is within the predetermined range, the controller is used to increase the reading limit; And when the reference value is not within the predetermined range, the controller is used to reduce the reading limit.

Images