Instruction-aware method for optimizing virtual-to-physical memory address translation

Abstract

The present invention relates to a method corresponding to virtual-to-physical address translation replacement policies that differentiates between instruction and data memory accesses in order to act synergistically and reduce pipeline stalls, latency and energy consumption. More specifically, the proposed method promotes instruction translations to higher positions within a second translation list (STLB), making them less probable to be evicted. In combination, data translations maintenance is enhanced in a first list (L2C) which in turn contains the second list. This way, instruction translations are prioritized in the STLB and the associated increase in memory unit misses triggered by data page walks is mitigated.

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