Controlling circuit

Abstract

A controlling circuit adapted for bridging between a host device and multiple storage devices is provided. The controlling circuit includes a bridge controller and a disk array controller. The bridge controller includes an upstream facing port (UFP) interface circuit, a downstream facing port (DFP) interface circuit and a routing circuit. The UFP interface circuit couples the host device to the routing circuit based on a first transmission protocol. The DFP interface circuit couples the routing circuit to the storage devices based on a second transmission protocol. The disk array controller is coupled to the routing circuit and the DFP interface circuit. The disk array controller accesses the storage devices through the DFP interface circuit, thereby a performance of accessing data being increased.

Description

[Technical Field]

[0001] The present invention relates to a control circuit, and more particularly to a control circuit suitable for bridging host devices and multiple storage devices. [Previous Technology]

[0002] Based on various transmission standards, a host can access one or more terminal devices through a bridging circuit. The terminal device may be, for example, a non-volatile memory (NVM) device. These NVM devices can be arranged into a logical array to form a redundant array of independent disks (RAID). RAID is also known as a disk array.

[0003] However, current bridging circuits require external devices such as switches or control units to bridge the host and multiple NVM devices in order to achieve RAID functionality. As a result, the host cannot directly access one or more NVM devices through the bridging circuit, thus reducing data access performance. [Summary of the Invention]

[0004] Embodiments of the present invention provide a control circuit suitable for bridging host devices and multiple storage devices, and can avoid the need for external devices to implement RAID function in order to improve data access efficiency.

[0005] The control circuit of this embodiment includes a bridge controller and a disk array controller. The bridge controller includes an uplink port interface circuit, a downlink port interface circuit, and a routing circuit. The uplink port interface circuit is used to couple a host device and the routing circuit based on a first transmission standard. The downlink port interface circuit is used to couple the routing circuit and multiple storage devices based on a second transmission standard. The disk array controller is coupled to the routing circuit and the downlink port interface circuit. The disk array controller is used to access multiple storage devices through the downlink port interface circuit.

[0006] Based on the above, the control circuit of the present invention integrates the bridge controller and the disk array controller, enabling the host device to access multiple storage devices to achieve RAID function without the need for external devices, thereby improving the data access efficiency.

[0007] In order to make the above features and advantages of the present invention more apparent and understandable, specific embodiments are described below, and detailed descriptions are given in conjunction with the accompanying drawings.

Implementation Method

[0008] Some embodiments of the present invention will now be described in detail with reference to the accompanying drawings. Component symbols used in the following description are considered to be the same or similar components when they appear in different drawings. These embodiments are only a part of the present invention and do not disclose all possible implementations of the invention. More precisely, these embodiments are merely examples within the scope of the patent application of the present invention.

[0009] FIG1 is a circuit block diagram of a control circuit according to an embodiment of the present invention. Referring to FIG1, the control circuit 100 is adapted to bridge a host device 210 and a plurality of storage devices 211-22N, wherein N is a positive integer greater than 1. The control circuit 100 may be coupled to the host device 210 based on a first transmission standard, and may be coupled to the plurality of storage devices 211-22N based on a second transmission standard. The first transmission standard is different from the second transmission standard.

[0010] In this embodiment, the plurality of storage devices 211-22N may be, for example, non-volatile memory (NVM) devices. These storage devices 211-22N are arranged in a logical array to form a redundant array of independent disks (RAID).

[0011] In this embodiment, the host device 210 can directly access one or more storage devices 211-22N through the control circuit 100 to realize RAID function. The host device 210 may be, for example, an electronic device such as a mobile phone, computer, tablet computer, laptop computer, and desktop computer.

[0012] In the embodiment of FIG1, the control circuit 100 includes a bridge controller 110 and a disk array controller (i.e., RAID controller) 120. The bridge controller 110 is coupled to the disk array controller 120.

[0013] In detail, the bridging controller 110 includes a routing circuit 111, an upstream facing port (UFP) interface circuit 112, and a downstream facing port (DFP) interface circuit 113. The upstream facing port interface circuit 112 is used to couple the host device 210 and the routing circuit 111 based on a first transmission standard. The downstream facing port interface circuit 113 is used to couple the routing circuit 111 and a plurality of storage devices 211~22N based on a second transmission standard.

[0014] That is, the routing circuit 111 is used to transmit data conforming to different transmission standards. For example, the routing circuit 111 receives data from the host device 210 through the uplink port interface circuit 112. The data conforms to a first transmission standard. The routing circuit 111 converts the data into data conforming to a second transmission standard. The routing circuit 111 also outputs data conforming to the second transmission standard to multiple storage devices 211~22N, or to the disk array controller 120, through the downlink port interface circuit 113.

[0015] In this embodiment, the disk array controller 120 and the bridge controller 110 are integrated in the same circuit architecture. That is, the disk array controller 120 is not coupled to the input / output terminals (e.g., downlink port interface circuit 113) of the bridge controller 110 via a transmission line (or transmission interface) as an external component.

[0016] Specifically, the disk array controller 120 is coupled to the routing circuit 111 and the downlink port interface circuit 113. Thus, the disk array controller 120 can access data output by the routing circuit 111. The data conforms to a second transmission standard. The disk array controller 120 can also access multiple storage devices 211-22N through the downlink port interface circuit 113 to implement RAID functionality.

[0017] It is worth mentioning that by integrating the disk array controller 120 and the bridge controller 110, the control circuit 100 can avoid the need for external switches or control units and other devices, so that the host device 210 can directly access multiple storage devices 211~22N through the control circuit 100 to realize the RAID function. In this way, the control circuit 100 can improve the performance of data access.

[0018] FIG2 is a circuit block diagram of a control circuit according to another embodiment of the present invention. Referring to FIG2, the control circuit 300 is adapted to bridge the host device 210 and a plurality of storage devices 221-224, wherein the number of these storage devices 221-224 is merely illustrative. The host device 210 can be coupled to the control circuit 300 through its own connector 201, and can directly access the plurality of storage devices 221-224 through the control circuit 300 to implement RAID function. The connector 201 can be, for example, a Universal Serial Bus Type-C (USB Type-C) connector.

[0019] In this embodiment, the plurality of storage devices 221-224 may be, for example, NVM devices. These storage devices 221-224 include at least one of a solid-state disk (SSD) and at least one hard disk drive (HDD). That is, each storage device 221-224 may be, for example, an SSD or an HDD.

[0020] In the embodiment of FIG2, the control circuit 300 includes a bridge controller 310 and a disk array controller 320. The bridge controller 310 and the disk array controller 320 can be deduced by referring to the relevant description of the control circuit 100.

[0021] In this embodiment, the control circuit 300 is coupled to the host device 210 based on a first transmission standard through an uplink port interface circuit (not shown in FIG2), and is used to transmit data conforming to the first transmission standard. The first transmission standard includes Universal Serial Bus (USB) standard (e.g., USB4 standard) or Thunderbolt (TBT) standard (e.g., TBT5 standard).

[0022] In this embodiment, the bridging controller 310 may be, for example, a USB4 bridging controller. Alternatively, the bridging controller 310 may be, for example, a TBT accessory controller compatible with TBT specifications such as TBT3, TBT4, and TBT5.

[0023] In this embodiment, the control circuit 300 also couples multiple storage devices 221-224 based on a second transmission specification through a downlink port interface circuit (not shown in FIG2), and transmits data conforming to the second transmission specification. The second transmission specification includes the PCI Express (PCIe) specification.

[0024] That is, the first transmission interface between connector 201 and control circuit 300 conforms to the USB4 specification or TBT specification. The first transmission interface may be, for example, a USB Type-C transmission line. In addition, the second transmission interface between control circuit 300 and each storage device 221-224 conforms to the PCIe specification. The second transmission interface may be, for example, a Serial Advanced Technology Attachment (SATA) transmission interface, a Serial Attached SCSI (SAS) transmission interface, or a Non-Volatile Memory Express (NVMe) transmission interface.

[0025] It should be noted that the bridge controller 310 and the disk array controller 320 are located on the same chip. That is, the bridge controller 310 and the disk array controller 320 are integrated into the same controller. The controller can be implemented, for example, as an integrated circuit. Thus, the control circuit 300 can not only realize data transmission functions compliant with various transmission standards (i.e., USB4 / TBT and PCIe), but also realize RAID functions.

[0026] Furthermore, since the control circuit 300 does not require an external PCIe switch and / or RAID controller to provide RAID functionality, the control circuit 300 can reduce the cost of RAID applications for the host device 210.

[0027] FIG3 is a circuit block diagram of a control circuit according to another embodiment of the present invention. Referring to FIG3, the control circuit 500 is adapted to bridge the host device 210 and a plurality of storage devices 221-224. The control circuit 500 includes a bridge controller 510 and a disk array controller 520. The bridge controller 510 includes a routing circuit 511, an uplink port interface circuit 512, and a downlink port interface circuit 513. The routing circuit 511, the uplink port interface circuit 512, the downlink port interface circuit 513, and the disk array controller 520 can be deduced by referring to the relevant descriptions of the control circuit 100 and the control circuit 300.

[0028] In this embodiment, the routing circuit 511 includes an adapter circuit 710 and an enhanced superspeed function circuit 720. The adapter circuit 710 may be, for example, a device router that supports USB specifications such as USB3 and USB4, and TBT specifications such as TBT3, TBT4, and TBT5. The enhanced superspeed function circuit 720 may be, for example, a module circuit that supports the USB3.2 specification to implement the enhanced superspeed transmission function.

[0029] Specifically, the adapter circuit 710 is coupled to the uplink port interface circuit 512 and the disk array controller 520. The adapter circuit 710 is used to convert data conforming to the USB4, USB3, TBT, or PCIe specifications and to transmit the converted data.

[0030] In detail, the adapter circuit 710 includes a control adapter 711, a time management unit (TMU) 712, a channel adapter 713, a USB adapter 714, and a PCIe adapter 715. The time management unit 712 is coupled to multiple adapters 711 and 713-715. The time management unit 712 is used to synchronize these adapters 711 and 713-715. The control adapter 711 is also coupled to the channel adapter 713, the USB adapter 714, and the PCIe adapter 715. The control adapter 711 is used to control these adapters 713-715.

[0031] In addition, the channel adapter 713 is also coupled to the upstream port interface circuit 512. The channel adapter 713 is used to process (including convert) data conforming to the USB4 / TBT specification, a compatible USB specification, or a PCIe specification, and to transmit the processed data. The USB adapter 714 is also coupled to the enhanced high-speed function circuit 720 through the upstream port interface circuit 512. The USB adapter 714 is used to process data conforming to the USB3 or PCIe specification, and to transmit the processed data. The PCIe adapter 715 is also coupled to the disk array controller 520. The PCIe adapter 715 is used to process data conforming to the PCIe, USB3, or USB4 / TBT specification, and to transmit the processed data.

[0032] In this embodiment, the enhanced high-speed function circuit 720 is coupled to the uplink port interface circuit 512, the disk array controller 520, and the downlink port interface circuit 513. The enhanced high-speed function circuit 720 is used to convert data conforming to the USB3 or PCIe specifications and transmit the converted data.

[0033] In detail, the enhanced high-speed function circuitry 720 includes a virtual high-speed non-volatile memory (NVM Express, NVMe) host 721, a USB 2.0 device controller 722, and a USB 3.2 device controller 723. The virtual NVMe host 721 is coupled to the USB 2.0 device controller 722, the USB 3.2 device controller 723, the disk array controller 320, and the downstream port interface circuitry 513. The virtual NVMe host 721 is used to control the USB 2.0 device controller 722 and the USB 3.2 device controller 723, and to assign the desired access target among the multiple storage devices 221-224.

[0034] In addition, the USB 2.0 device controller 722 is also coupled to the upstream port interface circuit 512. The USB 2.0 device controller 722 is used to process data conforming to the USB2 or PCIe specifications and to transmit the processed data. The USB 3.2 device controller 723 is also coupled to the USB adapter 714 through the upstream port interface circuit 512. The USB 3.2 device controller 723 is used to process data conforming to the USB3 or PCIe specifications and to transmit the processed data.

[0035] In this embodiment, the uplink port interface circuit 512 includes a demultiplexer 731, a USB 3.2 Physical Coding Sub-layer (PCS) circuit 732, and a multiplexer 733. The input of the demultiplexer 731 is coupled to connector 201. Multiple outputs of the demultiplexer 731 are coupled to channel adapter 713 and the USB 3.2 PCS circuit 732. The USB 3.2 PCS circuit 732 is also coupled to an input of the multiplexer 733. Another input of the multiplexer 733 is coupled to a USB adapter 714. The output of the multiplexer 733 is coupled to a USB 3.2 device controller 723.

[0036] In RAID applications, the uplink port interface circuit 512 has multiple transmission paths P1 to P4 between the connector 201 and the routing circuit 511. These transmission paths P1 to P4 support USB specifications such as USB3 and USB4, as well as TBT specifications such as TBT3, TBT4, and TBT5.

[0037] In detail, in the transmission path P1, the uplink port interface circuit 512 transmits data conforming to the USB4 specification between the connector 201 and the adapter circuit 710 through the sideband (SB) channel (i.e., SBTX / RX).

[0038] In transmission path P2, the uplink port interface circuit 512 couples the connector 201 and the channel adapter 713 together via the demultiplexer 731 to transmit USB3 compliant data between the connector 201 and the adapter circuit 710. Alternatively, the uplink port interface circuit 512 couples the connector 201 and the USB3.2 device controller 723 together via the demultiplexer 731, the USB3.2 PCS circuit 732, and the multiplexer 733. Thus, in transmission path P2, the uplink port interface circuit 512 transmits USB3.2 compliant data between the connector 201 and the enhanced ultra-high speed function circuit 720.

[0039] In the transmission path P3, the uplink port interface circuit 512 transmits data conforming to the USB2 specification between the connector 201 and the USB2.0 device controller 722 through the data channel (i.e., D+ / D-).

[0040] In this embodiment, the downlink port interface circuit 513 includes a plurality of PCIe switch controllers 741-742 and a PCIe physical layer circuit 743. The PCIe switch controller 741 may be, for example, a PCIe uplink switch controller. The PCIe switch controller 742 may be, for example, a PCIe downlink switch controller. These PCIe switch controllers 741-742 are coupled to the disk array controller 520 and the routing circuit 511, and are also coupled to the PCIe physical layer circuit 743.

[0041] In RAID applications, the downlink port interface circuit 513 has multiple transmission paths P4-P5 between the routing circuit 511 and multiple storage devices 221-224. These transmission paths P4-P5 support the PCIe specification.

[0042] In detail, in transmission path P4, the PCIe switch controller 741 processes data conforming to the PCIe specification and transmits the processed data between the virtual NVMe host 721 and the PCIe physical layer circuitry 743. In transmission path P5, the PCIe switch controller 742 processes data conforming to the PCIe specification and transmits the processed data between the PCIe physical layer circuitry 743 and the PCIe adapter 715. Thus, the processed data conforms to the PCIe specification and is accessed to multiple storage devices 221-224 via the PCIe physical layer circuitry 743.

[0043] It should be noted that the disk array controller 520 can be integrated with multiple PCIe switch controllers 741-742 in the same circuit module. In this way, the control circuit 500 can reduce the layout area, thereby reducing production costs.

[0044] In summary, the control circuit of this embodiment integrates the disk array controller and the bridge controller onto the same chip, thereby avoiding the need for additional external devices in RAID applications and improving data access performance. The control circuit can also reduce the layout area, thereby reducing production costs.

[0045] Although the present invention has been disclosed above by way of embodiments, it is not intended to limit the present invention. Anyone skilled in the art can make some modifications and refinements without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be determined by the appended claims. [Simplified Explanation of the Diagram]

[0046] FIG1 is a circuit block diagram of a control circuit according to an embodiment of the present invention. FIG2 is a circuit block diagram of a control circuit according to another embodiment of the present invention. FIG3 is a circuit block diagram of a control circuit according to another embodiment of the present invention.

Claims

1. A control circuit suitable for bridging a host device and multiple storage devices, comprising: A bridging controller includes an uplink port interface circuit, a downlink port interface circuit, and a routing circuit, wherein the uplink port interface circuit is used to couple the host device and the routing circuit according to a first transmission standard, and the downlink port interface circuit is used to couple the routing circuit and the storage devices according to a second transmission standard; and a disk array controller, coupled to the routing circuit and the downlink port interface circuit, is used to access the storage devices through the downlink port interface circuit, wherein the routing circuit includes: a adapter circuit, coupled to the uplink port interface circuit and the disk array controller, for converting data conforming to the USB4, USB3, TBT, or PCIe specifications for transmission of converted data; and an enhanced high-speed function circuit, coupled to the uplink port interface circuit, the disk array controller, and the downlink port interface circuit, for converting data conforming to the USB3 or PCIe specifications for transmission of converted data.

2. The control circuit as claimed in claim 1, wherein the bridge controller and the disk array controller are disposed on the same chip.

3. The control circuit as claimed in claim 1, wherein the first transmission specification includes the Universal Serial Bus (USB) specification or the Thunderbolt (TBT) specification.

4. The control circuitry as claimed in claim 1, wherein the second transmission specification includes the high-speed peripheral component interconnect (PCI Express, PCIe) specification.

5. The control circuit as claimed in claim 1, wherein the downlink port interface circuit includes: Multiple PCIe switch controllers are coupled to the disk array controller and the routing circuitry; And a PCIe physical layer circuit, coupled to these PCIe switch controllers.

6. The control circuit as claimed in claim 1, wherein the adapter circuit includes: A single-channel adapter is used to couple the uplink port interface circuitry. A USB adapter is coupled to the enhanced ultra-high speed function circuit through the uplink port interface circuit; A PCIe adapter is coupled to the disk array controller; And a control adapter coupled to the channel adapter, the USB adapter and the PCIe adapter.

7. The control circuit as claimed in claim 6, wherein the enhanced ultra-high-speed function circuit comprises: A USB 2.0 device controller is coupled to the uplink port interface circuitry; A USB 3.2 device controller is coupled to the USB adapter through the uplink port interface circuitry; And a Virtual High-Speed ​​Non-Volatile Memory (NVM Express, NVMe) host, coupled to the USB 2.0 device controller, the USB 3.2 device controller, the disk array controller, and the downstream port interface circuitry.

8. The control circuitry as claimed in claim 7, wherein the uplink port interface circuitry includes: A USB 3.2 Physical Coding Sub-layer (PCS) circuit; A demultiplexer has an input terminal coupled to the host device, and multiple output terminals of the demultiplexer coupled to the channel adapter and the USB 3.2 PCS circuit. And a multiplexer having multiple inputs coupled to the USB adapter and the USB 3.2 PCS circuit, the output of the multiplexer being coupled to the USB 2.0 device controller.

9. The control circuitry of claim 1, wherein the storage devices include at least one of a solid-state disk (SSD) and at least one hard disk drive (HDD).

Images