Circuit design method, circuit design device, and non-transitory computer readable storage medium

Abstract

A circuit design method, a circuit design device, and a non-transitory computer readable storage medium are disclosed herein. The circuit design method is executed by a processor reading at least command stored in a memory. The circuit design method includes following steps: providing a plurality of via pillar arrangements, wherein every via pillar arrangement of the plurality of via pillar arrangements includes a via pillar number and a via pillar spacing; providing a plurality of standard cells; calculating a plurality of pin overlapping numbers between every via pillar arrangement of the plurality of via pillar arrangements and the plurality of standard cells; and selecting a via pillar arrangement of the plurality of via pillar arrangements corresponding to a minimum pin overlapping number of the plurality of pin overlapping numbers as a target via pillar arrangement.

Description

[Technical Field]

[0001] This case relates to circuit design methods, circuit design apparatuses and non-transitory computer-readable recording media, and in particular to circuit design methods, circuit design apparatuses and non-transitory computer-readable recording media that improve pin accessibility and loop-around linearity. [Previous Technology]

[0002] During circuit development, in order to ensure the integrity of the power mesh and its subsequent adjustability, power planning usually involves creating the power mesh and via pillars before the layout and routing stages. However, the power mesh and via pillars share the routing resources of the metal layer with the signal routing, which can easily hinder the access area and routability of pins within a standard cell.

[0003] While standard cells can be slightly adjusted in position during circuit layout or the number of path pillars can be reduced during power planning to increase pin access area and loopback linearity, the adjustable position and loopback linearity are relatively limited in high-density standard cell placement areas. Furthermore, reducing the number of path pillars during power planning leads to more severe voltage drop (IR drop) and electromigration, thereby affecting the performance and reliability of integrated circuits (ICs). [Summary of the Invention]

[0004] In view of the shortcomings of the prior art, one of the objectives of this invention is (but not limited to) to provide a circuit design method, a circuit design apparatus and a non-transitory computer-readable recording medium to improve the shortcomings of the prior art.

[0005] In some embodiments, this invention provides a circuit design method executed by a processor reading at least one instruction stored in memory. The circuit design method includes the following steps: providing a complex array of via pillar arrangements, wherein each via pillar arrangement in the complex array includes a number of via pillars and a via pillar spacing; providing a plurality of standard components; calculating the number of times each via pillar arrangement in the complex array overlaps with a plurality of pins of the plurality of standard components; and selecting a via pillar arrangement from the complex array corresponding to the minimum number of pin overlaps among the plurality of pin overlaps as the target via pillar arrangement.

[0006] In some embodiments, the circuit design apparatus includes memory and a processor. The memory is used to store at least one instruction. The processor is used to read at least one instruction to perform the following steps: providing a complex array of path pillar arrangements, wherein each path pillar arrangement in the complex array of path pillar arrangements includes a number of path pillars and a path pillar spacing; providing a plurality of standard components; calculating the number of times each path pillar arrangement in the complex array of path pillar arrangements overlaps with a plurality of pins of the plurality of standard components; and selecting a path pillar arrangement in the complex array of path pillar arrangements corresponding to the smallest number of pin overlaps among the plurality of pin overlaps as the target path pillar arrangement.

[0007] In some embodiments, this invention provides a computer-readable recording medium storing a computer program for executing a circuit design method. The circuit design method includes: providing a complex array of path pillar arrangements, wherein each path pillar arrangement in the complex array includes a number of path pillars and a path pillar spacing; providing a plurality of standard components; calculating the number of times each path pillar arrangement in the complex array overlaps with a plurality of pins of the plurality of standard components; and selecting a path pillar arrangement from the complex array corresponding to the smallest number of pin overlaps among the plurality of pin overlaps as the target path pillar arrangement.

[0008] The technical means embodied in the embodiments of this invention can improve at least one of the disadvantages of the prior art. The circuit design method, circuit design apparatus and non-transitory computer-readable recording medium of this invention can improve pin access area and routability without reducing the number of copper pillars in the path.

[0009] Regarding the features, implementation and effects of this case, the preferred embodiments are described in detail below with reference to the drawings.

Implementation Method

[0010] All terms used herein have their common meanings. The definitions of the above terms in commonly used dictionaries, and any examples of the use of any term discussed herein, are merely illustrative and should not limit the scope or meaning of this application. Similarly, this application is not limited to the various embodiments shown in this specification.

[0011] The terms "coupled" or "connected" as used herein can refer to two or more components making direct physical or electrical contact with each other, or making indirect physical or electrical contact with each other, or two or more components operating or moving with each other. As used herein, the term "circuit" can be a device in which at least one transistor and / or at least one active or passive component are connected in a certain manner to process signals.

[0012] As used herein, the term "and / or" includes any combination of one or more of the listed related items. In this document, the terms first, second, third, etc., are used to describe and identify individual elements. Therefore, a first element in this document may also be referred to as a second element without departing from the intent of this case. For ease of understanding, similar elements in the various figures will be designated with the same reference numerals.

[0013] In order to improve the problem that the position and routability are relatively limited in the high-density standard cell placement area, and to improve the problem that reducing the number of via pillars will lead to more severe voltage drop and electromigration, this invention proposes a circuit design method, a circuit design device and a non-transitory computer-readable recording medium, which are described in detail below.

[0014] Figure 1 is a schematic diagram of a circuit design apparatus 100 according to some embodiments of this invention. As shown, the circuit design apparatus 100 includes a processor 110 and a memory 120. The memory 120 is used to store at least one instruction. The processor 110 is used to read at least one instruction to execute a circuit design process. For ease of understanding of the operation of the circuit design apparatus 100, please also refer to Figure 2, which is a flowchart according to some circuit design method 200.

[0015] Please refer to step 210 in Figure 2, which provides a complex array of copper pillar arrangements, wherein each group of copper pillar arrangements in the complex array includes the number of copper pillars and the spacing between them. For example, please refer to Figure 3, the circuit design method 200 of this invention provides a first group of copper pillar arrangements 310 and a second group of copper pillar arrangements 320. The first group of copper pillar arrangements 310 includes two copper pillars 311 and 312. Therefore, the number of copper pillars in the first group of copper pillar arrangements 310 is two. In addition, the distance between the copper pillars 311 and 312 is one copper pillar spacing (SP).

[0016] Furthermore, the second group of copper pillars arrangement 320 includes two copper pillars 321 and 322. Therefore, the number of copper pillars in the second group of copper pillars arrangement 320 is two. In addition, the distance between copper pillars 321 and 322 is three copper pillar intervals SP. It should be noted that the dotted lines where copper pillars 311, 312, 321, and 322 are located are the trace positions specified by the circuit design, and the copper pillars must be placed on the trace positions. The interval between two trace positions is one copper pillar interval SP in this case. However, this case is not limited to the above embodiment. In other embodiments, the first group of copper pillars arrangement 310 and the second group of copper pillars arrangement 320 may further include metal layer information, and the number of copper pillars and the copper pillar interval of the first group of copper pillars arrangement 310 and the second group of copper pillars arrangement 320 can adopt other suitable values, depending on the actual needs.

[0017] Please refer to step 220 of Figure 2, where a plurality of standard components are provided. For example, please refer to Figure 3, where the circuit design method 200 of this invention provides a plurality of standard components 330 and 340.

[0018] Please refer to step 230 in Figure 2 to calculate the number of times each group of copper pillars in the complex array of path arrangement overlaps with the multiple pins of the multiple standard components. For example, please refer to Figure 3. The circuit design method 200 of this case can calculate the number of times the first pin of the first group of copper pillars 310 overlaps with the first pin of the multiple standard components 330 and 340, and can calculate the number of times the second pin of the second group of copper pillars 320 overlaps with the second pin of the multiple standard components 330 and 340.

[0019] Please refer to step 240 in Figure 2, and select a group of path copper pillar arrangements from the multiple path copper pillar arrangements corresponding to the smallest number of pin overlaps among the multiple pin overlaps as the target path copper pillar arrangement. For example, please refer to Figure 3, the circuit design method 200 of this case can compare the number of first pin overlaps between the first group of path copper pillar arrangements 310 and the multiple standard components 330, 340 with the number of second pin overlaps between the second group of path copper pillar arrangements 320 and the multiple standard components 330, 340. If the number of first pin overlaps is less than the number of second pin overlaps, the first group of path copper pillar arrangements 310 corresponding to the number of first pin overlaps is selected as the target path copper pillar arrangement.

[0020] In some embodiments, after selecting the first group of copper pillar arrangements 310 as the target copper pillar arrangement, it is necessary to determine whether the target copper pillar arrangement conforms to the design rule. If the target copper pillar arrangement conforms to the design rule, the subsequent circuit design is performed using the target copper pillar arrangement. In addition, if the target copper pillar arrangement does not conform to the design rule, the next group of copper pillar arrangements with the minimum number of pin overlaps is selected sequentially until one group conforms to the design rule, or until no group conforms at all.

[0021] Figures 4 to 11 are schematic diagrams illustrating the relationship between a channel copper pillar and a standard component according to some embodiments of this invention. Referring to Figure 4, the overlap condition between the specified channel copper pillar arrangement 310 and the plurality of standard components 330 and 340 is that they overlap at two signal pins. As shown in the figure, the channel copper pillar arrangement 310 and the standard component 330 overlap at two signal pins, and this overlap is counted once.

[0022] Please refer to Figure 5. Figure 5 still specifies that the overlap condition between the copper pillar arrangement 310 and the plurality of standard components 330 and 340 is that they overlap at two signal pins. As shown in the figure, the copper pillar arrangement 310 and the standard component 340 overlap at two signal pins, and thus the overlap is calculated once.

[0023] Please refer to Figure 6. Figure 6 still specifies that the overlap condition between the copper pillar arrangement 310 and the plurality of standard components 330 and 340 is that they overlap at two signal pins. As shown in the figure, the copper pillar arrangement 310 and the standard component 340 overlap at two signal pins, and thus the overlap is calculated once.

[0024] In summary, if the overlap condition between the specified channel copper pillar arrangement 310 and the plurality of standard components 330 and 340 is that they overlap at two signal pins, then the number of times the pins of the channel copper pillar arrangement 310 and the standard component 330 overlap is 1 time, the number of times the pins of the channel copper pillar arrangement 310 and the standard component 340 overlap is 2 times, and the total number of times the pins of the channel copper pillar arrangement 310 and the plurality of standard components 330 and 340 overlap is 3 times.

[0025] Furthermore, please refer to Figure 7. The overlap condition between the specified path copper pillar arrangement 320 and the plurality of standard components 330 and 340 is that they overlap at two signal pins. As shown in the figure, the path copper pillar arrangement 320 and the standard component 330 overlap only at one signal pin, thus the overlap is calculated to be 0 times.

[0026] Please refer to Figure 8. Figure 8 still specifies that the overlap condition between the copper pillar arrangement 320 and the plurality of standard components 330 and 340 is that they overlap at two signal pins. As shown in the figure, the copper pillar arrangement 320 and the standard component 330 overlap only at one signal pin, so the overlap is calculated to be 0 times.

[0027] Please refer to Figure 9. Figure 9 still specifies that the overlap condition between the copper pillar arrangement 320 and the plurality of standard components 330 and 340 is that they overlap at two signal pins. As shown in the figure, the copper pillar arrangement 320 and the standard component 340 overlap only at one signal pin, so the overlap is calculated to be 0 times.

[0028] Please refer to Figure 10. Figure 10 still specifies that the overlap condition between the copper pillar arrangement 320 and the plurality of standard components 330 and 340 is that they overlap at two signal pins. As shown in the figure, the copper pillar arrangement 320 and the standard component 340 overlap only at one signal pin, so the overlap is calculated to be 0 times.

[0029] Please refer to Figure 11. Figure 11 still specifies that the overlap condition between the copper pillar arrangement 320 and the plurality of standard components 330 and 340 is that they overlap at two signal pins. As shown in the figure, the copper pillar arrangement 320 and the standard component 340 overlap only at one signal pin, so the overlap is calculated to be 0 times.

[0030] In summary, if the overlap condition between the specified channel copper pillar arrangement 320 and the plurality of standard components 330 and 340 is that they overlap at two signal pins, then the number of times the pins of the channel copper pillar arrangement 320 overlap with the standard component 330 is 0, the number of times the pins of the channel copper pillar arrangement 320 overlap with the standard component 340 is 0, and the total number of times the pins of the channel copper pillar arrangement 320 overlap with the plurality of standard components 330 and 340 is 0.

[0031] It can be seen that the number of pin overlaps between the copper pillar arrangement 320 and the plurality of standard components 330 and 340 is only 0 times, while the number of pin overlaps between the copper pillar arrangement 310 and the plurality of standard components 330 and 340 is 3 times. The circuit design method 200 of this case will select the copper pillar arrangement 320 corresponding to the minimum number of pin overlaps as the target copper pillar arrangement.

[0032] The circuit design method 200 of this case can calculate the number of overlaps between each group of path copper pillar arrangements and multiple pins of multiple standard components according to the overlap condition and different weights, as explained below. Figures 12 to 20 are schematic diagrams illustrating the relationship between path copper pillars and standard components according to some embodiments of this case. Referring to Figure 12, the overlap condition between the path copper pillar arrangement 310 and multiple standard components 330 and 340 is specified as overlapping at one signal pin, with standard component 330 having a weight of 1 and standard component 340 having a weight of 2. As shown in the figure, the path copper pillar arrangement 310 and standard component 330 overlap at one signal pin, thus calculating one overlap.

[0033] Please refer to Figure 13. Figure 13 still specifies that the overlap condition between the copper pillar arrangement 310 and the plurality of standard components 330 and 340 is that they overlap at one signal pin. As shown in the figure, the copper pillar arrangement 310 and the standard component 330 overlap at one signal pin, and this overlap is counted once.

[0034] Please refer to Figure 14. Figure 14 still specifies that the overlap condition between the copper pillar arrangement 310 and the multiple standard components 330 and 340 is that they overlap at one point. As shown in the figure, the copper pillar arrangement 310 and the standard component 340 overlap at one signal pin, thus calculating one overlap. Since the weight of the standard component 340 is 2, one overlap is multiplied by the weight 2, which is summarized as two overlaps.

[0035] Please refer to Figure 15. Figure 15 still specifies that the overlap condition between the copper pillar arrangement 310 and the plurality of standard components 330 and 340 is that they overlap at one signal pin. As shown in the figure, the copper pillar arrangement 310 overlaps with the standard component 340 at one signal pin, thus calculating one overlap. Since the weight of the standard component 340 is 2, one overlap is multiplied by the weight 2, which is summarized as two overlaps.

[0036] In summary, if the overlap condition between the specified channel copper pillar arrangement 310 and the plurality of standard components 330 and 340 is that they overlap at one signal pin, then the number of times the pins of the channel copper pillar arrangement 310 and the standard component 330 overlap is 2. After adjusting according to weight 2, the number of times the pins of the channel copper pillar arrangement 310 and the standard component 340 overlap is 4. The total number of times the pins of the channel copper pillar arrangement 310 and the plurality of standard components 330 and 340 overlap is 6.

[0037] Furthermore, referring to Figure 16, the overlap condition between the specified path copper pillar arrangement 320 and the plurality of standard components 330, 340 is that they overlap at one signal pin. As shown in the figure, the path copper pillar arrangement 320 overlaps with the standard component 330 at one signal pin, and this overlap is counted once.

[0038] Please refer to Figure 17. Figure 17 still specifies that the overlap condition between the copper pillar arrangement 320 and the plurality of standard components 330 and 340 is that they overlap at one signal pin. As shown in the figure, the copper pillar arrangement 320 and the standard component 330 overlap at one signal pin, and this overlap is counted once.

[0039] Please refer to Figure 18. Figure 18 still specifies that the overlap condition between the copper pillar arrangement 320 and the plurality of standard components 330 and 340 is that they overlap at one signal pin. As shown in the figure, the copper pillar arrangement 320 overlaps with the standard component 340 at one signal pin, thus calculating one overlap. Since the weight of the standard component 340 is 2, one overlap is multiplied by the weight 2, which is summarized as two overlaps.

[0040] Please refer to Figure 19. Figure 19 still specifies that the overlap condition between the copper pillar arrangement 320 and the plurality of standard components 330 and 340 is that they overlap at one signal pin. As shown in the figure, the copper pillar arrangement 320 overlaps with the standard component 340 at one signal pin, thus calculating one overlap. Since the weight of the standard component 340 is 2, one overlap is multiplied by the weight 2, which is summarized as two overlaps.

[0041] Please refer to Figure 20. Figure 20 still specifies that the overlap condition between the copper pillar arrangement 320 and the plurality of standard components 330 and 340 is that they overlap at one signal pin. As shown in the figure, the copper pillar arrangement 320 overlaps with the standard component 340 at one signal pin. This is calculated as one overlap. Since the weight of the standard component 340 is 2, one overlap is multiplied by the weight 2, which is summarized as two overlaps.

[0042] In summary, if the overlap condition between the specified channel copper pillar arrangement 320 and the plurality of standard components 330 and 340 is that they overlap at one signal pin, then the number of times the pins of the channel copper pillar arrangement 320 and the standard component 330 overlap is 2. After adjusting according to weight 2, the number of times the pins of the channel copper pillar arrangement 320 and the standard component 340 overlap is 6. The total number of times the pins of the channel copper pillar arrangement 320 and the plurality of standard components 330 and 340 overlap is 8.

[0043] It can be seen that the number of times the pins of the copper pillar arrangement 310 overlap with the pins of the plurality of standard components 330 and 340 is 6, while the number of times the pins of the copper pillar arrangement 320 overlap with the pins of the plurality of standard components 330 and 340 is 8. The circuit design method 200 of this case will select the copper pillar arrangement 310 corresponding to the minimum number of pin overlaps as the target copper pillar arrangement.

[0044] The aforementioned circuit design method 200 can be implemented as a computer program and stored in a non-transitory computer-readable recording medium, so that the computer reads this non-transitory computer-readable recording medium and executes the circuit design method 200. The non-transitory computer-readable recording medium can be read-only memory, flash memory, floppy disk, hard disk, optical disk, USB flash drive, magnetic tape, a database accessible by network, or any computer-readable recording medium with the same function that can be easily conceived by those skilled in the art. The aforementioned circuit design method 200 can also be implemented by integrating the computer program with one or more processors or chips.

[0045] It should be noted that this application is not limited to the embodiments shown in Figures 1 to 20, but is only used to illustrate one implementation method of this application to facilitate understanding of the technology. The scope of this application shall be determined by the scope of the invention application. Modifications and refinements made by those skilled in the art to the embodiments of this application without departing from the spirit of this application still fall within the scope of the invention application.

[0046] The technical means embodied in the embodiments of this invention can improve at least one of the disadvantages of the prior art. During the power planning stage, the circuit design method, circuit design apparatus, and non-transitory computer-readable recording medium of this invention can employ a circuit design method that reduces pin accessibility without reducing the number of copper pillars in the path, thereby improving pin accessibility area and routability during the subsequent layout and routing stages. Furthermore, the circuit design method, circuit design apparatus, and non-transitory computer-readable recording medium of this invention can provide corresponding power planning methods for different circuit designs.

[0047] Although the embodiments of this case are described above, these embodiments are not intended to limit this case. Those skilled in the art can make changes to the technical features of this case based on the explicit or implicit content of this case. All such changes may fall within the scope of patent protection sought in this case. In other words, the scope of patent protection in this case shall be determined by the scope of the patent application in this specification. [Simplified Explanation of the Diagram]

[0048] Figure 1 is a schematic diagram of a circuit design device according to some embodiments of the present invention; Figure 2 is a flowchart of a circuit design method according to some embodiments of the present invention; Figure 3 is a schematic diagram of the relationship between a copper pillar and a standard component according to some embodiments of the present invention; Figure 4 is a schematic diagram of the relationship between a copper pillar and a standard component according to some embodiments of the present invention; Figure 5 is a schematic diagram of the relationship between a copper pillar and a standard component according to some embodiments of the present invention; Figure 6 is a schematic diagram of the relationship between a copper pillar and a standard component according to some embodiments of the present invention; Figure 7 is a schematic diagram of the relationship between a copper pillar and a standard component according to some embodiments of the present invention; Figure 8 is a schematic diagram of the relationship between a copper pillar and a standard component according to some embodiments of the present invention; Figure 9 is a schematic diagram of the relationship between a copper pillar and a standard component according to some embodiments of the present invention; Figure 10 is a schematic diagram of the relationship between a copper pillar and a standard component according to some embodiments of the present invention; Figure 11 is a schematic diagram of the relationship between a copper pillar and a standard component according to some embodiments of the present invention; Figure 12 is a schematic diagram of the relationship between a copper pillar and a standard component according to some embodiments of the present invention. Figure 13 is a schematic diagram illustrating the relationship between a copper pillar and a standard component according to some embodiments of this invention; Figure 14 is a schematic diagram illustrating the relationship between a copper pillar and a standard component according to some embodiments of this invention; Figure 15 is a schematic diagram illustrating the relationship between a copper pillar and a standard component according to some embodiments of this invention; Figure 16 is a schematic diagram illustrating the relationship between a copper pillar and a standard component according to some embodiments of this invention; Figure 17 is a schematic diagram illustrating the relationship between a copper pillar and a standard component according to some embodiments of this invention; Figure 18 is a schematic diagram illustrating the relationship between a copper pillar and a standard component according to some embodiments of this invention; Figure 19 is a schematic diagram illustrating the relationship between a copper pillar and a standard component according to some embodiments of this invention; and Figure 20 is a schematic diagram illustrating the relationship between a copper pillar and a standard component according to some embodiments of this invention.

Claims

1. A circuit design method, executed by a processor reading at least one instruction stored in a memory, comprising: providing a complex array of path pillar arrangements, wherein each path pillar arrangement in the complex array of path pillar arrangements includes a number of path pillars and a path pillar spacing; providing a plurality of standard components; calculating the number of times each path pillar arrangement in the complex array of path pillar arrangements overlaps with a plurality of pins of the plurality of standard components; and selecting a path pillar arrangement in the complex array of path pillar arrangements corresponding to a minimum number of pin overlaps among the plurality of pin overlaps as a target path pillar arrangement.

2. The circuit design method as described in claim 1 further includes: determining whether the copper pillar arrangement of the target path conforms to a design rule; and if the copper pillar arrangement of the target path conforms to the design rule, performing a circuit design based on the copper pillar arrangement of the target path.

3. The circuit design method as described in claim 1, wherein the multiple array of copper pillar arrangements includes a first array of copper pillar arrangements and a second array of copper pillar arrangements, the multiple pin overlap times include a first pin overlap time and a second pin overlap time, wherein selecting the array of copper pillar arrangements corresponding to the minimum pin overlap time among the multiple pin overlap times as the target array of copper pillar arrangements includes: comparing the first pin overlap time of the first array of copper pillar arrangements with the multiple standard components and the second pin overlap time of the second array of copper pillar arrangements with the multiple standard components; and if the first pin overlap time is less than the second pin overlap time, selecting the first array of copper pillar arrangements corresponding to the first pin overlap time as the target array of copper pillar arrangements.

4. The circuit design method as claimed in claim 1, wherein the plurality of standard components includes a first standard component and a second standard component, wherein providing the plurality of standard components includes: providing the first standard component, wherein the first standard component includes a first weight; and providing the second standard component, wherein the second standard component includes a second weight.

5. The circuit design method as described in claim 4, wherein calculating the number of overlaps between each group of path pillars in the complex array of path pillars and the plurality of pins of the plurality of standard components comprises: specifying an overlap condition between each group of path pillars in the complex array of path pillars and the first standard component and the second standard component; and calculating the number of overlaps between each group of path pillars in the complex array of path pillars and the plurality of pins of the first standard component and the second standard component based on the overlap condition, the first weight, and the second weight.

6. A circuit design apparatus, comprising: a memory for storing at least one instruction; and a processor for reading the at least one instruction from the memory to perform the following steps: providing a complex array of path pillar arrangements, wherein each group of path pillar arrangements in the complex array includes a number of path pillars and a path pillar spacing; providing a plurality of standard components; calculating the number of times each group of path pillar arrangements in the complex array overlaps with a plurality of pins of the plurality of standard components; and selecting a group of path pillar arrangements in the complex array corresponding to the minimum number of pin overlaps among the plurality of pin overlaps as a target path pillar arrangement.

7. The circuit design apparatus as described in claim 6, wherein the processor further reads the at least one instruction from the memory to perform the following steps: determining whether the target path copper pillar arrangement conforms to a design rule; and if the target path copper pillar arrangement conforms to the design rule, performing a circuit design using the target path copper pillar arrangement.

8. The circuit design apparatus as described in claim 6, wherein the plurality of path pillar arrangements includes a first path pillar arrangement and a second path pillar arrangement, the plurality of pin overlap times includes a first pin overlap time and a second pin overlap time, wherein the processor further reads the at least one instruction from the memory to perform the following steps: comparing the first pin overlap time of the first path pillar arrangement with that of the plurality of standard components and the second pin overlap time of the second path pillar arrangement with that of the plurality of standard components; and if the first pin overlap time is less than the second pin overlap time, selecting the first path pillar arrangement corresponding to the first pin overlap time as the target path pillar arrangement.

9. The circuit design apparatus of claim 6, wherein the plurality of standard elements includes a first standard element and a second standard element, wherein the processor further reads the at least one instruction from the memory to perform the following steps: providing the first standard element, wherein the first standard element includes a first weight; and providing the second standard element, wherein the second standard element includes a second weight.

10. A non-transitory computer-readable recording medium storing a computer program for executing a circuit design method, wherein the circuit design method comprises: providing a complex array of path pillar arrangements, wherein each path pillar arrangement in the complex array of path pillar arrangements includes a number of path pillars and a path pillar spacing; providing a plurality of standard components; calculating the number of times each path pillar arrangement in the complex array of path pillar arrangements overlaps with a plurality of pins of the plurality of standard components; and selecting a path pillar arrangement in the complex array of path pillar arrangements corresponding to the minimum number of pin overlaps among the plurality of pin overlaps as a target path pillar arrangement.

Images