Micro-led pixel circuit with leakage balancing structure
Patent Information
- Application Number
- TW114108331
- Authority / Receiving Office
- TW · TW
- Patent Type
- Applications
- Current Assignee / Owner
- Filing Date
- 2025-03-06
- Publication Date
- 2026-09-16
- Estimated Expiration
- 2045-03-05
AI Technical Summary
Conventional micro-LED pixel circuits with a 2T1C architecture suffer from leakage currents that cause voltage deviations, leading to uneven driving currents and display quality issues in ultra-high resolution panels due to the small pixel area and ultra-low capacitance of the capacitor.
A micro-LED pixel circuit with a leakage current balancing architecture using a 4T1C, 4T2C, 5T1C, or 5T2C configuration, incorporating specific transistor polarities and capacitors to balance leakage currents, ensuring consistent driving current through CMOS process technology.
The proposed circuit achieves leakage current balance, maintaining consistent driving current and improving display quality in ultra-high resolution panels by compensating for transistor leakage currents.
Smart Images
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Abstract
Description
[Technical Field]
[0001] This invention relates to display devices, and more particularly to a micro-light-emitting diode pixel circuit with a leakage current balancing architecture. [Previous Technology]
[0002] Please refer to Figure 1, which shows a schematic diagram of a conventional micro-light-emitting diode (LED) pixel circuit. As shown in Figure 1, the conventional LED pixel circuit 1 adopts a 2T1C (two transistors and one capacitor) architecture. The second transistor M2 of the LED pixel circuit 1 is turned on column by column through the scan line to write the voltage of the data line into the pixel and store it in the capacitor C1. The first transistor M1 generates current of different magnitudes to drive the LED. Afterwards, when the second transistor M2 is turned off, the charge stored in the capacitor C1 can still maintain the voltage difference between the gate and source terminals of the first transistor M1, so that the first transistor M1 continues to generate current, thereby reducing power consumption.
[0003] It should be noted that when the second transistor M2 is turned off, two leakage current paths may be generated: First, when the second transistor M2 is operating in the subcritical region (not completely turned off), there may be a bias voltage between the source and drain terminals of the second transistor M2, forming a subcritical leakage current ISUB; Second, if the second transistor M2 is an enhancement type, when the second transistor M2 is turned off, the reverse bias voltage of the PN junction between its drain and body terminals will be too large, forming a reverse PN junction leakage current IDR.
[0004] Because the pixel area of the ultra-high resolution display panel is very small, the capacitor C1 in the traditional micro-light-emitting diode pixel circuit 1 can only have an ultra-low capacitance value (e.g., 20fF). Once the second transistor M2 is turned off, a subcritical leakage current ISUB and a reverse PN junction leakage current IDR are generated. The capacitor C1 is completely unable to maintain a constant voltage value within the time of one frame, resulting in a deviation in the driving current and seriously affecting the quality of the display image. This needs to be further overcome. [Summary of the Invention]
[0005] Therefore, the present invention proposes a micro-light-emitting diode pixel circuit with a leakage current balance architecture, thereby effectively solving the above-mentioned problems encountered by the prior art.
[0006] A preferred embodiment of the present invention is a micro-light-emitting diode (LED) pixel circuit with a leakage current balancing architecture. In this embodiment, the micro-light-emitting diode (LED) pixel circuit with a leakage current balancing architecture includes a first transistor to a fourth transistor and a first capacitor. The first transistor is coupled between a first power supply voltage and a second power supply voltage, and the control terminal of the first transistor is coupled to a first node. The first power supply voltage is greater than the second power supply voltage. The second transistor is coupled between an operating voltage and the first node, and the control terminal of the second transistor is controlled by a first control signal. The third transistor is coupled between the first node and a second reference voltage, and the control terminal of the third transistor is controlled by the first reference voltage. The operating voltage is greater than the second reference voltage, which is greater than the first reference voltage. The first capacitor is coupled between the first node and the second node. The fourth transistor is coupled between a data voltage and the second node, and the control terminal of the fourth transistor is controlled by the first control signal. The first transistor, the second transistor, and the fourth transistor have a first polarity, and the third transistor has a second polarity opposite to the first polarity.
[0007] In one embodiment, the first power supply voltage is equal to the operating voltage and the first reference voltage is equal to the second power supply voltage.
[0008] In one embodiment, the micro-light-emitting diode pixel circuit further includes a second capacitor. The second capacitor is coupled between the operating voltage and the first node.
[0009] In one embodiment, the micro-light-emitting diode pixel circuit further includes a fifth transistor. The fifth transistor is coupled between the second node and the second reference voltage. The control terminal of the fifth transistor is controlled by a second control signal.
[0010] In one embodiment, the micro-LED pixel circuit further includes a second capacitor and a fifth transistor. The second capacitor is coupled between the operating voltage and the first node. The fifth transistor is coupled between the second node and the second reference voltage. The control terminal of the fifth transistor is controlled by a second control signal.
[0011] In one embodiment, during the data writing stage, the first control signal is the second level and the second control signal is the first level, causing the second transistor and the fourth transistor to be turned on and the first transistor, the third transistor and the fifth transistor to be turned off. The first node has an operating voltage and the second node has a data voltage, and the first level is higher than the second level.
[0012] In one embodiment, during the light emission stage, the first control signal is the first level and the second control signal is the second level, causing the first transistor and the fifth transistor to be turned on and the second transistor, the third transistor and the fourth transistor to be turned off. The second node is maintained at the second reference voltage and the first node has a coupling voltage related to the operating voltage and the data voltage. The first transistor will have a driving current flowing through it, and the first level is higher than the second level.
[0013] In one embodiment, during the light-emitting stage, the operating voltage is greater than the coupling voltage of the first node and greater than the second reference voltage, so that when the second transistor is turned off, the first leakage current and the second leakage current still charge the first node, and when the third transistor is turned off, the third leakage current and the fourth leakage current still discharge the first node, wherein the sum of the first leakage current and the second leakage current is equal to the sum of the third leakage current and the fourth leakage current, so as to achieve leakage balance at the first node.
[0014] In one embodiment, when the first polarity is P-type and the second polarity is N-type, the micro-light-emitting diode system is disposed between the first transistor and the second power supply voltage.
[0015] In one embodiment, when the first polarity is N-type and the second polarity is P-type, the micro-light-emitting diode system is disposed between the first power supply voltage and the first transistor.
[0016] Compared to the prior art, the micro-light-emitting diode pixel circuit with leakage current balance architecture proposed in this invention can be applied to ultra-high resolution display panels using a 4T1C (four transistors and one capacitor) architecture, a 4T2C (four transistors and two capacitors) architecture, a 5T1C (five transistors and one capacitor) architecture, or a 5T2C (five transistors and two capacitors) architecture. It can also use CMOS process design to adapt to extremely small pixel areas, thereby achieving leakage current balance and effectively solving the problem that the traditional micro-light-emitting diode pixel circuit using a 2T1C (two transistors and one capacitor) architecture is easily affected by transistor leakage current, resulting in uneven driving current.
Implementation Method
[0017] A preferred embodiment of the present invention is a micro-light-emitting diode pixel circuit with a leakage current balancing architecture. In this embodiment, the micro-light-emitting diode pixel circuit adopts a 4T1C (four transistors and one capacitor) architecture for use in ultra-high resolution display panels, and can be designed using CMOS process technology to adapt to extremely small pixel areas, but is not limited thereto.
[0018] Please refer to Figure 2, which shows a schematic diagram of the micro-light-emitting diode pixel circuit 2 with leakage current balancing architecture in this embodiment.
[0019] As shown in Figure 2, the micro-light-emitting diode (LED) pixel circuit 2 with leakage current balancing architecture in this embodiment has a 4T1C (four transistors and one capacitor) architecture. The micro-light-emitting diode (LED) pixel circuit 2 includes a first transistor M1, a second transistor M2, a third transistor M3, a fourth transistor M4, and a first capacitor C1. The first transistor M1, the second transistor M2, and the fourth transistor M4 have a first polarity, and the third transistor M3 has a second polarity opposite to the first polarity.
[0020] The first transistor M1 is coupled between the first power supply voltage ELVDD and the second power supply voltage ELVSS, and the control terminal of the first transistor M1 is coupled to the first node A. The second transistor M2 is coupled between the operating voltage VDD and the first node A, and the control terminal of the second transistor M2 is controlled by the first control signal S[N]. The third transistor M3 is coupled between the first node A and the second reference voltage V2, and the control terminal of the third transistor M3 is controlled by the first reference voltage V1. The fourth transistor M4 is coupled between the data voltage VDAT and the second node B, and the control terminal of the fourth transistor M4 is controlled by the first control signal S[N]. The first capacitor C1 is coupled between the first node A and the second node B.
[0021] In this embodiment, the main leakage current balancing architecture of the micro-light-emitting diode pixel circuit 2 is composed of the second transistor M2 and the third transistor M3, but is not limited thereto. The first power supply voltage ELVDD is greater than the second power supply voltage ELVSS. The operating voltage VDD is greater than the second reference voltage V2, which is greater than the first reference voltage V1. In practice, the first power supply voltage ELVDD can be equal to the operating voltage VDD and the first reference voltage V1 can be equal to the second power supply voltage ELVSS. In this case, the first power supply voltage ELVDD is greater than the second reference voltage V2, which is greater than the second power supply voltage ELVSS, but is not limited thereto.
[0022] It should be noted that the first transistor M1, the second transistor M2, and the fourth transistor M4 in Figure 2 have a first polarity of P-type, and the third transistor M3 has a second polarity of N-type. That is, the first transistor M1, the second transistor M2, and the fourth transistor M4 in Figure 2 are P-type transistors, and the third transistor M3 is an N-type transistor. At this time, the micro-light-emitting diode (LED) is positioned between the first transistor M1 and the second power supply voltage ELVSS.
[0023] Conversely, if the first transistor M1, the second transistor M2 and the fourth transistor M4 have an N-type first polarity and the third transistor M3 has a P-type second polarity, that is, the first transistor M1, the second transistor M2 and the fourth transistor M4 are N-type transistors and the third transistor M3 is a P-type transistor, then the micro-light-emitting diode (LED) needs to be changed to be set between the first power supply voltage ELVDD and the first transistor M1.
[0024] In another embodiment, as shown in FIG3, the micro-light-emitting diode pixel circuit 3 with leakage current balancing architecture in this embodiment has a 4T2C (four transistors and two capacitors) architecture. The micro-light-emitting diode pixel circuit 3 includes a first transistor M1, a second transistor M2, a third transistor M3, a fourth transistor M4, a first capacitor C1, and a second capacitor C2. Among them, the first transistor M1, the second transistor M2, and the fourth transistor M4 have a first polarity, and the third transistor M3 has a second polarity opposite to the first polarity.
[0025] The first transistor M1 is coupled between the first power supply voltage ELVDD and the second power supply voltage ELVSS, and the control terminal of the first transistor M1 is coupled to the first node A. The second transistor M2 is coupled between the operating voltage VDD and the first node A, and the control terminal of the second transistor M2 is controlled by the first control signal S[N]. The third transistor M3 is coupled between the first node A and the second reference voltage V2, and the control terminal of the third transistor M3 is controlled by the first reference voltage V1. The fourth transistor M4 is coupled between the data voltage VDAT and the second node B, and the control terminal of the fourth transistor M4 is controlled by the first control signal S[N]. The first capacitor C1 is coupled between the first node A and the second node B. The second capacitor C2 is coupled between the operating voltage VDD and the first node A.
[0026] In this embodiment, the main leakage current balancing architecture of the micro-light-emitting diode pixel circuit 3 is composed of the second transistor M2 and the third transistor M3, but is not limited thereto. The first power supply voltage ELVDD is greater than the second power supply voltage ELVSS; the operating voltage VDD is greater than the second reference voltage V2, which is greater than the first reference voltage V1. In fact, the first power supply voltage ELVDD can be equal to the operating voltage VDD and the first reference voltage V1 can be equal to the second power supply voltage ELVSS. In this case, the first power supply voltage ELVDD is greater than the second reference voltage V2, which is greater than the second power supply voltage ELVSS, but is not limited thereto.
[0027] It should be noted that the first transistor M1, the second transistor M2, and the fourth transistor M4 in Figure 3 have a first polarity of P-type, and the third transistor M3 has a second polarity of N-type. That is, the first transistor M1, the second transistor M2, and the fourth transistor M4 in Figure 3 are P-type transistors, and the third transistor M3 is an N-type transistor. At this time, the micro-light-emitting diode (LED) is disposed between the first transistor M1 and the second power supply voltage ELVSS.
[0028] Conversely, if the first transistor M1, the second transistor M2 and the fourth transistor M4 have an N-type first polarity and the third transistor M3 has a P-type second polarity, that is, the first transistor M1, the second transistor M2 and the fourth transistor M4 are N-type transistors and the third transistor M3 is a P-type transistor, then the micro-light-emitting diode (LED) needs to be changed to be set between the first power supply voltage ELVDD and the first transistor M1.
[0029] In another embodiment, as shown in FIG4, the micro-light-emitting diode pixel circuit 4 with leakage current balancing architecture in this embodiment has a 5T1C (five transistors and one capacitor) architecture. The micro-light-emitting diode pixel circuit 4 includes a first transistor M1, a second transistor M2, a third transistor M3, a fourth transistor M4, a fifth transistor M5, and a first capacitor C1. Among them, the first transistor M1, the second transistor M2, the fourth transistor M4, and the fifth transistor M5 have a first polarity, and the third transistor M3 has a second polarity opposite to the first polarity.
[0030] The first transistor M1 is coupled between the first power supply voltage ELVDD and the second power supply voltage ELVSS, and the control terminal of the first transistor M1 is coupled to the first node A. The second transistor M2 is coupled between the operating voltage VDD and the first node A, and the control terminal of the second transistor M2 is controlled by the first control signal S[N]. The third transistor M3 is coupled between the first node A and the second reference voltage V2, and the control terminal of the third transistor M3 is controlled by the first reference voltage V1. The fourth transistor M4 is coupled between the data voltage VDAT and the second node B, and the control terminal of the fourth transistor M4 is controlled by the first control signal S[N]. The fifth transistor M5 is coupled between the second node B and the second reference voltage V2. The control terminal of the fifth transistor M5 is controlled by the second control signal EM[N]. The first capacitor C1 is coupled between the first node A and the second node B.
[0031] In this embodiment, the main leakage current balancing architecture of the micro-LED pixel circuit 4 is composed of the second transistor M2 and the third transistor M3, and the main voltage regulation architecture of the micro-LED pixel circuit 4 is composed of the fifth transistor M5, but this is not a limitation. The first power supply voltage ELVDD is greater than the second power supply voltage ELVSS; the operating voltage VDD is greater than the second reference voltage V2 and greater than the first reference voltage V1. In fact, the first power supply voltage ELVDD can be equal to the operating voltage VDD and the first reference voltage V1 can be equal to the second power supply voltage ELVSS. In this case, the first power supply voltage ELVDD is greater than the second reference voltage V2 and greater than the second power supply voltage ELVSS, but this is not a limitation.
[0032] It should be noted that the first transistor M1, the second transistor M2, the fourth transistor M4, and the fifth transistor M5 in Figure 4 have a first polarity of P-type, and the third transistor M3 has a second polarity of N-type. That is, the first transistor M1, the second transistor M2, the fourth transistor M4, and the fifth transistor M5 in Figure 4 are P-type transistors, and the third transistor M3 is an N-type transistor. At this time, the micro-light-emitting diode (LED) is disposed between the first transistor M1 and the second power supply voltage ELVSS.
[0033] Conversely, if the first transistor M1, the second transistor M2, the fourth transistor M4, and the fifth transistor M5 have an N-type first polarity and the third transistor M3 has a P-type second polarity, that is, the first transistor M1, the second transistor M2, the fourth transistor M4, and the fifth transistor M5 are N-type transistors and the third transistor M3 is a P-type transistor, then the micro-light-emitting diode (LED) needs to be changed to be positioned between the first power supply voltage ELVDD and the first transistor M1.
[0034] In another embodiment, as shown in FIG5, the micro-light-emitting diode pixel circuit 5 with leakage current balancing architecture in this embodiment has a 5T2C (five transistors and two capacitors) architecture. The micro-light-emitting diode pixel circuit 5 includes a first transistor M1, a second transistor M2, a third transistor M3, a fourth transistor M4, a fifth transistor M5, a first capacitor C1, and a second capacitor C2. Among them, the first transistor M1, the second transistor M2, the fourth transistor M4, and the fifth transistor M5 have a first polarity, and the third transistor M3 has a second polarity opposite to the first polarity.
[0035] The first transistor M1 is coupled between the first power supply voltage ELVDD and the second power supply voltage ELVSS, and the control terminal of the first transistor M1 is coupled to the first node A. The second transistor M2 is coupled between the operating voltage VDD and the first node A, and the control terminal of the second transistor M2 is controlled by the first control signal S[N]. The third transistor M3 is coupled between the first node A and the second reference voltage V2, and the control terminal of the third transistor M3 is controlled by the first reference voltage V1. The fourth transistor M4 is coupled between the data voltage VDAT and the second node B, and the control terminal of the fourth transistor M4 is controlled by the first control signal S[N]. The fifth transistor M5 is coupled between the second node B and the second reference voltage V2. The control terminal of the fifth transistor M5 is controlled by the second control signal EM[N]. The first capacitor C1 is coupled between the first node A and the second node B. The second capacitor C2 is coupled between the operating voltage VDD and the first node A.
[0036] In this embodiment, the main leakage current balancing architecture of the micro-LED pixel circuit 5 is composed of the second transistor M2 and the third transistor M3, and the main voltage regulation architecture of the micro-LED pixel circuit 5 is composed of the fifth transistor M5, but this is not a limitation. The first power supply voltage ELVDD is greater than the second power supply voltage ELVSS; the operating voltage VDD is greater than the second reference voltage V2 and greater than the first reference voltage V1. In fact, the first power supply voltage ELVDD can be equal to the operating voltage VDD and the first reference voltage V1 can be equal to the second power supply voltage ELVSS. In this case, the first power supply voltage ELVDD is greater than the second reference voltage V2 and greater than the second power supply voltage ELVSS, but this is not a limitation.
[0037] It should be noted that the first transistor M1, the second transistor M2, the fourth transistor M4, and the fifth transistor M5 in Figure 5 have a first polarity of P-type, and the third transistor M3 has a second polarity of N-type. That is, the first transistor M1, the second transistor M2, the fourth transistor M4, and the fifth transistor M5 in Figure 5 are P-type transistors, and the third transistor M3 is an N-type transistor. At this time, the micro-light-emitting diode (LED) is disposed between the first transistor M1 and the second power supply voltage ELVSS.
[0038] Conversely, if the first transistor M1, the second transistor M2, the fourth transistor M4, and the fifth transistor M5 have an N-type first polarity and the third transistor M3 has a P-type second polarity, that is, the first transistor M1, the second transistor M2, the fourth transistor M4, and the fifth transistor M5 are N-type transistors and the third transistor M3 is a P-type transistor, then the micro-light-emitting diode (LED) needs to be changed to be positioned between the first power supply voltage ELVDD and the first transistor M1.
[0039] Next, we will take the micro-light-emitting diode pixel circuit 5 with a 5T2C (five transistors and two capacitors) architecture as an example to explain in detail the operation of the micro-light-emitting diode pixel circuit 5 in the data writing stage and the light-emitting stage.
[0040] Please refer to Figures 6A and 6B. Figure 6A shows a schematic diagram of the micro-LED pixel circuit 5 operating in the data writing stage. Figure 6B shows a timing diagram of the first control signal S[N] and the second control signal EM[N] when the micro-LED pixel circuit 5 is operating in the data writing stage.
[0041] As shown in Figures 6A and 6B, during the period from time t1 to t2, the micro-light-emitting diode pixel circuit 5 operates in the data writing stage. The first control signal S[N] is the second quasi-VGL and the second control signal EM[N] is the first quasi-VGH, causing the second transistor M2 and the fourth transistor M4 to be turned on and the first transistor M1, the third transistor M3 and the fifth transistor M5 to be turned off. The turned-on second transistor M2 and the fourth transistor M4 will have current flowing through to the first node A and the second node B respectively, causing the first node A to have an operating voltage VDD and the second node B to have a data voltage VDAT, wherein the first quasi-VGH is higher than the second quasi-VGL.
[0042] Please refer to Figures 7A and 7B. Figure 7A shows a schematic diagram of the micro-light-emitting diode pixel circuit 5 operating in the light-emitting stage. Figure 7B shows a timing diagram of the first control signal S[N] and the second control signal EM[N] when the micro-light-emitting diode pixel circuit 5 is operating in the light-emitting stage.
[0043] As shown in Figures 7A and 7B, before time t1 and after time t2, the micro-LED pixel circuit 5 operates in the light-emitting stage. The first control signal S[N] is the first quasi-VGH and the second control signal EM[N] is the second quasi-VGL, causing the first transistor M1 and the fifth transistor M5 to be turned on and the second transistor M2, the third transistor M3 and the fourth transistor M4 to be turned off. The second node B will be maintained at the second reference voltage V2 and the first node A will have a coupling voltage VCP related to the operating voltage VDD and the data voltage VDAT. The first transistor M1, which is turned on, will have a drive current ILED passing through it, where the first quasi-VGH is higher than the second quasi-VGL. The coupling voltage VCP of the first node A will be equal to the operating voltage VDD - {[first capacitor C1 / (first capacitor C1 + second capacitor C2)] × (data voltage VDAT - second reference voltage V2)}.
[0044] It should be noted that when the micro-light-emitting diode pixel circuit 5 of the present invention operates in the light-emitting stage, leakage current balance is achieved at the first node A. As shown in FIG8, in the light-emitting stage, the operating voltage VDD is greater than the coupling voltage VCP of the first node A and greater than the second reference voltage V2, so that when the second transistor M2 is turned off, the first leakage current IDS_M2 and the second leakage current IDB_M2 are still generated to charge the first node A, and when the third transistor M3 is turned off, the third leakage current IDS_M3 and the fourth leakage current IDB_M3 are still generated to discharge the first node A. The sum of the first leakage current IDS_M2 and the second leakage current IDB_M2 that charge the first node A is equal to the sum of the third leakage current IDS_M3 and the fourth leakage current IDB_M3 that discharge the first node A, thereby achieving leakage current balance at the first node A.
[0045] Compared with the prior art, the micro-light-emitting diode pixel circuit with leakage current balance architecture proposed in this invention can be applied to ultra-high resolution display panels using a 4T1C (four transistors and one capacitor) architecture, a 4T2C (four transistors and two capacitors) architecture, a 5T1C (five transistors and one capacitor) architecture, or a 5T2C (five transistors and two capacitors) architecture. It can also use CMOS process design to adapt to extremely small pixel areas, thereby achieving leakage current balance and effectively solving the problem that the traditional micro-light-emitting diode pixel circuit using a 2T1C (two transistors and one capacitor) architecture is easily affected by transistor leakage current, resulting in uneven driving current. [Simplified Explanation of the Diagram]
[0046] Figure 1 shows a schematic diagram of a conventional micro-light-emitting diode pixel circuit.
[0047] Figures 2 to 5 respectively illustrate schematic diagrams of micro-light-emitting diode pixel circuits with leakage current balancing architecture in different embodiments of the present invention.
[0048] Figure 6A shows a schematic diagram of the micro-light-emitting diode pixel circuit operating in the data writing stage.
[0049] Figure 6B shows the timing diagram of the first control signal and the second control signal when the micro-light-emitting diode pixel circuit is operating in the data writing stage.
[0050] Figure 7A shows a schematic diagram of the micro-light-emitting diode pixel circuit operating in the light-emitting stage.
[0051] Figure 7B shows the timing diagram of the first control signal and the second control signal when the micro-light-emitting diode pixel circuit is operating in the light-emitting stage.
[0052] Figure 8 illustrates a schematic diagram of leakage current balance achieved at the first node when the micro-light-emitting diode pixel circuit is operating in the light-emitting stage.
Claims
1. A micro-light-emitting diode pixel circuit with a leakage current balancing architecture, comprising: A first transistor is coupled between a first power supply voltage and a second power supply voltage, and the control terminal of the first transistor is coupled to a first node, wherein the first power supply voltage is greater than the second power supply voltage; a second transistor is coupled between an operating voltage and the first node, and the control terminal of the second transistor is controlled by a first control signal; a third transistor is coupled between the first node and a second reference voltage, and the control terminal of the third transistor is controlled by a first reference voltage, wherein the operating voltage is greater than the second reference voltage and greater than the first reference voltage; a first capacitor is coupled between the first node and the second node; and a fourth transistor is coupled between a data voltage and the second node, and the control terminal of the fourth transistor is controlled by the first control signal; wherein the first transistor, the second transistor, and the fourth transistor have a first polarity and the third transistor has a second polarity opposite to the first polarity.
2. The micro-light-emitting diode pixel circuit as claimed in claim 1, wherein the first power supply voltage is equal to the operating voltage and the first reference voltage is equal to the second power supply voltage.
3. The micro-light-emitting diode pixel circuit as described in claim 1 further includes: A second capacitor is coupled between the operating voltage and the first node.
4. The micro-light-emitting diode pixel circuit as described in claim 1 further includes: A fifth transistor is coupled between the second node and the second reference voltage, and the control terminal of the fifth transistor is controlled by a second control signal.
5. The micro-light-emitting diode pixel circuit as described in claim 1 further includes: A second capacitor is coupled between the operating voltage and the first node; And a fifth transistor, coupled between the second node and the second reference voltage, wherein the control terminal of the fifth transistor is controlled by a second control signal.
6. The micro-light-emitting diode pixel circuit as claimed in claim 5, wherein during a data writing phase, the first control signal is a second level and the second control signal is a first level, causing the second transistor and the fourth transistor to be turned on and the first transistor, the third transistor and the fifth transistor to be turned off, the first node has the operating voltage and the second node has the data voltage, and the first level is higher than the second level.
7. The micro-light-emitting diode pixel circuit as claimed in claim 5, wherein during a light-emitting phase, the first control signal is a first level and the second control signal is a second level, causing the first transistor and the fifth transistor to be turned on and the second transistor, the third transistor and the fourth transistor to be turned off, the second node is maintained at the second reference voltage and the first node has a coupling voltage related to the operating voltage and the data voltage, a drive current flows through the first transistor, and the first level is higher than the second level.
8. The micro-light-emitting diode pixel circuit as claimed in claim 7, wherein during the light-emitting phase, the operating voltage is greater than the coupling voltage of the first node is greater than the second reference voltage, causing a first leakage current and a second leakage current to charge the first node when the second transistor is turned off, and a third leakage current and a fourth leakage current to discharge the first node when the third transistor is turned off, wherein the sum of the first leakage current and the second leakage current is equal to the sum of the third leakage current and the fourth leakage current, so as to achieve leakage balance at the first node.
9. The micro-light-emitting diode pixel circuit as claimed in claim 1, wherein when the first polarity is P-type and the second polarity is N-type, a micro-light-emitting diode system is disposed between the first transistor and the second power supply voltage.
10. The micro-light-emitting diode pixel circuit as claimed in claim 1, wherein when the first polarity is N-type and the second polarity is P-type, a micro-light-emitting diode system is disposed between the first power supply voltage and the first transistor.