Output signal control circuit for selection of signal outputting and system circuit thereof

Abstract

An output signal control circuit, includes an input transistor, a first output transistor and a second output transistor. The input transistor is coupled to a first signal generator, so as to receive a first signal generated by the first signal generator. The first output transistor is coupled to a second signal generator, so as to receive a second signal generated by the second signal generator, and is coupled to an output end. The output end generates an output signal. The second output transistor is coupled to the first output transistor and the output end, and receives a first constant voltage. The input transistor, the first output transistor and the second output transistor are in an on-state or an off-state in response to the first signal, so as to selectively provide the second signal or the first constant voltage as the output signal.

Description

[Technical Field]

[0001] This disclosure relates to a control circuit, and more particularly to an output signal control circuit and system circuit for selecting signal output. [Previous Technology]

[0002] With the advancement of semiconductor manufacturing technology and the maturity of light-emitting diode (LED) devices, advanced LED devices, such as organic light-emitting diodes (OLEDs) and micro light-emitting diodes (μLEDs), have been widely used in flat panel displays. In displays that incorporate microLEDs, the light-emitting duty period of the light-emitting transistors in the display's driving circuit can be increased, thereby maintaining the microLED at a high-efficiency point.

[0003] However, during the blanking time sensing of the driving circuit, the timing of the light emission driving of each array of the display's corresponding light emission gate circuit array may be inconsistent; therefore, inconsistent light emission driving will affect the sensing results of the display's scanning gate circuit array.

[0004] In view of the above issues, it is necessary to improve the driving circuit of the display in order to control the output of the light emission signal of the light emission gate circuit array, in order to reduce the impact of the light emission driving of the light emission gate circuit array on the sensing result of the scanning gate circuit array. [Summary of the Invention]

[0005] According to one aspect of this disclosure, an output signal control circuit is provided, including an input transistor, a first output transistor, and a second output transistor. The input transistor is coupled to a first signal generator to receive a first signal generated by the first signal generator. The first output transistor is coupled to a second signal generator to receive a second signal generated by the second signal generator, and is coupled to an output terminal, which generates an output signal. The second output transistor is coupled to the first output transistor and the output terminal, and receives a first constant voltage. The input transistor, the first output transistor, and the second output transistor are in an on or off state in response to the first signal, so as to selectively provide the second signal or the first constant voltage as an output signal.

[0006] According to another aspect of this disclosure, a system circuit is provided, including a control circuit, an active circuit array, and a plurality of drive circuits. The control circuit generates a control signal. The active circuit array includes a plurality of display arrays. Each of the drive circuits includes a light-emitting gate circuit array and an output signal control circuit. The light-emitting gate circuit array generates a light-emitting signal. The output signal control circuit receives the control signal and the light-emitting signal, and generates an output signal. The output signal generated by the output signal control circuit is correspondingly provided to the display arrays.

[0007] Other aspects and advantages of this disclosure will become apparent from the following figures, detailed description and claims.

Implementation Method

[0008] The technical terms used in this specification refer to those commonly used in the field of technical expertise. Where this specification provides explanations or definitions for certain terms, the interpretation of those terms shall be based on the explanations or definitions provided in this specification. Each embodiment disclosed herein has one or more technical features. Where feasible, those skilled in the art may selectively implement some or all of the technical features in any embodiment, or selectively combine some or all of the technical features in these embodiments.

[0009] Figure 1 is a circuit diagram of a light-emitting signal (EM) control circuit 1000 according to an embodiment of the present disclosure. As shown in Figure 1, the light-emitting signal control circuit 1000 includes a first transistor T1a, a second transistor T2a, a third transistor T3a, and a fourth transistor T4a. The first transistor T1a is, for example, an N-type metal-oxide-semiconductor (NMOS), and the second transistor T2a, the third transistor T3a, and the fourth transistor T4a are, for example, P-type metal-oxide-semiconductor (PMOS). The second transistor T2a can also be referred to as the "input transistor," the third transistor T3a as the "first output transistor," and the fourth transistor T4a as the "second output transistor."

[0010] A first transistor T1a and a second transistor T2a constitute an inverter 100. The inverter 100 has a complementary metal-oxide-semiconductor (CMOS) architecture. More specifically, the gate g1a of the first transistor T1a is coupled to the gate g2a of the second transistor T2a; the coupling point of the gate g1a of the first transistor T1a and the gate g2a of the second transistor T2a is the input terminal 101 of the inverter 100. On the other hand, the drain d1a of the first transistor T1a is coupled to the drain d2a of the second transistor T2a; the coupling point of the drain d1a of the first transistor T1a and the drain d2a of the second transistor T2a is the output terminal 102 of the inverter 100. Furthermore, the source s1a of the first transistor T1a is coupled to a voltage source (not shown in the figure) to receive a second constant voltage VGL. The second constant voltage VGL is a low-potential gate voltage, for example, -8V. The source s2a of the second transistor T2a is coupled to another voltage source (not shown in the figure) to receive a first constant voltage VGH. The first constant voltage VGH is a high-potential gate voltage, for example, 8V.

[0011] The coupling point between the gate g1a of the first transistor T1a and the gate g2a of the second transistor T2a (i.e., the input terminal 101 of the inverter 100) is the first input terminal 1001 of the light emission signal control circuit 1000. The first input terminal 1001 of the light emission signal control circuit 1000 is coupled to the scanning gate array (Scan GOA) 200, and the first input terminal 1001 receives the scan output signal CS1 generated by the scanning gate array 200.

[0012] The coupling point between the drain d1a of the first transistor T1a and the drain d2a of the second transistor T2a (i.e., the output terminal 102 of the inverter 100) is coupled to the gate g3a of the third transistor T3a. The source s3a of the third transistor T3a is the second input terminal 1002 of the light emission signal control circuit 1000. The second input terminal 1002 of the light emission signal control circuit 1000 is coupled to the light emission gate circuit array (EM GOA) 300, and the second input terminal 1002 receives the light emission signal EM generated by the light emission gate circuit array 300.

[0013] The drain d3a of the third transistor T3a is coupled to the drain d4a of the fourth transistor T4a. The gate g4a of the fourth transistor T4a is coupled to the gate g2a of the second transistor T2a. The source s4a of the fourth transistor T4a is the third input terminal 1003 of the light emission signal control circuit 1000. The third input terminal 1003 of the light emission signal control circuit 1000 is coupled to another voltage source (not shown in the figure), and the third input terminal 1003 receives a first constant voltage VGH.

[0014] The coupling point between the drain d3a of the third transistor T3a and the drain d4a of the fourth transistor T4a is the output terminal 1004 of the light emission signal control circuit 1000. The output terminal 1004 of the light emission signal control circuit 1000 provides the output signal EM1. The third transistor T3a and the fourth transistor T4a serve as buffer transistors for the voltage of the output gate line. The dimensions of the third transistor T3a and the fourth transistor T4a cannot affect the discharge current of the output gate line. Therefore, the third transistor T3a and the fourth transistor T4a have relatively large dimensions; for example, the width-to-length ratio of their transistor channels ranges from 72 / 3 to 180 / 3.

[0015] Figure 2 shows the waveforms of the light emission signal EM and the scan output signal CS1 received by the light emission signal control circuit 1000 in Figure 1, and the corresponding output signal EM1 generated by the light emission signal control circuit 1000. Please refer to Figures 1 and 2 simultaneously to illustrate the basic operation of the light emission signal control circuit 1000: The first input terminal 1001 of the light emission signal control circuit 1000 receives the scan output signal CS1 generated by the scan gate circuit array 200; the scan output signal CS1 is, for example, the scan signal SCAN or the sensing signal SEN generated by the scan gate circuit array 200. Furthermore, the second input terminal 1002 of the light emission signal control circuit 1000 receives the light emission signal EM generated by the light emission gate circuit array 300. In response to the scan output signal CS1 received at the first input terminal 1001 being either a first potential V1 or a second potential V2, the light emission signal control circuit 1000 selectively provides the light emission signal EM received at the second input terminal 1002 or the first constant voltage VGH received at the third input terminal 1003 as the output signal EM1. The first potential V1 of the scan output signal CS1 is, for example, 8V, and the second potential V2 is, for example, -8V.

[0016] In the example of Figure 2, during the period from time point t1 to time point t2 and during the period from time point t3 to time point t4, since the scan output signal CS1 is the first potential V1, the light emission signal control circuit 1000 provides the light emission signal EM received by the second input terminal 1002 as the output signal EM1. Therefore, the output signal EM1 is approximately equal to the light emission signal EM.

[0017] On the other hand, during the period from time point t2 to time point t3, since the scan output signal CS1 is the second potential V2, the light emission signal control circuit 1000 provides the first constant voltage VGH received by the third input terminal 1003 as the output signal EM1. Therefore, the output signal EM1 is approximately equal to the first constant voltage VGH.

[0018] Figures 3A and 3B are schematic diagrams of the operation of the light emission signal control circuit 1000 in Figure 1. Please refer to Figures 2 and 3A first. The period from time point t1 to time point t2 is the first stage of operation of the light emission signal control circuit 1000. In the first stage, the scanning gate circuit array 200 is in the off mode, and the scanning output signal CS1 generated by the scanning gate circuit array 200 is the first potential V1. The gates of the second transistor T2a and the fourth transistor T4a receive the scanning output signal CS1 at the first potential V1. Since both the second transistor T2a and the fourth transistor T4a are PMOS transistors, they are in the off state. On the other hand, the gate of the first transistor T1a receives the scanning output signal CS1 at the first potential V1. Since the first transistor T1a is an NMOS transistor, it is in the on state. The second constant voltage VGL is conducted to the gate of the third transistor T3a via the conducting first transistor T1a. Since the third transistor T3a is a PMOS transistor, it is in the conducting state in response to the second constant voltage VGL. The light-emitting signal EM generated by the light-emitting gate circuit array 300 is conducted to the output terminal 1004 of the light-emitting signal control circuit 1000 via the conducting third transistor T3a, becoming the output signal EM1. In other words, during the first stage (between time point t1 and time point t2), the scanning gate circuit array 200 is in the off mode, and the light-emitting signal control circuit 1000 provides the light-emitting signal EM generated by the light-emitting gate circuit array 300 as the output signal EM1.

[0019] Next, please refer to Figure 2 and Figure 3B. The period from time point t2 to time point t3 is the second stage of operation of the light emission signal control circuit 1000. In the second stage, the scanning gate circuit array 200 is in the on mode, and the scanning output signal CS1 generated by the scanning gate circuit array 200 is the second potential V2.

[0020] The first transistor T1a, which is an NMOS transistor, is in a cutoff state in response to the scan output signal CS1 at the second potential V2. The second transistor T2a and the fourth transistor T4a, which are PMOS transistors, are in a conducting state in response to the scan output signal CS1 at the second potential V2. The first constant voltage VGH is conducted to the gate of the third transistor T3a via the conducting second transistor T2a, and the third transistor T3a is in a cutoff state in response to the first constant voltage VGH. Therefore, the light emission signal EM generated by the light emission gate circuit array 300 cannot be conducted to the output terminal 1004 of the light emission signal control circuit 1000 via the third transistor T3a. Instead, the first constant voltage VGH is conducted to the output terminal 1004 of the light emission signal control circuit 1000 via the conducting fourth transistor T4a, becoming the output signal EM1. In other words, during the second phase (between time point t2 and time point t3), the scanning gate circuit array 200 is in the on mode, and the light emission signal control circuit 1000 provides the first constant voltage VGH as the output signal EM1.

[0021] Figure 4 is a schematic diagram of the light emission signal control circuit 1000 of Figure 1 applied to the system circuit 1100 of the display. The system circuit 1100 is, for example, a gate circuit array of one stage of the low-temperature poly-silicon oxide (LTPO) backplane of the display, including: a scanning gate circuit array 200, a light emission gate circuit array 300, and an active circuit array 400. The light emission signal control circuit 1000 is disposed in the system circuit 1100, and the light emission signal control circuit 1000 provides an output signal EM1 to the active circuit array 400.

[0022] When the scanning gate circuit array 200 is performing sensing, the light emission signal EM is prevented from affecting the normal operation of the active circuit array 400; therefore, during the sensing period of the scanning gate circuit array 200, the output signal EM1 generated by the light emission signal control circuit 1000 is approximately equal to the first constant voltage VGH and is provided to the active circuit array 400, which is equivalent to making the active circuit array 400 receive the off light emission signal EM.

[0023] Figure 5 is a circuit diagram of a light-emitting signal control circuit 2000 according to another embodiment of this disclosure. The light-emitting signal control circuit 2000 of this embodiment functions similarly to the light-emitting signal control circuit 1000 of Figure 1. The light-emitting signal control circuit 2000 receives a scan output signal CS1 generated by the scan gate circuit array 200 and a light-emitting signal EM generated by the light-emitting gate circuit array 300; in response to the first potential V1 or the second potential V2 of the scan output signal CS1, the light-emitting signal control circuit 2000 selectively provides the light-emitting signal EM or the first constant voltage VGH as the output signal EM1.

[0024] As shown in Figure 5, the light emission signal control circuit 2000 includes a first transistor T1b, a second transistor T2b, a third transistor T3b, a fourth transistor T4b, a fifth transistor T5b, and a sixth transistor T6b. Each of the first transistors T1b to the sixth transistor T6b is a PMOS transistor. The second transistor T2b can also be referred to as the "input transistor," the fifth transistor T5b as the "first output transistor," and the sixth transistor T6b as the "second output transistor." Furthermore, the third transistor T3b can also be referred to as the "first dielectric transistor," and the fourth transistor T4b as the "second dielectric transistor."

[0025] More specifically, the gate g1b and source s1b of the first transistor T1b and the source s3b of the third transistor T3b are coupled together to a voltage source (not shown in the figure) to receive a second constant voltage VGL. The drain d1b of the first transistor T1b is coupled to the gate g3b of the third transistor T3b and the drain d2b of the second transistor T2b.

[0026] The gate g2b of the second transistor T2b is the first input terminal 2001 of the light emission signal control circuit 2000 to receive the scan output signal CS1 generated by the scan gate circuit array 200. The gate g4b of the fourth transistor T4b and the gate g6b of the sixth transistor T6b are both coupled to the gate g2b of the second transistor T2b.

[0027] The source s2b of the second transistor T2b is coupled to the source s4b of the fourth transistor T4b and the source s6b of the sixth transistor T6b. The coupling point of the aforementioned source s2b, source s4b and source s6b is the third input terminal 2003 of the light emission signal control circuit 2000, which is coupled to another voltage source (not shown in the figure) to receive the first constant voltage VGH.

[0028] The drain d3b of the third transistor T3b is coupled to the gate g5b of the fifth transistor T5b and the drain d4b of the fourth transistor T4b. The source s5b of the fifth transistor T5b is the second input terminal 2002 of the light emission signal control circuit 2000, which is coupled to the light emission gate circuit array 300 to receive the light emission signal EM.

[0029] The drain d5b of the fifth transistor T5b is coupled to the drain d6b of the sixth transistor T6b to form the output terminal 2004 of the light emission signal control circuit 2000; the output terminal 2004 provides the output signal EM1. Similar to the third transistor T3a and the fourth transistor T4a of the light emission signal control circuit 1000 in Figure 1, the fifth transistor T5b and the sixth transistor T6b serve as buffer transistors for the voltage of the output gate line, and therefore the fifth transistor T5b and the sixth transistor T6b have larger dimensions. For example, the width-to-length ratio of the transistor channels of the fifth transistor T5b and the sixth transistor T6b ranges from 72 / 3 to 180 / 3.

[0030] Figures 6A and 6B are schematic diagrams of the operation of the light emission signal control circuit 2000 in Figure 5. Please refer to Figures 2 and 6A first. In the first stage from time point t1 to time point t2, the scanning gate circuit array 200 is in the off mode, and the scanning output signal CS1 generated by the scanning gate circuit array 200 is the first potential V1. The second transistor T2b, the fourth transistor T4b, and the sixth transistor T6b are in the off state in response to the scanning output signal CS1 at the first potential V1. Therefore, the first constant voltage VGH cannot be conducted to the output terminal 2004 of the light emission signal control circuit 2000 via the sixth transistor T6b.

[0031] On the other hand, the first transistor T1b is in a conducting state in response to the second constant voltage VGL. The second constant voltage VGL is conducted to the gate of the third transistor T3b via the conducting first transistor T1b, thus the third transistor T3b is in a conducting state. Similarly, the second constant voltage VGL is conducted to the gate of the fifth transistor T5b via the conducting third transistor T3b, thus the fifth transistor T5b is in a conducting state. The light emission signal EM generated by the light emission gate circuit array 300 is conducted to the output terminal 2004 of the light emission signal control circuit 2000 via the conducting fifth transistor T5b, becoming the output signal EM1.

[0032] In other words, during the first stage from time point t1 to time point t2, the scanning gate circuit array 200 is in the off mode, and the scanning output signal CS1 generated by it is the first potential V1. The light emission signal control circuit 2000 provides the light emission signal EM generated by the light emission gate circuit array 300 as the output signal EM1.

[0033] Next, please refer to Figures 2 and 6B. In the second stage from time point t2 to time point t3, the scanning gate circuit array 200 is in the on mode, and the scanning output signal CS1 generated by the scanning gate circuit array 200 is the second potential V2. The second transistor T2b, the fourth transistor T4b, and the sixth transistor T6b are in the conducting state in response to the scanning output signal CS1 at the second potential V2. Therefore, the first constant voltage VGH can be conducted to the output terminal 2004 of the light emission signal control circuit 2000 through the conducting sixth transistor T6b, and become the output signal EM1.

[0034] On the other hand, the first constant voltage VGH is conducted to the gate of the third transistor T3b via the conducting second transistor T2b, thus the third transistor T3b is in a cutoff state. Furthermore, the second constant voltage VGL is conducted to the gate of the third transistor T3b via the conducting first transistor T1b, generating a voltage divider of the second constant voltage VGL at the gate of the third transistor T3b. The cutoff third transistor T3b can prevent the voltage divider of the second constant voltage VGL from being conducted to the gate of the fifth transistor T5b, thus ensuring that the fifth transistor T5b is in a cutoff state. Accordingly, the light emission signal EM generated by the light emission gate circuit array 300 cannot be provided to the output terminal 2004 of the light emission signal control circuit 2000 via the fifth transistor T5b.

[0035] In other words, during the second stage from time point t2 to time point t2, the scanning gate circuit array 200 is in the on mode, and the scanning output signal CS1 generated by it is the second potential V2. The light emission signal control circuit 2000 provides the first constant voltage VGH as the output signal EM1.

[0036] Please refer to Figure 4 again. The light emission signal control circuit 2000 can also be applied to the system circuit 1100 of the display, especially to the low-temperature polysilicon (LTPS) backplane. In other words, the light emission signal control circuit 1000 in Figure 1 is applied to the LTPO backplane of the display, while the light emission signal control circuit 2000 in Figure 5 is applied to the LTPS backplane of the display.

[0037] Figure 7 shows the waveforms of the scan signal SCAN, the sensing signal SEN, the light emission signal EM, and the output signal EM1 when the system circuit 1100 of the display in Figure 4 is simulated. In Figure 7, the scan signal SCAN and / or the sensing signal SEN generated by the scan gate circuit array 200 can represent the scan output signal CS1.

[0038] During the period from time point t01 to time point t02, the scanning gate circuit array 200 is in the off mode, and the scanning signal SCAN and sensing signal SEN generated by the scanning gate circuit array 200 are at the first potential V1. The light emission signal control circuit 1000 or (light emission signal control circuit 2000) provides the light emission signal EM generated by the light emission gate circuit array 300 as the output signal EM1. In other words, when the scanning gate circuit array 200 is in the off mode, the output signal EM1 is approximately equal to the light emission signal EM.

[0039] Subsequently, during the period from time point t02 to time point t03, the scanning gate circuit array 200 switches to the on mode, and the scanning signal SCAN and sensing signal SEN generated by the scanning gate circuit array 200 are converted to the second potential V2. The light emission signal control circuit 1000 or (light emission signal control circuit 2000) provides the first constant voltage VGH as the output signal EM1 to prevent the light emission signal EM from affecting the normal operation of the active circuit array 400. In other words, when the scanning gate circuit array 200 is in the on mode, the output signal EM1 is approximately equal to the first constant voltage VGH.

[0040] Subsequently, during the period from time point t03 to time point t04, the scan gate circuit array 200 switches to the off mode again, and the scan signal SCAN and sensing signal SEN generated by the scan gate circuit array 200 are converted to the first potential V1 again. The light emission signal control circuit 1000 or (light emission signal control circuit 2000) provides the light emission signal EM generated by the light emission gate circuit array 300 as the output signal EM1.

[0041] Figure 8 is a schematic diagram of the light emission signal control circuit 1000 of Figure 1 applied to a panel 3000 having an under-display camera (UDC). The panel 3000 is equipped with an under-display camera; in the example of Figure 8, the lens 3010 of the under-display camera is positioned inside the display area 350 of the panel 3000. Because the lens 3010 is positioned inside the display area 350, when the under-display camera is performing light collection operation, the display area 350 of the panel 3000 must remain a black screen.

[0042] The light emission signal control circuit 1000 in Figure 1 can be applied to the display area 350 of the control panel 3000. When the camera under the monitor is performing light collection operation, the light emission signal control circuit 1000 provides the active circuit array inside the display area 350 of the panel 3000 with a first constant voltage VGH as the output signal EM1, causing the display area 350 of the panel 3000 to display a black screen.

[0043] Figure 9 is a schematic diagram of the system circuit 1200 inside the panel 3000 in Figure 8. The system circuit 1200 includes a control circuit 500, an active circuit array 400, and multiple levels of drive circuits 601, 602, 603, etc. Among them, drive circuit 601 includes a light-emitting gate circuit array 301 and a light-emitting signal control circuit 1000-1; drive circuit 602 includes a light-emitting gate circuit array 302 and a light-emitting signal control circuit 1000-2; drive circuit 603 includes a light-emitting gate circuit array 303 and a light-emitting signal control circuit 1000-3, and so on. The circuit architecture of the light-emitting signal control circuits 1000-1, 1000-2, and 1000-3 in Figure 9 is the same as that of the light-emitting signal control circuit 1000 in Figure 1. The light-emitting signal control circuits 1000-1, 1000-2, and 1000-3 receive the light-emitting signals EM generated by the light-emitting gate circuit arrays 301, 302, and 303 respectively. Furthermore, the light-emitting signal control circuits 1000-1, 1000-2, and 1000-3 provide output signals EM[N], EM[N+1], and EM[N+2] to the active circuit array 400. The active circuit array 400 includes multiple levels of display arrays 40[N], 40[N+1], and 40[N+2], etc. The display arrays 40[N], 40[N+1], and 40[N+2] receive the output signals EM[N], EM[N+1], and EM[N+2] provided by the light-emitting signal control circuits 1000-1, 1000-2, and 1000-3.

[0044] The light emission signal control circuits 1000-1, 1000-2, and 1000-3 are all controlled by the control circuit 500. More specifically, the control circuit 500 provides a single control signal CS2 to the light emission signal control circuits 1000-1, 1000-2, and 1000-3. In response to the control signal CS2, the light emission signal control circuits 1000-1, 1000-2, and 1000-3 selectively provide the light emission signal EM as the corresponding output signals EM[N], EM[N+1], and EM[N+2], or use a first constant voltage VGH as the output signals EM[N], EM[N+1], and EM[N+2].

[0045] Figure 10 shows the waveforms of the light emission signal EM and control signal CS2 received by the light emission signal control circuits 1000-1, 1000-2 and 1000-3 in Figure 9, and the corresponding output signals EM[N], EM[N+1] and EM[N+2]. Please also refer to Figures 8, 9 and 10. In operation, when the camera under the display in Figure 8 performs light receiving operation between time point t11 ​​and time point t12, the control signal CS2 generated by the control circuit 500 of the system circuit 1200 in Figure 9 is converted to the second potential V2. In response to the control signal CS2 at the second potential V2, during the period between time point t11 ​​and time point t12, the light emission signal control circuits 1000-1, 1000-2 and 1000-3 use the first constant voltage VGH as the output signals EM[N], EM[N+1] and EM[N+2].

[0046] During the period from time point t11 ​​to time point t12, the display arrays 40[N], 40[N+1], and 40[N+2] of the active circuit array 400 in Figure 9 each receive output signals EM[N], EM[N+1], and EM[N+2] that are approximately equal to the first constant voltage VGH. Therefore, the display arrays 40[N], 40[N+1], and 40[N+2] all display black, causing the entire panel 3000 to display a completely black screen during the period from time point t11 ​​to time point t12. With the above implementation, all output signals EM[N], EM[N+1], and EM[N+2] can be controlled by a single control signal CS2 to achieve the requirement of black screen switching.

[0047] Figure 11A is a circuit diagram of an output signal control circuit 1000a according to an embodiment of the present disclosure. The circuit architecture of the output signal control circuit 1000a is the same as that of the light emission signal control circuit 1000 in Figure 1, and the output signal control circuit 1000a is also composed of a first transistor T1a, a second transistor T2a, a third transistor T3a and a fourth transistor T4a.

[0048] The output signal control circuit 1000a operates in conjunction with the first signal generator 210 and the second signal generator 310; the output signal control circuit 1000a receives the first signal SA generated by the first signal generator 210 and the second signal SB generated by the second signal generator 310.

[0049] Functionally, the output signal control circuit 1000a determines whether to output the second signal SB based on the first signal SA. More specifically, in operation, the output signal control circuit 1000a selectively provides the second signal SB as the output control signal SO or provides the first constant voltage VGH as the output control signal SO based on the first signal SA.

[0050] Figure 11B is a circuit diagram of an output signal control circuit 2000a according to another embodiment of this disclosure. The circuit architecture of the output signal control circuit 2000a is the same as that of the light emission signal control circuit 2000 in Figure 5, and the output signal control circuit 2000a is also composed of a first transistor T1b, a second transistor T2b, a third transistor T3b, a fourth transistor T4b, a fifth transistor T5b, and a sixth transistor T6b.

[0051] The output signal control circuit 2000a functions the same as the output signal control circuit 1000a in Figure 11A. The output signal control circuit 2000a determines whether to output the second signal SB based on the first signal SA. More specifically, the output signal control circuit 2000a selectively provides the second signal SB as the output control signal SO or provides the first constant voltage VGH as the output control signal SO based on the first signal SA.

[0052] The control circuit based on the same circuit architecture as the light emission signal control circuit 1000 in Figure 1 (or the light emission signal control circuit 2000 in Figure 4) can be applied not only to the output control of the light emission signal EM of the panel, but also to the output control of any other type of signal.

[0053] Although this disclosure has been described in detail above with reference to preferred embodiments and examples, it is understood that these examples are intended to illustrate rather than limit. It is anticipated that various modifications and combinations will be conceived by those skilled in the art, and such modifications and combinations fall within the spirit of this disclosure and the scope of the appended claims. [Simplified Explanation of the Diagram]

[0054] Figure 1 is a circuit diagram of an EM (Emitting Light) control circuit according to an embodiment of this disclosure. Figure 2 is a waveform diagram of the EM received by the EM control circuit in Figure 1, the scan output signal, and the output signal generated by the EM control circuit accordingly. Figures 3A and 3B are schematic diagrams of the operation of the EM control circuit in Figure 1. Figure 4 is a schematic diagram of a system circuit of the EM control circuit in Figure 1 applied to a display. Figure 5 is a circuit diagram of an EM control circuit according to another embodiment of this disclosure. Figures 6A and 6B are schematic diagrams of the operation of the EM control circuit in Figure 5. Figure 7 is a waveform diagram of the scan signal, sensing signal, EM signal, and output signal when the system circuit of the display in Figure 4 is simulated. Figure 8 is a schematic diagram of the EM control circuit in Figure 1 applied to a panel having a camera under the display. Figure 9 is a schematic diagram of the system circuit inside the panel in Figure 8. Figure 10 is a waveform diagram of the light emission signal and control signal received by the light emission signal control circuit in Figure 9, and the corresponding output signal generated. Figure 11A is a circuit diagram of an output signal control circuit according to one embodiment of this disclosure. Figure 11B is a circuit diagram of an output signal control circuit according to another embodiment of this disclosure.

Claims

1. An output signal control circuit, comprising: An input transistor is coupled to a first signal generator to receive a first signal generated by the first signal generator; A first output transistor is coupled to a second signal generator to receive a second signal generated by the second signal generator, and is coupled to an output terminal that generates an output signal. And a second output transistor, coupled to the first output transistor and the output terminal, and receiving a first constant voltage, wherein the input transistor, the first output transistor and the second output transistor are in an on state or an off state in response to the first signal, so as to selectively provide the second signal or the first constant voltage as the output signal.

2. The output signal control circuit of claim 1, wherein a source of the first output transistor is coupled to the second signal generator to receive the second signal, and a drain of the first output transistor is coupled to the output terminal, wherein when the first output transistor is in the on state and the second output transistor is in the off state, the second signal is conducted to the output terminal through the first output transistor to provide the output signal.

3. The output signal control circuit of claim 1, wherein a source of the second output transistor receives the first constant voltage, and a drain of the second output transistor is coupled to the output terminal, wherein when the second output transistor is in the on state and the first output transistor is in the off state, the first constant voltage is conducted to the output terminal through the second output transistor to provide the output signal.

4. The output signal control circuit of claim 1, wherein a gate of the input transistor is coupled to the first signal generator to receive the first signal and is coupled to a gate of the second output transistor, and a source of the input transistor receives the first constant voltage.

5. The output signal control circuit of claim 4 further includes: A first transistor is coupled to the input transistor and receives a second constant voltage, wherein the second constant voltage is lower than the first constant voltage.

6. The output signal control circuit of claim 5, wherein the output signal is applied to a low-temperature poly-silicon oxide (LTPO) backplane or a low-temperature polysilicon (LTPS) backplane.

7. The output signal control circuit of claim 6, wherein when the output signal is applied to the low-temperature polycrystalline silicon oxide backplane, the first transistor and the input transistor form a complementary metal-oxide-semiconductor inverter.

8. The output signal control circuit of claim 6, wherein when the output signal is applied to the low-temperature polycrystalline silicon backplane, the output signal control circuit further includes: A first dielectric transistor is coupled to the first output transistor and receives the second constant voltage; And a second dielectric transistor, coupled to the first dielectric transistor, the input transistor and the second output transistor, and receiving the first constant voltage.

9. The output signal control circuit of claim 8, wherein when the first constant voltage is provided as the output signal, the first dielectric transistor and the first output transistor are in a cutoff state, and the input transistor, the second dielectric transistor and the second output transistor are in a conduction state.

10. The output signal control circuit of claim 9, wherein the first dielectric transistor in the off state blocks the voltage divider of the second constant voltage from being conducted to a gate of the first output transistor.

11. The output signal control circuit of claim 8, wherein when the second signal is provided as the output signal, the first transistor, the first dielectric transistor and the first output transistor are in an on state, and the input transistor, the second dielectric transistor and the second output transistor are in an off state.

12. The output signal control circuit of claim 1, wherein the first signal generator is a scanning gate circuit array, and the first signal is a scanning output signal.

13. The output signal control circuit of claim 12, wherein the scan output signal is a scan signal or a sensing signal generated by the scan gate circuit array.

14. The output signal control circuit of claim 12, wherein the second signal generator is a light-emitting gate circuit array, and the second signal is a light-emitting signal.

15. The output signal control circuit of claim 14, wherein when the scanning gate circuit array is in the on mode, the first constant voltage is provided as the output signal, and when the scanning gate circuit array is in the off mode, the light emission signal is provided as the output signal.

16. A system circuit, comprising: A control circuit generates a control signal; An active circuit array comprises a plurality of display arrays; and a plurality of driving circuits, each of which includes: an array of light-emitting gate circuits that generates a light-emitting signal; and the output signal control circuit, as claimed in claims 1 to 11, that receives the control signal and the light-emitting signal and generates an output signal, wherein the output signals generated by the output signal control circuits are correspondingly provided to the display arrays.

17. The system circuit of claim 16, wherein each of the output signal control circuits selectively provides the light emission signal or a first constant voltage as the output signal in response to the control signal.

18. The system circuit of claim 17, wherein the system circuit is disposed on a panel, the panel comprising: A camera under a display has a lens disposed inside a display area of ​​the panel; wherein, when the camera under the display is performing light collection operation, the output signal control circuit provides a first constant voltage as the output signal and transmits it to the display array, causing the display area to display a black screen.

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