Display device

Abstract

A display device includes a display panel and shift registers from the first level to the N thlevel. The i thlevel of the shift registers from the first level to the N thlevel includes a pull-up unit driving stage, a pull-up unit, and a discharge unit. The pull-up unit driving stage receives a first input signal and a second input signal, and outputs a pre-charge signal via a first node. The pull-up unit receives the pre-charge signal and plural clock signals, and outputs an i thlevel scanning signal via a second node. The discharge unit receives the pre-charge signal, a first discharge control signal and a second discharge control signal, and controls whether to pull-down and keep the i thlevel scanning signal to a reference voltage level. The first discharge control signal and the second discharge control signal switches between high and low voltage levels within every frame time of the display device and when every frame time of the display device ends.

Description

Technical Field

[0001] This disclosure relates to a display device, and more particularly to a display device comprising a shift register with automatic critical voltage offset correction and a narrow bezel display device having the shift register. Prior Technology

[0002] In recent years, panel manufacturers have been able to integrate gate circuits directly into the left and right edges of the array glass using row-on-array (GOA) architectures on array substrates, thereby reducing the number of display driver ICs (DDICs). However, as panel resolutions increase, the aforementioned architecture design is prone to encountering the problem of requiring excessive layout space, which hinders the achievement of narrow bezels.

[0003] Furthermore, with the continuous advancement of thin-film transistor (TFT) panel technology, including designs that can integrate driving circuits onto the panel, such as SOG (system on glass) technology, amorphous silicon (a-Si) processes can be used. However, due to limitations in process capability, the critical voltage (Vth) of the manufactured TFT elements gradually increases with the influence of applied bias stress. In conventional technologies, scan displacement circuits using amorphous silicon thin-film transistors as components exhibit instability in the critical voltage offset of several amorphous silicon thin-film transistor elements. As usage time increases, the degree of critical voltage offset severely affects the normal operation of the scan displacement circuit, and may even eventually cause the scan displacement circuit to fail. Summary of the Invention

[0004] The purpose of this invention is to provide a display device that achieves a narrow bezel effect in dual-gate and triple-gate driven panel technologies through the configuration of the circuit units in a shift register. By designing the pull-up units in the shift register as a three-layer capacitor structure, the tolerance to variations in the critical voltage (Vth) of the components in the shift register is increased. Furthermore, the discharge control signal received by the discharge unit in the shift register can be designed to switch between high and low potentials during each frame time of the display panel and at the end of each frame time, thereby controlling the offset of the critical voltage value of the components in the shift register and slowing down the aging rate of the critical voltage value. This effectively improves the reliability of the shift register.

[0005] To achieve the above objectives, the present invention provides a display device comprising a display panel and shift registers of levels 1 to N. The shift registers of levels 1 to N are used to drive the display panel, wherein one of the shift registers of level i includes a pull-up unit driver stage, a pull-up unit, and a discharge unit. The pull-up unit driver stage receives a first input signal and a second input signal, and outputs a pull-up drive signal from a first node based on the first and second input signals. The pull-up unit is coupled to the pull-up unit driver stage, receives the pull-up drive signal and a plurality of clock signals, and outputs an i-th level scan signal from a second node based on the pull-up drive signal and the clock signals. The discharge unit is coupled to the pull-up unit driver stage and the pull-up unit, receives the pull-up drive signal, a first discharge control signal, and a second discharge control signal, and controls whether to pull down and maintain the i-th level scan signal at a reference potential based on the pull-up drive signal, the first discharge control signal, and the second discharge control signal. The first discharge control signal and the second discharge control signal switch between high and low potentials during each frame time and at the end of each frame time on the display panel.

[0006] According to one embodiment of the present invention, within each frame time, the potential switching time of the second input signal is before the potential switching time of the first input signal.

[0007] According to another embodiment of the present invention, within each frame time, the potential switching time of the second input signal is substantially the same as the potential switching time of the first discharge control signal and the second discharge control signal.

[0008] According to another embodiment of the present invention, the high-low potential switching of the first discharge control signal and the second discharge control signal during each frame time of the display panel and at the end of each frame time includes the high-low potential switching of the first discharge control signal and the second discharge control signal at a first point in time during the blanking period of each frame time of the display panel.

[0009] According to another embodiment of the present invention, the high-low potential switching of the first discharge control signal and the second discharge control signal during each frame time of the display panel and at the end of each frame time includes the high-low potential switching of the first discharge control signal or the second discharge control signal at a second time point during the blank period of each frame time of the display panel.

[0010] According to another embodiment of the present invention, the signal period of the clock signal is 12 data write times, wherein the data write time is defined as the time during which each of the shift registers from level 1 to level N drives the corresponding pixel column in the display panel in each frame time.

[0011] According to another embodiment of the present invention, the potential switching time of the first discharge control signal is approximately 2.5 microseconds apart from the potential switching time of the second discharge control signal.

[0012] According to another embodiment of the present invention, the signal period of the first discharge control signal and the second discharge control signal is approximately 2 seconds.

[0013] According to another embodiment of the present invention, there is a data holding time between the first discharge control signal or the second discharge control signal and the i-th level scan signal, and the data holding time is 2.5 microseconds.

[0014] According to another embodiment of the present invention, the signal period of the clock signal is 16 data write times, wherein the data write time is defined as the time during which each of the shift registers from level 1 to level N drives the corresponding pixel column in the display panel in each frame time.

[0015] According to another embodiment of the present invention, the display device further includes a reset unit. The reset unit is coupled to a pull-up unit driver stage, a pull-up unit, and a discharge unit. The reset unit receives a reset signal and, based on the reset signal, resets the potentials of the first node and the second node after sequentially scanning a plurality of pixel rows of the display panel during each frame time of the display panel.

[0016] According to another embodiment of the present invention, the reset unit includes a first transistor and a second transistor. A reset signal is input to the control terminal of the first transistor, a first terminal of the first transistor is coupled to a reference potential, and a second terminal of the first transistor is coupled to a first node. The control terminal of the second transistor is coupled to the control terminal of the first transistor, a first terminal of the second transistor is coupled to the reference potential, and a second terminal of the second transistor is coupled to a second node.

[0017] According to another embodiment of the present invention, when the i-th stage shift register is scanning forward, in each frame time, the potential switching time point of the first discharge control signal and the potential switching time point of the second discharge control signal are after the potential switching time point of the second input signal, and are substantially the same as the potential switching time point of the reset signal.

[0018] According to another embodiment of the present invention, when the i-th stage shift register is in reverse scan, during each frame time, the potential switching time point of the first discharge control signal and the potential switching time point of the second discharge control signal are substantially the same as the potential switching time point of the first input signal, and substantially the same as the potential switching time point of the reset signal.

[0019] According to another embodiment of the present invention, within each frame time, the potential switching time of the first discharge control signal is substantially the same as the potential switching time of the reset signal.

[0020] According to another embodiment of the present invention, the pull-up unit driver stage includes a third transistor and a fourth transistor. The control terminal of the third transistor receives a first input signal, the first terminal of the third transistor receives a forward input signal, and the second terminal of the third transistor outputs a pull-up drive signal. The control terminal of the fourth transistor receives a second input signal, the first terminal of the fourth transistor receives a reverse input signal, and the second terminal of the fourth transistor is coupled to the second terminal of the third transistor.

[0021] According to another embodiment of the present invention, the pull-up unit includes a fifth transistor and a capacitor. The control terminal of the fifth transistor receives a pull-up drive signal, the first terminal of the fifth transistor receives a clock signal, and the second terminal of the fifth transistor outputs the i-th level scan signal. The first terminal of the capacitor is coupled to the control terminal of the fifth transistor, and the second terminal of the capacitor is coupled to the second terminal of the fifth transistor.

[0022] According to another embodiment of the present invention, the capacitor includes a first metal layer, a second metal layer, a lower electrode layer, and an upper electrode layer. The second metal layer is located on the first metal layer, wherein a first sub-capacitor is formed between the first metal layer and the second metal layer. The lower electrode layer is located on the first metal layer, wherein a second sub-capacitor is formed between the second metal layer and the lower electrode layer. The upper electrode layer is located on the lower electrode layer, wherein a third sub-capacitor is located between the lower electrode layer and the upper electrode layer.

[0023] According to another embodiment of the present invention, the discharge unit includes a sixth transistor, a seventh transistor, an eighth transistor, a ninth transistor, and a tenth transistor. A first discharge control signal is input to the control terminal and its first terminal of the sixth transistor. A second discharge control signal is input to the control terminal of the seventh transistor; the first terminal of the seventh transistor is coupled to a reference potential, and the second terminal of the seventh transistor is coupled to the second terminal of the sixth transistor. The control terminal of the eighth transistor is coupled to a third node, and the first terminal of the eighth transistor is coupled to a reference potential. The control terminal of the ninth transistor is coupled to a third node, and the first terminal of the ninth transistor is coupled to a reference potential. The first terminal of the tenth transistor is coupled to a third node, and the second terminal of the tenth transistor is coupled to a reference potential.

[0024] According to another embodiment of the present invention, the display panel has a dual-gate pixel array structure or a triple-gate pixel array structure. Simple Explanation of the Diagram

[0025] To gain a more complete understanding of the embodiments and their advantages, the following description, taken in conjunction with the accompanying drawings, is provided, wherein: Figure 1 is a schematic diagram of a display device according to some embodiments of the present invention; Figure 2A shows an example of the driving method for the display panel in Figure 1; Figure 2B shows another example of the driving method for the display panel in Figure 1; Figure 3A is an example of the equivalent circuit diagram of the i-th stage shift register in Figure 1; Figure 3B is another example of the equivalent circuit diagram of the i-th stage shift register in Figure 1; Figure 4A is a cross-sectional view of the panel structure in the display panel of Figure 1; Figures 4B to 4D are top-view diagrams of Figure 4A at different stages; Figure 5 is a schematic diagram of the capacitor architecture in Figure 4A; Figures 6A and 6B are examples of forward timing diagrams for the shift register in Figure 1; Figures 6C and 6D are examples of reverse timing diagrams for the shift register in Figure 1; Figures 7A and 7B are another example of the forward timing diagram of the shift register in Figure 1; Figures 7C and 7D are another example of the reverse timing diagram of the shift register in Figure 1; and Figure 8 is a voltage-time diagram of the discharge control signals of the first to Nth stage shift registers in the scan drive circuit of Figure 1. Implementation

[0026] The embodiments disclosed herein are discussed in detail below. However, it will be understood that the embodiments provide many applicable concepts that can be implemented in a wide variety of specific situations. The discussed and disclosed embodiments are for illustrative purposes only and are not intended to limit the scope of this disclosure.

[0027] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the scope of the claims. Unless otherwise limited, the singular forms of "a" or "the" may also be used to denote the plural forms.

[0028] It is understood that although terms such as "first," "second," etc., may be used in this article to describe various features, these terms should not limit these features. These terms are only used to distinguish one feature from another.

[0029] The use of spatial relativity is intended to describe the different orientations of a component during use or operation, and is not limited to the orientation shown in the diagram. Components may also be oriented in other ways (rotated 90 degrees or in other directions), and the spatial relativity described here can be interpreted in the same way.

[0030] For the sake of simplicity and clarity, element symbols and / or letters may be repeated in various embodiments herein, but this does not imply a causal relationship between the various embodiments and / or configurations discussed. Furthermore, for the sake of simplicity and clarity in illustrating technical features, elements in the drawings are not drawn to scale, and the dimensions of each element may be arbitrarily increased or decreased.

[0031] Please refer to Figure 1, which is a schematic diagram of a display device 100 according to some embodiments of the present invention. The display device 100 may include a display panel 200 and a scanning drive circuit 300. The display panel 200 may be various types of liquid crystal display panels, such as twisted nematic (TN), in-plane switching (IPS), fringe-field switching (FFS), or vertical alignment (VA), or an organic light-emitting diode (OLED) display panel. In addition, the scanning drive circuit 300 of the present invention may also be used as a driving circuit for a total reflection display panel, a transflective semi-transparent display panel, or a micro-transflective display panel. The scanning drive circuit 300 includes shift registers 300(1) to 300(N) of stages 1 to N, which are electrically connected to the display panel 200 and used to drive the display panel 200, wherein N is a positive integer greater than or equal to 5. The shift registers 300(1) to 300(N) from level 1 to level N can be array substrate row drive (GOA) circuit structures.

[0032] Please refer to Figure 2A, which is an example of the driving method of the display panel 200 of Figure 1 according to some embodiments of the present invention. The display panel 200 may have a dual-gate pixel array structure. Specifically, the display panel 200 may include a plurality of pixels 220, wherein the pixels 220 include sub-pixels SP1, SP2, and SP3, and the sub-pixels SP1, SP2, and SP3 may display different colors, such as red, green, and blue. The sub-pixels SP1, SP2, and SP3 may be designed to be arranged horizontally. Sub-pixels SP1 and SP2 share data line D1, sub-pixels SP1 and SP3 share data line D2, sub-pixels SP2 and SP3 share data line D3, and the sub-pixels SP1, SP2, or SP3 in pixel column R1 may be electrically connected to gate line G1 or G2, respectively. The sub-pixels SP1, SP2, or SP3 in pixel column R2 may be electrically connected to gate line G3 or G4, respectively. This allows each pixel 220 to be electrically connected to two gate lines. Compared to conventional driving methods (such as single-gate pixel array structures), the number of data lines in the display panel 200 is halved, and the number of gate lines is doubled, enabling the driving speed of the display panel 200 to be increased by up to two times.

[0033] Please refer to Figure 2B, which is another example of the driving method of the display panel 200 of Figure 1 according to some embodiments of the present invention. The display panel 200 may have a three-gate pixel array structure. In detail, the display panel 200 may include a plurality of pixels 220, wherein the pixels 220 include sub-pixels SP1, SP2 and SP3, and the sub-pixels SP1, SP2 and SP3 may display different colors, such as red, green and blue. The sub-pixels SP1, SP2 and SP3 may be designed to be arranged vertically. The sub-pixels SP1, SP2 and SP3 in each row share data line D4 or D5. For example, the sub-pixels SP1, SP2 and SP3 in pixel row L1 may share data line D4, and the sub-pixels SP1, SP2 and SP3 in pixel row L2 may also share data line D4. The sub-pixels SP1, SP2 and SP3 may be electrically connected to different gate lines. For example, sub-pixels SP1 in pixel arrays R3 and R6 can be electrically connected to gate lines G5 and G8. Sub-pixels SP2 in pixel arrays R4 and R7 can be electrically connected to gate lines G6 and G9. Sub-pixels SP3 in pixel arrays R5 and R8 can be electrically connected to gate lines G7 and G10. This allows each pixel 220 to be electrically connected to three gate lines. Compared to conventional driving methods (such as single-gate pixel array structures), the number of data lines in the display panel 200 is reduced to one-third, increasing the driving speed of the display panel 200 by up to three times.

[0034] Figure 3A is an example of the equivalent circuit diagram of the i-th stage shift register 300(i) in Figure 1, where i is a positive integer from 1 to N. The i-th stage shift register 300(i) includes a reset unit 310, a pull-up unit driver stage 320, a pull-up unit 330, and a discharge unit 340. One end of the reset unit 310, the pull-up unit driver stage 320, the pull-up unit 330, and the discharge unit 340 is coupled to node N1 (which corresponds to the pull-up drive signal PC(i)), and the other end of the reset unit 310, the pull-up unit 330, and the discharge unit 340 is coupled to node N2 (which corresponds to the i-th stage scan signal OUT(i)).

[0035] Reset unit 310 is coupled to pull-up unit driver stage 320, pull-up unit 330, and discharge unit 340. Reset unit 310 receives a reset signal RST and, according to the reset signal RST, resets the potentials of nodes N1 and N2 after sequentially scanning multiple pixel rows of the display panel 200 at each frame time FR1 or FR2 (refer to Figures 6A to 7D). Reset unit 310 includes transistors T1 and T2. The control terminal of transistor T1 receives the reset signal RST, the first terminal of transistor T1 is coupled to a reference potential REF, and the second terminal of transistor T1 is coupled to node N1. The control terminal of transistor T2 is coupled to the control terminal of transistor T1, the first terminal of transistor T2 is coupled to the reference potential REF, and the second terminal of transistor T2 is coupled to node N2. In this embodiment, the reference potential REF is the gate low voltage (VGL), but it is not limited thereto. In this paper, the "control terminal", "first terminal" and "second terminal" of a transistor refer to the gate, source and drain of the transistor, respectively, or the gate, drain and source of the transistor, respectively.

[0036] Pull-up unit driver stage 320 is coupled to reset unit 310 and pull-up unit 330. It receives input signals INT1 and INT2 and outputs pull-up drive signal PC(i) from node N1 according to input signals INT1 and INT2. Pull-up unit driver stage 320 includes transistors T3 and T4. The control terminal of transistor T3 receives input signal INT1, the first terminal of transistor T3 receives forward input signal FW, and the second terminal of transistor T3 outputs pull-up drive signal PC(i). The control terminal of transistor T4 receives input signal INT2, the first terminal of transistor T4 receives inverted input signal BW, and the second terminal of transistor T4 is coupled to the second terminal of transistor T3. The first to Nth stage shift registers 300(1)~300(N) can perform forward or reverse scanning of display panel 200 according to the potential switching state of forward input signal FW and inverted input signal BW.

[0037] If the i-th level shift register 300(i) of the shift registers 300(1) to 300(N) of the first to Nth levels is one of the shift registers 300(1) to 300(4) of the first to fourth levels (i.e. i is 1, 2, 3 or 4), then the input signal INT1 is the start signal, and the input signal INT2 is the scan signal OUT(i+4) output by the shift register 300(i+4) of the (i+4)th level (i+4) (e.g., the 7th level scan signal OUT(7) or the 8th level scan signal OUT(8)). If the i-th level shift register 300(i) is one of the 5th to (N-2)th level shift registers 300(5)~300(N-2) (i.e., i is any positive integer from 5 to (N-2), then the input signals INT1 and INT2 are the (i-6)th level scan signal OUT(i-6) output by the (i-6)th level shift register 300(i-6) and the (i+2)th level scan signal OUT(i+2) output by the (i+2)th level shift register 300(i+2), respectively. If the i-th level shift register 300(i) is the (N-1)-th level shift register 300(N-1) or the N-th level shift register 300(N) (i.e., i is (N-1) or N), then the input signal INT1 is the scan signal OUT(i-5) output by the (i-5)-th level shift register 300(i-5) (i.e., the (N-5)-th level scan signal OUT(N-5) or the (N-4)-th level scan signal OUT(N-4)), and the input signal INT2 is the end signal.

[0038] It is worth mentioning that when the i-th level shift register 300(i) of the shift registers 300(1) to 300(N) of the first to Nth levels is in forward scan, that is, when the forward input signal FW is at a high level and the reverse input signal BW is at a low level, signal STV1 is the start signal and signal STV2 is the end signal. When the i-th level shift register 300(i) of the shift registers 300(1) to 300(N) of the first to Nth levels is in reverse scan, that is, when the forward input signal FW is at a low level and the reverse input signal BW is at a high level, signal STV2 is the start signal and signal STV1 is the end signal.

[0039] Pull-up unit 330 is coupled to pull-up unit driver stage 320. It receives pull-up drive signal PC(i) and multiple clock signals CK, and outputs the i-th level scan signal OUT(i) from node N2 according to the pull-up drive signal PC(i) and clock signals CK, where the clock signal CK is any one of clock signals C1~C6 or C1~C8. Pull-up unit 330 includes transistor T5 and capacitor Cx. The control terminal of transistor T5 receives the pull-up drive signal PC(i), the first terminal of transistor T5 receives the clock signal CK, and the second terminal of transistor T5 outputs the i-th level scan signal OUT(i). The first terminal of capacitor Cx is coupled to the control terminal of transistor T5, and the second terminal of capacitor Cx is coupled to the second terminal of transistor T5.

[0040] Discharge unit 340 is coupled to pull-up unit driver stage 320 and pull-up unit 330. It receives pull-up drive signal PC(i), discharge control signal GPW1, and discharge control signal GPW2, and controls whether to pull down the i-th level scan signal OUT(i) to and maintain it at the reference potential REF according to the pull-up drive signal PC(i), discharge control signal GPW1, and discharge control signal GPW2. Discharge unit 340 includes transistors T6 to T10. The control terminal and its first terminal of transistor T6 input the discharge control signal GPW1, and the second terminal of transistor T6 is coupled to node N3. The control terminal of transistor T7 inputs the discharge control signal GPW2. The first terminal of transistor T7 is coupled to the reference potential REF, and the second terminal of transistor T7 is coupled to the second terminal of transistor T6. The control terminal of transistor T8 is coupled to node N3, and the first terminal of transistor T8 is coupled to the reference potential REF. The control terminal of transistor T9 is coupled to node N3, the first terminal of transistor T9 is coupled to the reference potential REF, and the second terminal of transistor T9 receives the i-th scan signal OUT(i). The first terminal of transistor T10 is coupled to node N3, and the second terminal of transistor T10 is coupled to the reference potential REF.

[0041] Please refer to Figure 3B, which is another example of the equivalent circuit diagram of the i-th stage shift register 300(i) of Figure 1, where i is a positive integer from 1 to N. The example in Figure 3B is similar to that in Figure 3A. The difference between the example in Figure 3B and that in Figure 3A is as follows. As shown in Figure 3B, the i-th stage shift register 300(i) does not include the reset unit 310, while other features are similar to those in the example in Figure 3A, and will not be repeated here.

[0042] Please refer to Figures 4A to 4D. Figure 4A is a cross-sectional view of the panel structure 400 in the display panel 200 of Figure 1, and Figures 4B to 4D are top views of Figure 4A at different stages. The panel structure 400 includes a first metal layer M1, a gate insulating layer GI, a semiconductor layer SE, a second metal layer M2, a first insulating layer PV1, a lower electrode layer BITO, a second insulating layer PV2, and an upper electrode layer TITO, which are sequentially disposed on a substrate 420.

[0043] The first metal layer M1 can be composed of copper, aluminum, molybdenum, chromium, and / or other suitable conductive materials, and can be formed by processes such as film deposition, exposure, and etching. Alternatively, the first metal layer M1 can also be a stacked layer of multiple conductive material layers, such as a film composed of three conductive material layers sequentially stacked: indium tin oxide (ITO), silver, and ITO. The gate insulating layer GI can be composed of inorganic insulating materials, such as silicon nitride or other suitable materials, and can be formed on the first metal layer M1 by processes such as molding. The semiconductor layer SE can be an undoped semiconductor layer or a doped semiconductor layer. The undoped semiconductor layer can be made of amorphous silicon, monocrystalline silicon, polycrystalline silicon, or other suitable materials, while the doped semiconductor layer can be made of doped amorphous silicon, doped monocrystalline silicon, doped polycrystalline silicon, or other suitable materials. The semiconductor layer SE can be formed on the gate insulating layer GI by processes such as molding, exposure, and etching. The second metal layer M2 can be composed of copper, aluminum, molybdenum, chromium, and / or other suitable conductive materials. Similarly, the second metal layer M2 can also be a multilayer conductive stack, such as a film layer composed of three conductive material layers sequentially stacked: indium tin oxide (ITO), silver, and ITO. It can be formed on the gate insulating layer GI and the semiconductor layer SE by processes such as film deposition, exposure, and etching. The first metal layer M1 includes a gate G, and the second metal layer M2 includes a source S and a drain D. The gate G, a portion of the gate insulating layer GI, the semiconductor layer SE, the source S, and the drain D constitute a thin-film transistor (TFT). The first insulating layer PV1 can be composed of inorganic insulating materials, such as silicon nitride, silicon oxynitride, combinations thereof, and / or other suitable materials. In other embodiments, the first insulating layer PV1 can be composed of organic insulating materials, such as acrylic, siloxane, polyimide, epoxy resin, combinations thereof, and / or other suitable materials. The first insulating layer PV1 can be formed on the second metal layer M2 by a process such as film deposition. The lower electrode layer BITO can be composed of indium tin oxide (ITO), indium zinc oxide (IZO), antimony tin oxide (ATO), fluorine tin oxide (FTO), tin oxide, zinc oxide, graphene, combinations thereof, and / or other suitable transparent conductive materials, and can be formed on the first insulating layer PV1 by processes such as film deposition, exposure, and etching. The second insulating layer PV2 can be composed of inorganic insulating materials, such as silicon nitride, silicon nitride, silicon oxynitride, combinations thereof, and / or other suitable materials. In other embodiments, the second insulating layer PV2 can be composed of organic insulating materials, such as acrylic, silicate, polyimide, epoxy resin, combinations thereof, and / or other suitable materials.The second insulating layer PV2 can be formed on the lower electrode layer BITO by processes such as film deposition, exposure, and etching. The upper electrode layer TITO can be composed of indium tin oxide, indium zinc oxide, tin oxide, tin oxide, zinc oxide, graphene, combinations thereof, and / or other suitable transparent conductive materials, and can be formed on the second insulating layer PV2 by processes such as film deposition, exposure, and etching. The upper electrode layer TITO can contact and electrically connect some components in the first metal layer M1, the second metal layer M2, and the lower electrode layer BITO.

[0044] It is worth mentioning that the second metal layer M2 is disposed above the first metal layer M1 in the Z direction and overlaps the first metal layer M1 in the Z direction. Therefore, the first metal layer M1, the second metal layer M2, and the gate insulating layer GI located between the first metal layer M1 and the second metal layer M2 can form a sub-capacitor Cx1. The lower electrode layer BITO is disposed above the second metal layer M2 in the Z direction and overlaps the second metal layer M2 in the Z direction. Therefore, the lower electrode layer BITO, the second metal layer M2, and the first insulating layer PV1 located between the lower electrode layer BITO and the second metal layer M2 can form a sub-capacitor Cx2. The upper electrode layer TITO is disposed above the lower electrode layer BITO in the Z direction and overlaps the lower electrode layer BITO in the Z direction. Therefore, the upper electrode layer TITO, the lower electrode layer BITO, and the second insulating layer PV2 located between the upper electrode layer TITO and the lower electrode layer BITO can form a sub-capacitor Cx3.

[0045] Please refer to Figure 5, which is a schematic diagram of the capacitor Cx in Figure 4A. For ease of explanation, Figure 5 only shows the parallel structure S1 of the first metal layer M1, the second metal layer M2, the first insulating layer PV1, the lower electrode layer BITO, the second insulating layer PV2, and the upper electrode layer TITO. In this embodiment, the second insulating layer PV2 may include multiple via structures TH, allowing the first metal layer M1, the second metal layer M2, the lower electrode layer BITO, and the upper electrode layer TITO to be interconnected via the via structures TH. The lower electrode layer BITO and the upper electrode layer TITO can respectively receive a common signal and a pixel signal. Specifically, in sub-capacitor Cx2, the lower electrode layer BITO can first be connected to the upper electrode layer TITO and then to the first metal layer M1, so that sub-capacitor Cx2 can be electrically connected to sub-capacitor Cx1. In sub-capacitor Cx3, the upper electrode layer TITO can be connected to the second metal layer M2, so that sub-capacitor Cx3 can be electrically connected to sub-capacitor Cx2. Therefore, capacitor Cx can be formed by connecting capacitors Cx1, Cx2, and Cx3 in parallel, and capacitor Cx can store the voltage change between the common signal and the pixel signal. Furthermore, designing capacitor Cx as a parallel structure S1 of three layers of capacitors can increase the tolerance to variations in the critical voltage (Vth) of the i-th stage shift register 300(i).

[0046] Please refer to Figures 6A and 6B together. Figures 6A and 6B are examples of forward timing diagrams for the first to Nth stage shift registers 300(1)~300(N) of Figure 1, where Figure 6A shows a right-side scan and Figure 6B shows a left-side scan. The equivalent circuits of the first to Nth stage shift registers 300(1)~300(N) can be shown in Figure 3A or Figure 3B. In this embodiment, the equivalent circuit of Figure 3A is used as an example, and the equivalent circuit of Figure 3B can be deduced by analogy and will not be described again.

[0047] As shown in Figure 6A, shift registers 300(1) to 300(N) of stages 1 to N are in forward scanning. During the operation of frame time FR1, OP, the forward input signal FW maintains a gate high voltage (VGH), while the reverse input signal BW maintains a gate low voltage, so as to discharge the array substrate row drive circuit structure. At the same time, clock signals C1 to C6 are sequentially raised to a high potential, so that the corresponding scan signals OUT(1) to OUT(N) of stages 1 to N are raised to a high potential. Clock signals C1 to C6 are sequentially lowered to a low potential, so that the corresponding scan signals OUT(1) to OUT(N) of stages Ni to N are lowered to a low potential. The signal period of clock signals C1 to C6 is 12 data write times, where the data write time is defined as the time during which each of the shift registers 300(1) to 300(N) of stages 1 to N drives a corresponding pixel column in the display panel 200 in each frame time. It is worth mentioning that the high potential of clock signals C1~C6 is maintained for 5 data write times, the low potential of clock signals C1~C6 is maintained for 7 data write times, and there needs to be an interval of one data write time between clock signals C1 and C4, clock signals C2 and C5, and clock signals C3 and C6.

[0048] After the scan signals OUT(1)~OUT(N) from level 1 to level N are sequentially raised to high and lowered to low, signal STV2 undergoes a potential switch. Within each frame time, the potential switch point of signal STV2 precedes the potential switch points of signals STV1 and the reset signal RST, where signal STV2 is the end signal. For example, during the operation period OP of frame time FR1 and before the entry point TP1 into blank time BT, signal STV2 rises from low to high and then falls from high to low to complete the data input within frame time FR1, where the high potential of signal STV2 is maintained for 5 data write times.

[0049] Next, the blank period BT of frame time FR1 is entered. The reset signal RST is switched at time TP2 during the blank period BT of frame time FR1, wherein the time point of the reset signal RST is before the time point of the signal STV1. For example, at time TP2 during the blank period BT of frame time FR1, the reset signal RST rises from a low potential to a high potential to turn on transistors T1 and T2, thereby resetting the potentials of nodes N1 and N2 of each shift register 300(1) to 300(N) of stage 1 to stage N to a low potential, and after the potential reset of nodes N1 and N2 is completed, the reset signal RST drops from a high potential to a low potential, wherein the high potential of the reset signal RST is maintained for 5 data write times.

[0050] Next, we proceed to frame time FR2. Signal STV1 rises from low to high, and clock signals C1~C6 rise to high in sequence, causing the level 1 to level N scan signals OUT(1)~OUT(N) to rise to high in sequence. Clock signals C1~C6 then fall to low in sequence, causing the level 1 to level N scan signals OUT(1)~OUT(N) to fall to low in sequence. The high level of signal STV1 is maintained for 5 data write times, and signal STV1 falls to low before clock signal C1. During the subsequent period of frame time FR2, the timing of clock signals C1~C6, signal STV2, lower reset signal RST, signal STV1, and level 1 to level N scan signals OUT(1)~OUT(N) is the same as the timing in frame time FR1.

[0051] It is worth mentioning that the discharge control signals GPW1 and GPW2 switch between high and low potentials during each frame time and at the end of each frame time on the display panel 200. Within each frame time, the discharge control signals GPW1 and GPW2 are inversely related, meaning one of them is at a high potential while the other is at a low potential. More specifically, the high-low potential switching of the discharge control signals GPW1 and GPW2 during each frame time and at the end of each frame time on the display panel 200 includes the high-low potential switching of either GPW1 or GPW2 at the first point in time during the blank period of each frame time on the display panel 200. For example, during the blank period BT of frame time FR1, at time point TP1, the discharge control signal GPW1 can switch from gate high voltage to gate low voltage, and the discharge control signal GPW2 can switch from gate low voltage to gate high voltage. The potential switching time of discharge control signal GPW1 is substantially the same as the potential switching time of discharge control signal GPW2, and the potential switching times of discharge control signals GPW1 and GPW2 are substantially the same as the potential switching time of signal STV2 when it drops from high to low potential. Furthermore, the high / low potential switching of discharge control signals GPW1 and GPW2 during each frame time of the display panel 200 and at the end of each frame time includes the high / low potential switching of discharge control signals GPW1 or GPW2 at a second time point during the blank period of each frame time of the display panel 200. For example, during the blank period BT of the frame time FR1, at time point TP2, the discharge control signal GPW1 can switch from gate low voltage to gate high voltage, and the discharge control signal GPW2 can switch from gate high voltage to gate low voltage. The potential switching time of the discharge control signal GPW1 is substantially the same as the potential switching time of the discharge control signal GPW2, and the potential switching time of the discharge control signals GPW1 and GPW2 is substantially the same as the potential switching time of the reset signal RST rising from low potential to high potential.

[0052] Please refer to Figures 6C and 6D together. Figures 6C and 6D are examples of reverse timing diagrams of the first to Nth stage shift registers 300(1)~300(N) of Figure 1, where Figure 6C is a right-side scan and Figure 6D is a left-side scan. The equivalent circuits of the first to Nth stage shift registers 300(1)~300(N) can be shown in Figure 3A or Figure 3B. In this embodiment, the equivalent circuit of Figure 3A is used as an example, and the equivalent circuit of Figure 3B can be deduced by analogy and will not be described again.

[0053] As shown in Figures 6C and 6D, the shift registers 300(1) to 300(N) of the first to Nth stages are in reverse scan mode. During the operation of frame time FR1, OP, the forward input signal FW maintains a low gate voltage, while the reverse input signal BW maintains a high gate voltage, so as to discharge the array substrate row drive circuit structure. At the same time, the clock signals C6 to C1 are sequentially raised to a high potential, so that the scan signals OUT(N) to OUT(1) of the Nth to 1st stages are raised to a high potential. The clock signals C6 to C1 are sequentially lowered to a low potential, so that the scan signals OUT(N) to OUT(1) of the Nth to 1st stages are lowered to a low potential. The signal period of the clock signals C6 to C1 is 12 data write times, where the data write time is defined as the time during which each of the shift registers 300(1) to 300(N) of the first to Nth stages drives a corresponding pixel column in the display panel 200 during each frame time. It is worth mentioning that the high potential of clock signals C6~C1 is maintained for 5 data write times, the low potential of clock signals C6~C1 is maintained for 7 data write times, and there needs to be an interval of one data write time between clock signals C1 and C4, clock signals C2 and C5, and clock signals C3 and C6.

[0054] After the Nth to 1st level scan signals OUT(N)~OUT(1) are sequentially raised to high and lowered to low, signal STV1 undergoes a potential switch. The potential switch time of signal STV1 is before the potential switch time of signal STV2 and reset signal RST, where signal STV1 is the end signal. For example, during the operation period OP of frame time FR1 and before the time point TP1 of blank period BT, signal STV1 rises from low to high and falls from high to low to complete the data input in frame time FR1, where the high potential of signal STV1 is maintained for 5 data write times.

[0055] Next, the blank period BT of frame time FR1 is entered. The reset signal RST is switched at time TP2 during the blank period BT of frame time FR1, wherein the time point of the reset signal RST is before the time point of the signal STV2. For example, at time TP2 during the blank period BT of frame time FR1, the reset signal RST rises from a low potential to a high potential to turn on transistors T1 and T2, thereby resetting the potentials of nodes N1 and N2 of each shift register 300(1) to 300(N) from level 1 to level N to a low potential, and after the potential reset of nodes N1 and N2 is completed, the reset signal RST drops from a high potential to a low potential, wherein the high potential of the reset signal RST is maintained for 5 data write times.

[0056] Next, the frame time FR2 begins. Then, signal STV2 rises from low to high, and clock signals C6~C1 subsequently rise to high, causing the Nth to 1st level scan signals OUT(N)~OUT(1) to rise to high. Clock signals C6~C1 then sequentially fall to low, causing the Nth to 1st level scan signals OUT(N)~OUT(1) to fall to low. The high level of signal STV2 is maintained for 5 data write times, and signal STV2 actually falls to low before clock signal C6. During the subsequent period of frame time FR2, the timing of clock signals C6~C1, signal STV1, lower reset signal RST, signal STV2, and the Nth to 1st level scan signals OUT(N)~OUT(1) is the same as in frame time FR1.

[0057] It is worth mentioning that the discharge control signals GPW1 and GPW2 switch between high and low potentials during each frame time and at the end of each frame time on the display panel 200. Within each frame time, the discharge control signals GPW1 and GPW2 are inversely related, meaning one of them is at a high potential while the other is at a low potential. More specifically, the high-low potential switching of the discharge control signals GPW1 and GPW2 during each frame time and at the end of each frame time on the display panel 200 includes the high-low potential switching of either GPW1 or GPW2 at the first point in time during the blank period of each frame time on the display panel 200. For example, during the blank period BT of frame time FR1, at time point TP1, the discharge control signal GPW1 can switch from gate high voltage to gate low voltage, and the discharge control signal GPW2 can switch from gate low voltage to gate high voltage. The potential switching time of discharge control signal GPW1 is substantially the same as the potential switching time of discharge control signal GPW2, and the potential switching times of discharge control signals GPW1 and GPW2 are substantially the same as the potential switching time of signal STV1 when it drops from high to low potential. Furthermore, the high / low potential switching of discharge control signals GPW1 and GPW2 during each frame time of the display panel 200 and at the end of each frame time includes the high / low potential switching of discharge control signals GPW1 or GPW2 at a second time point during the blank period of each frame time of the display panel 200. For example, during the blank period BT of the frame time FR1, at time point TP2, the discharge control signal GPW1 can switch from gate low voltage to gate high voltage, and the discharge control signal GPW2 can switch from gate high voltage to gate low voltage. The potential switching time of the discharge control signal GPW1 is substantially the same as the potential switching time of the discharge control signal GPW2, and the potential switching time of the discharge control signals GPW1 and GPW2 is substantially the same as the potential switching time of the reset signal RST rising from low potential to high potential.

[0058] Please refer to Figures 7A and 7B together. Figures 7A and 7B are another example of the forward timing diagrams of the first to Nth stage shift registers 300(1)~300(N) in Figure 1, where Figure 7A is a right-side scan and Figure 7B is a left-side scan. The equivalent circuits of the first to Nth stage shift registers 300(1)~300(N) can be shown in Figure 3A or Figure 3B. In this embodiment, the equivalent circuit of Figure 3A is used as an example, and the equivalent circuit of Figure 3B can be deduced by analogy and will not be described again.

[0059] As shown in Figures 7A and 7B, shift registers 300(1) to 300(N) of levels 1 to N are in forward scanning. During the operation of frame time FR1, OP, the forward input signal FW maintains a high gate voltage, while the reverse input signal BW maintains a low gate voltage, so as to discharge the array substrate row drive circuit structure. At the same time, clock signals C1 to C8 are sequentially raised to a high potential, so that the corresponding scan signals OUT(1) to OUT(N) of levels 1 to N are raised to a high potential. Clock signals C1 to C8 are sequentially lowered to a low potential, so that the corresponding scan signals OUT(1) to OUT(N) of levels 1 to N are lowered to a low potential. The signal period of clock signals C1 to C8 is 16 data write times, where the data write time is defined as the time during which each of the shift registers 300(1) to 300(N) of levels 1 to N drives a corresponding pixel column in the display panel 200 in each frame time. It is worth mentioning that the high potential of clock signals C1~C8 is maintained for 6 data write times, the low potential of clock signals C1~C8 is maintained for 10 data write times, and there needs to be an interval of one data write time between clock signals C1 and C4, clock signals C2 and C5, and clock signals C3 and C6.

[0060] After the scan signals OUT(1)~OUT(N) from level 1 to level N are sequentially raised to high and lowered to low, signal STV2 switches its potential. Within each frame time, the potential switching point of signal STV2 precedes the potential switching points of signal STV1 and the reset signal RST, where signal STV2 is the end signal. For example, during the operation period OP of frame time FR1 and before the entry point TP1 into blank time BT, signal STV2 rises from low to high and then falls from high to low to complete the data input within frame time FR1, where the high potential of signal STV2 is maintained for 6 data write times.

[0061] Next, the blank period BT of frame time FR1 is entered. The reset signal RST is switched at time TP2 during the blank period BT of frame time FR1, wherein the time point of the reset signal RST is before the time point of the signal STV1. For example, at time TP2 during the blank period BT of frame time FR1, the reset signal RST rises from a low potential to a high potential to turn on transistors T1 and T2, thereby resetting the potentials of nodes N1 and N2 of each shift register 300(1) to 300(N) of stage 1 to stage N to a low potential, and after the potential reset of nodes N1 and N2 is completed, the reset signal RST drops from a high potential to a low potential, wherein the high potential of the reset signal RST is maintained for 6 data write times.

[0062] Next, the frame time FR2 begins. One data time interval separates the potential switching point where the reset signal RST drops from high to low. Signal STV1 rises from low to high and then drops from high to low. The high potential of signal STV1 is maintained for 6 data write time intervals. In fact, signal STV1 drops from high to low before clock signal C1 drops from high to low. Next, clock signals C1 to C8 rise to high in sequence, causing the level 1 to N level scan signals OUT(1) to OUT(N) to rise to high in frame time FR2. Simultaneously, the level 1 scan signal OUT(1) rises to high, and frame time FR2 begins. Then, clock signals C1 to C8 drop to low in sequence, causing the level 1 to N level scan signals OUT(1) to drop to low. During the period following frame time FR2, the timing of clock signals C1~C8, signal STV2, lower reset signal RST, signal STV1, and level 1 to level N scan signals OUT(1)~OUT(N) are the same as the timing in frame time FR1.

[0063] It is worth mentioning that the discharge control signals GPW1 and GPW2 switch between high and low potentials during each frame time and at the end of each frame time on the display panel 200. Within each frame time, the discharge control signals GPW1 and GPW2 are inversely related, meaning one of them is at a high potential while the other is at a low potential. More specifically, the high-low potential switching of the discharge control signals GPW1 and GPW2 during each frame time and at the end of each frame time on the display panel 200 includes the high-low potential switching of either GPW1 or GPW2 at the first point in time during the blank period of each frame time on the display panel 200. For example, during the blank period BT of frame time FR1, at time point TP1, the discharge control signal GPW1 can switch from gate high voltage to gate low voltage, and the discharge control signal GPW2 can switch from gate low voltage to gate high voltage. The potential switching time of discharge control signals GPW1 and GPW2 is after the potential switching time of signal STV2, which drops from high to low potential. The signal period of discharge control signals GPW1 and GPW2 is approximately 2 seconds. Furthermore, the high / low potential switching of discharge control signals GPW1 and GPW2 during each frame time of the display panel 200 and at the end of each frame time includes the high / low potential switching of discharge control signals GPW1 or GPW2 at a second time point during the blank period of each frame time of the display panel 200. For example, during the blank period BT at time TP2 of frame time FR1, the discharge control signal GPW1 can switch from gate low voltage to gate high voltage, and the discharge control signal GPW2 can switch from gate high voltage to gate low voltage. The potential switching time of discharge control signals GPW1 and GPW2 can be substantially the same as the potential switching time of reset signal RST rising from low potential to high potential. In addition, there is a data hold time DH1 between discharge control signal GPW1 or GPW2 and the Nth level scan signal OUT(N) to ensure that the data in frame time FR1 can be completely input, wherein the data hold time DH1 is 2.5 microseconds.

[0064] In another embodiment, the potential switching time of the discharge control signal GPW1 may be approximately 2.5 microseconds apart from the potential switching time of the discharge control signal GPW2.

[0065] Please refer to Figures 7C and 7D together. Figures 7C and 7D are examples of reverse timing diagrams of the first to Nth stage shift registers 300(1) to 300(N) of Figure 1, where Figure 7C is a right-side scan and Figure 7D is a left-side scan. The equivalent circuits of the first to Nth stage shift registers 300(1) to 300(N) can be shown in Figure 3A or Figure 3B. In this embodiment, the equivalent circuit of Figure 3A is used as an example, and the equivalent circuit of Figure 3B can be deduced by analogy and will not be described again.

[0066] As shown in Figures 7C and 7D, the shift registers 300(1) to 300(N) of the first to Nth stages are in reverse scan mode. During the operation of frame time FR1, OP, the forward input signal FW maintains a low gate voltage, while the reverse input signal BW maintains a high gate voltage, so as to discharge the array substrate row drive circuit structure. At the same time, the clock signals C8 to C1 are sequentially raised to a high potential, so that the scan signals OUT(N) to OUT(1) of the Nth to 1st stages are raised to a high potential. The clock signals C8 to C1 are sequentially lowered to a low potential, so that the scan signals OUT(N) to OUT(1) of the Nth to 1st stages are lowered to a low potential. The signal period of the clock signals C8 to C1 is 16 data write times, where the data write time is defined as the time during which each of the shift registers 300(1) to 300(N) of the first to Nth stages drives a corresponding pixel column in the display panel 200 during each frame time. It is worth mentioning that the high potential of clock signals C8~C1 is maintained for 5 data write times, and the low potential of clock signals C8~C1 is maintained for 11 data write times.

[0067] After the Nth to 1st level scan signals OUT(N)~OUT(1) are sequentially raised to high and lowered to low, signal STV1 undergoes a potential switch. The potential switch time of signal STV1 is before the potential switch time of signal STV2 and reset signal RST, where signal STV1 is the end signal. For example, during the operation period OP of frame time FR1 and before the entry point TP1 of blank period BT, signal STV1 rises from low to high and falls from high to low to complete the data input in frame time FR1, where the high potential of signal STV1 is maintained for 5 data write times.

[0068] Next, the blank period BT of frame time FR1 is entered. The reset signal RST is switched at time TP2 during the blank period BT of frame time FR1, wherein the time point of the reset signal RST is before the time point of the signal STV2. For example, at time TP2 during the blank period BT of frame time FR1, the reset signal RST rises from a low potential to a high potential to turn on transistors T1 and T2, thereby resetting the potentials of nodes N1 and N2 of each shift register 300(1) to 300(N) from level 1 to level N to a low potential, and after the potential reset of nodes N1 and N2 is completed, the reset signal RST drops from a high potential to a low potential, wherein the high potential of the reset signal RST is maintained for 5 data write times.

[0069] Next, the frame time FR2 is entered. One data time interval is elapsed between the potential switching point where the reset signal RST drops from high to low. Signal STV2 rises from low to high, maintaining its high level for 5 data write times. Signal STV2 actually drops from high to low before clock signal C8 drops from high to low. Then, the frame time FR2 is entered again. Clock signals C8~C1 rise to high in sequence, causing the corresponding scan signals OUT(N)~OUT(1) from level N to level 1 to rise to high. Clock signals C8~C1 then drop to low in sequence, causing the corresponding scan signals OUT(N)~OUT(1) from level N to level 1 to drop to low. During the period following frame time FR2, the timing of clock signals C8~C1, signal STV1, lower reset signal RST, signal STV2, and the Nth to 1st level scan signals OUT(1)~OUT(N) are the same as the timing in frame time FR1.

[0070] It is worth mentioning that the discharge control signals GPW1 and GPW2 switch between high and low potentials within each frame time and at the end of each frame time on the display panel 200. Within each frame time, the discharge control signals GPW1 and GPW2 are inversely related, meaning one of them is at a high potential while the other is at a low potential. Specifically, the high-low potential switching of the discharge control signals GPW1 and GPW2 within each frame time and at the end of each frame time on the display panel 200 includes the switching of either GPW1 or GPW2 at the first point in the blank period of each frame time on the display panel 200. For example, at point TP1 of the blank period BT of frame time FR1, the discharge control signal GPW1 can switch from a high gate voltage to a low gate voltage, and the discharge control signal GPW2 can switch from a low gate voltage to a high gate voltage. The signal period of the discharge control signals GPW1 and GPW2 is approximately 2 seconds. The potential switching time of discharge control signals GPW1 or GPW2 is substantially the same as the potential switching time of signal STV1 from high potential to low potential. Furthermore, the high / low potential switching of discharge control signals GPW1 and GPW2 during each frame time and at the end of each frame time in the display panel 200 includes a second point in time during the blank period of each frame time in the display panel 200 when discharge control signals GPW1 or GPW2 switch high / low potential. For example, at point TP2 of the blank period BT of frame time FR1, discharge control signal GPW1 can switch from gate low voltage to gate high voltage, and discharge control signal GPW2 can switch from gate high voltage to gate low voltage. The potential switching time of discharge control signal GPW1 is substantially the same as the potential switching time of discharge control signal GPW2, and the potential switching time of discharge control signals GPW1 and GPW2 is substantially the same as the potential switching time of reset signal RST from low potential to high potential. Furthermore, a data hold time DH2 exists between the discharge control signal GPW1 or GPW2 and the first-level scan signal OUT(1) to ensure that the data in the frame time FR1 can be completely input, wherein the data hold time DH2 is 2.5 microseconds. In another embodiment, the potential switching time of the discharge control signal GPW1 may be approximately 2.5 microseconds apart from the potential switching time of the discharge control signal GPW2.

[0071] Please refer to Figure 8, which is a voltage-time diagram of the discharge control signals GPW1 and GPW2 of the first to Nth stage shift registers 300(1)-300(N) in the scan drive circuit 300 of Figure 1. In the prior art, if a positive bias voltage drive or a negative bias voltage drive is continuously applied to a shift circuit using thin-film transistors as components, the multiple thin-film transistor elements in the shift circuit will exhibit instability in critical voltage shift (Vth shift). For example, if a positive bias voltage drive is continuously applied, the critical voltages of the multiple thin-film transistor elements in the shift circuit will gradually shift to the right. In other words, the critical voltages of these thin-film transistor elements become larger. If a negative bias voltage drive is continuously applied, the critical voltages of the multiple thin-film transistor elements in the shift circuit will gradually shift to the left. In other words, the critical voltages of these thin-film transistor elements become smaller. However, the degree of critical voltage shift will seriously affect the normal operation of the scan shift circuit. For example, a larger critical voltage makes it difficult for thin-film transistors to conduct, while a smaller critical voltage makes it difficult for thin-film transistors to turn off, which in turn causes problems such as insufficient drive current or excessive leakage current in the shift circuit.

[0072] Therefore, to avoid the above problems, the scan drive circuit 300 can adopt a drive method that automatically corrects the critical voltage value offset. Taking the example of the discharge control signal GPW1 being first applied a first gate high voltage and then a first gate low voltage, and the discharge control signal GPW2 being first applied a second gate high voltage and then a second gate low voltage, other voltage implementation methods can be deduced by analogy and will not be elaborated here. Specifically, during the operation period OP of frame time FR1, the discharge control signal GPW1 can be continuously applied a first gate high voltage, and the discharge control signal GPW2 can be continuously applied a second gate low voltage, making node N3 positively biased, thereby causing the critical voltages of transistors T8 and T9 to gradually shift to the right. In other words, during the operation period OP of frame time FR1, the critical voltages of transistors T8 and T9 gradually increase. During the blank period BT of frame time FR1, the discharge control signal GPW1 can be continuously supplied with a first gate low voltage, and the discharge control signal GPW2 can be continuously supplied with a second gate high voltage, making node N3 negatively biased (e.g., reference potential REF), thereby causing the critical voltages of transistors T8 and T9 to gradually shift to the left. In other words, during the blank period BT of frame time FR1, the critical voltages of transistors T8 and T9 can gradually decrease from a larger critical voltage, allowing the critical voltages of transistors T8 and T9 to automatically recover. In this way, through the voltage changes of discharge control signals GPW1, GPW2, and node N3, the shift in the critical voltage values ​​of transistors T8 and T9 can be mitigated, effectively improving the reliability of the scan drive circuit 300. During frame time FR2, the voltage changes of discharge control signals GPW1 and GPW2 are the same as those during frame time FR1, and will not be described again here.

[0073] In summary, the display device of the present invention achieves a narrow bezel effect in dual-gate and triple-gate driven panel technologies through the configuration of the various circuit units in the shift register. By designing the capacitors of the pull-up units in the shift register as a three-layer capacitor structure, the tolerance to variations in the critical voltage (Vth) of the components in the shift register is increased. Furthermore, the discharge control signal received by the discharge unit in the shift register can be designed to switch between high and low potentials during each frame time of the display panel and at the end of each frame time, thereby controlling the offset of the critical voltage value of the components in the shift register and slowing down the aging rate of the critical voltage value. This effectively improves the reliability of the shift register.

[0074] Although the present invention has been disclosed above by way of embodiments, it is not intended to limit the present invention. Anyone skilled in the art can make some modifications and refinements without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be determined by the appended claims.

[0075] 100: Display device 200: Display panel 220: Pixel SP1, SP2, SP3: sub-pixel 300: Scan drive circuit 300(1)~300(N),300(i): Shift registers 310: Reset Unit 320: Pull-up unit driver stage 330: Pull-up unit 340: Discharge Unit 400: Panel Architecture 420:Substrate BW: Reverse Input Signal BT: Blank Period BITO: Lower Electrode Layer Cx, Cx1, Cx2, Cx3: Capacitors CK, C1~C8: Clock signals D: Jiji D1~D5: Data Line DH1, DH2: Data retention time FW: Forward Input Signal FR1, FR2: Timing of the drawing frame OUT(1)~OUT(N),OUT(i): Scan signal INT1, INT2: Input signals G: Gate GI: Gate Insulation Layer GPW1, GPW2: Discharge control signals G1~G10: Gate wires L1, L2: rows N1, N2, N3: Nodes M1: First metal layer M2: Second metal layer OP: During operation PC(i): Pull-up drive signal PV1, PV2: Insulation layer R1~R8: Columns REF: Reference potential RST: Reset signal S: Source SE: Semiconductor layer STV1, STV2, STV3: Signal S1: Parallel structure T1~T10: Transistors TITO: Top electrode layer TH: Through-hole structure TP1, TP2: Time points Z: Direction

Claims

1. A display device, comprising: a display panel; and shift registers of levels 1 to N for driving the display panel, wherein one of the shift registers of level 1 to N, at level i, includes: a pull-up unit driver stage, receiving a first input signal and a second input signal, and outputting a pull-up drive signal from a first node according to the first input signal and the second input signal; A pull-up unit, coupled to the pull-up unit driver stage, receives the pull-up drive signal and a plurality of clock signals, and outputs an i-th level scan signal from a second node according to the pull-up drive signal and the clock signals; and a discharge unit, coupled to the pull-up unit driver stage and the pull-up unit, receives the pull-up drive signal, a first discharge control signal and a second discharge control signal, and controls whether to pull down the i-th level scan signal to and maintain it at a reference potential according to the pull-up drive signal, the first discharge control signal and the second discharge control signal; wherein the first discharge control signal and the second discharge control signal switch between high and low potentials during each frame time of the display panel and at the end of each frame time.

2. The display device as claimed in claim 1, wherein during each frame time, the potential switching time of the second input signal precedes the potential switching time of the first input signal.

3. The display device as claimed in claim 1, wherein during each frame time, the potential switching time of the second input signal is substantially the same as the potential switching time of the first discharge control signal and the second discharge control signal.

4. The display device as claimed in claim 1, wherein the high-low potential switching of the first discharge control signal and the second discharge control signal during each frame time of the display panel and at the end of each frame time includes the high-low potential switching of the first discharge control signal and the second discharge control signal during a blanking period of each frame time of the display panel at a first point in time.

5. The display device as claimed in claim 1, wherein the high-low potential switching of the first discharge control signal and the second discharge control signal during each frame time of the display panel and at the end of each frame time includes the high-low potential switching of the first discharge control signal or the second discharge control signal during a blank period of each frame time of the display panel at a second time point.

6. The display device as claimed in claim 1, wherein the signal period of the clock signals is 12 data write times, wherein the data write time is defined as the time during which each of the first to Nth level shift registers drives a corresponding pixel column in the display panel in each frame time.

7. The display device as claimed in claim 1, wherein the potential switching time of the first discharge control signal is approximately 2.5 microseconds apart from the potential switching time of the second discharge control signal.

8. The display device as claimed in claim 1, wherein the signal period of the first discharge control signal and the second discharge control signal is approximately 2 seconds.

9. The display device as claimed in claim 1, wherein the first discharge control signal or the second discharge control signal has a data hold time of 2.5 microseconds between it and the i-th level scan signal.

10. The display device as claimed in claim 1, wherein the signal period of the clock signals is 16 data write times, wherein the data write time is defined as the time during which each of the first to Nth level shift registers drives a corresponding pixel column in the display panel in each frame time.

11. The display device as claimed in claim 1 further comprises: a reset unit coupled to the pull-up unit driver stage, the pull-up unit, and the discharge unit, the reset unit receiving a reset signal and resetting the potentials of the first node and the second node in each frame time of the display panel after sequentially scanning a plurality of pixel rows of the display panel according to the reset signal.

12. The display device as claimed in claim 11, wherein the reset unit comprises: a first transistor having a control terminal that receives the reset signal, a first terminal of which is coupled to the reference potential, and a second terminal of which is coupled to the first node; and a second transistor having a control terminal coupled to the control terminal of the first transistor, a first terminal of which is coupled to the reference potential, and a second terminal of which is coupled to the second node.

13. The display device as claimed in claim 11, wherein when the i-th stage shift register is in forward scanning, in each frame time, the potential switching time of the first discharge control signal and the potential switching time of the second discharge control signal are after the potential switching time of the second input signal and are substantially the same as the potential switching time of the reset signal.

14. The display device as claimed in claim 11, wherein when the i-th stage shift register is in reverse scan, during each frame time, the potential switching time of the first discharge control signal and the potential switching time of the second discharge control signal are substantially the same as the potential switching time of the first input signal and substantially the same as the potential switching time of the reset signal.

15. The display device as claimed in claim 11, wherein during each frame time, the potential switching time of the first discharge control signal is substantially the same as the potential switching time of the reset signal.

16. The display device as claimed in claim 1, wherein the pull-up unit driver stage comprises: a third transistor having a control terminal that receives the first input signal, a first terminal that receives a forward input signal, and a second terminal that outputs the pull-up drive signal; and a fourth transistor having a control terminal that receives the second input signal, a first terminal that receives a reverse input signal, and a second terminal that is coupled to the second terminal of the third transistor.

17. The display device as claimed in claim 1, wherein the pull-up unit comprises: a fifth transistor whose control terminal receives the pull-up drive signal, whose first terminal receives the clock signals, and whose second terminal outputs the i-th level scan signal; and a capacitor whose first terminal is coupled to the control terminal of the fifth transistor, and whose second terminal is coupled to the second terminal of the fifth transistor.

18. The display device as claimed in claim 17, wherein the capacitor comprises: a first metal layer; a second metal layer located on the first metal layer, wherein a first sub-capacitor is formed between the first metal layer and the second metal layer; a lower electrode layer located on the first metal layer, wherein a second sub-capacitor is formed between the second metal layer and the lower electrode layer; and an upper electrode layer located on the lower electrode layer, wherein a third sub-capacitor is located between the lower electrode layer and the upper electrode layer.

19. The display device as claimed in claim 1, wherein the discharge unit comprises: a sixth transistor having a control terminal and a first terminal for receiving the first discharge control signal; a seventh transistor having a control terminal for receiving the second discharge control signal, a first terminal coupled to the reference potential, and a second terminal coupled to a second terminal of the sixth transistor; an eighth transistor having a control terminal coupled to a third node, and a first terminal coupled to the reference potential; a ninth transistor having a control terminal coupled to the third node, and a first terminal coupled to the reference potential; and a tenth transistor having a first terminal coupled to the third node, and a second terminal coupled to the reference potential.

20. The display device as claimed in claim 1, wherein the display panel has a dual-gate pixel array structure or a triple-gate pixel array structure.

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