Interface chips, semiconductor memory devices and memory systems

Abstract

This invention improves the access speed of memory chips. The interface chip of this invention can be connected to a memory chip and a memory controller. The memory chip includes a plurality of memory cells and word lines connected to the plurality of memory cells. The interface chip includes a control unit that, upon receiving a first instruction for data readout issued by the memory controller, sends a second instruction corresponding to the first instruction to the memory chip to cause the memory chip to perform a readout operation. When the memory chip finishes the readout operation, before receiving a third instruction for data output issued by the memory controller, a fourth instruction for data output is sent to the memory chip.

Images